CN106531793B - 具有外延层的半导体结构 - Google Patents

具有外延层的半导体结构 Download PDF

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CN106531793B
CN106531793B CN201510577437.6A CN201510577437A CN106531793B CN 106531793 B CN106531793 B CN 106531793B CN 201510577437 A CN201510577437 A CN 201510577437A CN 106531793 B CN106531793 B CN 106531793B
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epitaxial layer
fin
structures
crown
region
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CN106531793A (zh
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许智凯
洪裕祥
傅思逸
童宇诚
郑志祥
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种具有外延层的半导体结构，包含一基底，其上定义有一第一导电型态区域以及一第二导电型态区域，多条第一鳍状结构位于该基底上并位于该第一导电型态区域内，以及多条第二鳍状结构位于该基底上并位于该第二导电型态区域内，多个第一栅极结构位于该第一导电型态区域内，多个第二栅极结构位于该第二导电型态区域内，以及至少两第一冠状外延层，设置于该第一导电型态区域内，以及多个第二外延层，设置于该第二导电型态区域内，该第二外延层的形状与该第一冠状外延层不同。

Description

具有外延层的半导体结构
技术领域
本发明涉及半导体领域，尤其是涉及一种具有多种不同外延层的半导体结构。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的设计仍存在许多瓶颈，除了影响通道区载流子的迁移率之外，又影响元件的整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
本发明提供一种半导体元件，包含一基底，其上定义有一第一导电型态区域以及一第二导电型态区域，多条第一鳍状结构位于该基底上并位于该第一导电型态区域内，以及多条第二鳍状结构位于该基底上并位于该第二导电型态区域内，多个第一栅极结构位于该第一导电型态区域内，横跨该多条第一鳍状结构，以及多个第二栅极结构位于该第二导电型态区域内，横跨该多条第二鳍状结构，以及至少两第一冠状外延层，设置于该第一导电型态区域内，且位于各该第一栅极结构的两侧，以及多个第二外延层，设置于该第二导电型态区域内，位于各该第二栅极结构的两侧，其中该第一冠状外延层位于该第一栅极结构的两侧的一第一凹槽内，该第一凹槽具有一平坦底面，且同时接触该多个第一鳍状结构，另外该第二外延层的形状与该第一冠状外延层不同。
本发明提供一种半导体元件，包含一基底，其上定义有一第一导电型态区域，该第一导电型态区域内包含有一第一区域以及一第二区域，多条第一鳍状结构位于该基底上并位于该第一区域内，以及多条第二鳍状结构位于该基底上并位于该第二区域内，多个第一栅极结构位于该第一区域内，横跨该多条第一鳍状结构，以及多个第二栅极结构位于该第二区域内，横跨该多条第二鳍状结构，以及至少两第一冠状外延层，设置于该第一区域内，且位于各该第一栅极结构的两侧，以及多个第二外延层，设置于该第二区域内，位于各该第二栅极结构的两侧，其中该第一冠状外延层位于该第一栅极结构的两侧的一第一凹槽内，该第一凹槽具有一平坦底面，且同时接触该多个第一鳍状结构,另外该第二外延层的形状与该第一冠状外延层不同。
本发明的特征在于，在同一个半导体结构之中，不同的导电型态区域内，包含有不同形状的外延层。或者是同一个半导体结构的同一个导电型态区域内，包含有不同区域，且各区域分别包含不同形状的外延层。本发明将不同形状的外延层制作于同一半导体结构中，可提高半导体结构在应用上的灵活性。
附图说明
图1至图6为本发明的第一优选实施例的半导体结构的制作方法示意图，其中图4为半导体结构的立体示意图；
图7为本发明的第二优选实施例的半导体结构剖视图；
图8为本发明的第三优选实施例的半导体结构剖视图；
图9为本发明的第四优选实施例的半导体结构剖视图。
主要元件符号说明
10 基底
12 鳍状结构
13 浅沟隔离
14 光致抗蚀剂图案
16 凹槽
20 绝缘层
30 栅极结构
32 栅极介电层
34 栅极导电层
36 帽盖层
100 第一导电型态区域
100A 第一区域
100B 第二区域
100C 第三区域
100D 第四区域
112 鳍状结构
130 栅极结构
139 掩模层
140 凹槽
150 冠状外延层
150A 冠状外延层
152 底面
154 顶面
200 第二导电型态区域
212 鳍状结构
212’ 次鳍状结构
230 栅极结构
240 次外延层
240B 次外延层
250 牙状外延层
250C 牙状外延层
252 凹槽
254 上表面
260 冠状外延层
260D 冠状外延层
A1 区域
P1 蚀刻步骤
P2 鳍状切割步骤
P3 选择性外延成长步骤
P4 选择性外延成长步骤
P5 选择性外延成长步骤
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所揭露的范围，在此容先叙明。
图1至图5绘示了本发明的第一优选实施例的半导体结构的制作方法示意图。请参照图1，图1绘示了半导体结构于初始阶段的剖视图。如图1所示，首先，提供一基底10，基底10上设置有多个鳍状结构12。基底10除了块硅基底之外，上述基底10也可例如是一含硅基底、一三五族半导体覆硅基底(例如GaAs-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)或硅覆绝缘(silicon-on-insulator,SOI)基底、氧化硅基底(silicon dioxide)、铝化硅基底(aluminum oxide)、蓝宝石基底(sapphire)、含锗(germanium)基底或是硅锗合金基底(alloy of silicon and germanium)等半导体基底。
详细来说，鳍状结构12的制备方法可包括下列步骤，但不以此为限。举例来说，首先提供一块状基底(未绘示)，并在其上形成硬掩模层(未绘示)，接着利用光刻以及蚀刻制作工艺，将硬掩模层图案化，以定义出后续欲对应形成的鳍状结构12的位置。接着，进行一蚀刻步骤P1，将定义于硬掩模层内的图案转移至块状基底中，而形成所需的鳍状结构12。最后选择性地去除硬掩模层，便可获得如图1所示的结构。在此情况下，鳍状结构12可视为延伸出自基底10的一表面，且彼此间具有相同的成分组成，例如单晶硅。另一方面，当基底并非选自上述块状基底，而是选自于三五族半导体覆硅基底时，则鳍状结构的主要组成会与此基底的三五族半导体组成相同。
接下来，再利用一光致抗蚀剂图案14当作掩模来进行一鳍状结构切割(fin-cut)步骤。如图2所示，经过鳍状切割步骤P2之后，部分鳍状结构12与部分的基底被移除而形成凹槽16。一般来说，凹槽16所在的区域将再后续步骤会被填入绝缘层，而形成例如浅沟隔离(shallow trench isolation,STI)的绝缘区。而被凹槽16所包围的区域A1可定义为半导体元件的主动区，也就是后续步骤中形成的晶体管等元件的所在区域。
如图3所示，移除光致抗蚀剂图案14后，全面性形成一平坦的绝缘层20于基底10上，覆盖基底10表面并且填入凹槽16中，然后进行一平坦化步骤以及一回蚀刻步骤(图未示)，以形成浅沟隔离13。绝缘层20例如为氧化硅或是氮化硅等绝缘材质。此外，在形成绝缘层20之前，可先选择性形成一衬垫层(图未示)于基底10与绝缘层20之间，在此不多加赘述。
图4绘示了半导体结构的立体图。请注意，为了图示简洁，图4仅绘出部分半导体结构。如图4所示，形成多个栅极结构30，位于绝缘层20上并且横跨于各鳍状结构12上。其中各栅极结构30可包含一栅极介电层32、一栅极导电层34以及一帽盖层36。其中栅极介电层32的材料可以包括氧化硅(SiO)、氮化硅(SiN)、氮氧化硅(SiON)，或包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium siliconoxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontiumtitanate oxide，SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其组合所组成的群组。栅极导电层34的材料可以包括未掺杂的多晶硅、重掺杂的多晶硅、金属硅化物、或是单层或多层金属层，金属层例如功函数金属层，阻挡层和低电阻金属层等。帽盖层36可包括单层结构或多层的介电材料，例如氧化硅(SiO)、氮化硅(SiN)、碳化硅(SiC)、碳氮化硅(SiCN)，氮氧化硅(SiON)或者其组合。此外，栅极结构30侧壁可含有间隙壁，但为了附图简洁，间隙壁未被绘于图4中。
到此步骤为止，本发明的半导体结构已经形成多个鳍状结构12于基底10上，并形成多个栅极结构30于基底10上，并且各栅极结构30横跨至少一鳍状结构12。接下来在基底上定义有至少一第一导电型态区域100，以及一第二导电型态区域200，第一导电型态区域100与第二导电型态区域200之间存在有浅沟隔离。其中第一导电型态区域100或第二导电型态区域200各包含有至少一鳍状结构以及至少一栅极结构位于其中，为了更清楚说明，以下段落将位于第一导电型态区域100内的鳍状结构12标记为鳍状结构112，位于第一导电型态区域100内的栅极结构30标记为栅极结构130，位于第二导电型态区域200内的鳍状结构12标记为鳍状结构212，位于第二导电型态区域200内的栅极结构30标记为栅极结构230，其结构特征与上述的鳍状结构12以及栅极结构30相同，在此不另外赘述。
其中，第一导电型态区域100可能为一n型晶体管区域，而在后续步骤中形成至少一n型晶体管于第一导电型态区域100内，或者是一p型晶体管区域，而在后续步骤中形成至少一p型晶体管于第一导电型态区域100内。同样地，第二导电型态区域200也可能包含有一n型晶体管区域或是一p型晶体管区域。优选地，后续步骤中，第一导电型态区域100与第二导电型态区域200内所包含的晶体管，具有互补的导电型态。举例来说，若第一导电型态区域100是一n型晶体管区域，则第二导电型态区域200是一p型晶体管区域，但不限于此。以下依序介绍本发明的半导体结构所包含的外延层结构。
1.冠状外延层(crown epitaxial layer)：
请参考图5～图6，并一并参考上述的图3～图4。图5～图6为本发明的第一优选实施例的半导体结构剖视图。其中冠状外延层150形成在第一导电型态区域100内。其制作方法包含先形成一具有开口的掩模层139，至少覆盖部分的鳍状结构(例如覆盖于第二导电型态区域200内)，然后进行一蚀刻步骤(例如离子反应蚀刻等)，移除部分的鳍状结构112，在此步骤中，仅有被栅极结构130(请参考图4的立体结构)所覆盖的部分鳍状结构未被移除，而其余曝露的鳍状结构则被完全移除，因此上述蚀刻步骤之后形成至少两凹槽140(图5中仅绘出其中一个)，分别位于栅极结构的两侧。其中凹槽140具有一平坦底面，且凹槽140同时曝露(或接触)多个未被移除的鳍状结构。
接着再进行一选择性外延成长(SEG)步骤P3，以于凹槽140内形成一冠状外延层150，冠状外延层150位于栅极结构130的两侧。根据不同实施例，冠状外延层150可包含一硅锗外延层，而适用于一PMOS晶体管，或者冠状外延层150可包含一硅碳外延层，而适用于一NMOS晶体管。熟悉该项技术的人士应知，在进行外延成长步骤P3时，冠状外延层150沿着凹槽140的各表面成长，但不会沿着绝缘层表面成长。因此冠状外延层150填满凹槽140，优选地，冠状外延层150具有一平坦底面152以及一平坦顶面154，但不限于此。另外值得注意的是，由于鳍状结构112仅位于凹槽140旁(位于栅极结构130下方)，而不位于凹槽140内，因此冠状外延层150虽然位于多个鳍状结构112旁并且直接接触多个鳍状结构112，但是却不会覆盖于鳍状结构112之上。
值得注意的是，本实施例中冠状外延层150位于第一导电型态区域100内，但本发明不限于此，冠状外延层150可能位于其他区域，也属于本发明的涵盖范围内。
2.次外延层(sub-epitaxial layer)
请继续参考图5～图6，并且一并参考上述的图3～图4。在第二区域中，形成多个次外延层240，位于栅极结构230(其位置请参考图4)旁，且覆盖于各鳍状结构212上。与上述冠状外延层150的制作方法不同在于，制作次外延层240并不需要进行蚀刻步骤来移除鳍状结构，而是可以直接进行一选择性外延成长(SEG)步骤P4，于各鳍状结构212上形成次外延层240。根据不同实施例，次外延层240可包含一硅锗外延层，而适用于一PMOS晶体管，或者次外延层240可包含一硅碳外延层，而适用于一NMOS晶体管。
值得注意的是，本实施例中，第二导电型态区域200内，由于未移除鳍状结构212，因此次外延层240至少会覆盖于部分鳍状结构212的三个表面，包含一顶面以及两侧壁。根据不同实施例，调整选择性外延成长(SEG)步骤P4的参数(例如时间等)，可能导致各次外延层240可能会彼此分开或是互相聚合(merged)一起。上述方法为本领域技术人员所熟知，故不再赘述，但本发明不以此为限。
3.牙状外延层(teeth epitaxial layer)：
请参考图7，并一并参考上述的图3～图4。图7为本发明的第二优选实施例的半导体结构剖视图。其中冠状外延层150形成在第一导电型态区域100内。其制作方法与上述第一实施例相同，在此不另外赘述。另外本实施例中，至少二牙状外延层250形成于位于栅极结构230(其位置请参考图4)旁，其制作方法类似形成冠状外延层的步骤，包含先形成一具有开口的掩模层(图未示)，至少覆盖部分的鳍状结构212，然后进行一蚀刻步骤(例如离子反应蚀刻等)，移除部分的鳍状结构212，在此步骤中，被栅极结构230(请参考图4的立体结构)所覆盖的部分鳍状结构212未被移除，而其余曝露的鳍状结构则被部分移除，而形成多个次鳍状结构212’，各次鳍状结构212’由位于栅极结构230正下方，未被移除的鳍状结构212延伸出来，并且次鳍状结构212’的高度较第二鳍状结构212的高度低。因此上述蚀刻步骤之后形成至少两凹槽252(图6中仅绘出其中一个)，分别位于栅极结构的两侧。其中凹槽252内包含有多个次鳍状结构212’。
接着再进行一选择性外延成长(SEG)步骤P5，以于凹槽252内形成一牙状外延层250，牙状外延层250位于栅极结构230的两侧。根据不同实施例，牙状外延层250可包含一硅锗外延层，而适用于一PMOS晶体管，或者牙状外延层250可包含一硅碳外延层，而适用于一NMOS晶体管。熟悉该项技术的人士应知，在进行外延成长步骤P5时，牙状外延层250沿着凹槽252的各表面成长，且凹槽252内包含有多个次鳍状结构212’，因此牙状外延层250填满凹槽250，同时，牙状外延层250的一上表面254应具有凹凸轮廓。此外，牙状外延层250直接覆盖于次鳍状结构212’正上方，并且位于鳍状结构212旁。
请参考图8，并一并参考上述的图3～图4。图8为本发明的第三优选实施例的半导体结构剖视图。其中冠状外延层150形成在第一导电型态区域100内。其制作方法与上述第一实施例相同，在此不另外赘述。而第二导电型态区域200内则形成有多个冠状外延层260，其制作方法也与冠状外延层150相同，只是在本实施例中，通过调整凹槽的深度，冠状外延层150与冠状外延层260具有不同的厚度。另外值得注意的是，上述其他形状的外延层，也可与本实施例整合，也就是通过调整制作工艺参数而改变厚度。举例来说，本发明的一实施例中，半导体结构在其中一导电型态区域中包含有一牙状外延层，在另外一个导电型态区域中则包含有另一具有不同厚度的牙状外延层，也属于本发明的涵盖范围内。
此外，上述各实施例也可以互相整合，举例来说，本发明的一实施例中，半导体结构在其中一导电型态区域中包含有多个次外延层，在另外一个导电型态区域中则包含有另一牙状外延层。仅需要满足在同一个半导体结构中，包含有不同形状的外延层，都属于本发明涵盖范围。
另外，上述各实施例中揭露在同一个半导体结构中，不同的导电型态区域中，分别包含有不同形状的外延层。但是在本发明中，即使是同一个导电型态区域中，也可以包含有不同形状的外延层。请参考图9，其绘示本发明第四优选实施例的半导体结构剖视图。本实施例中，基底10尚包含有多个鳍状结构12以及栅极结构(图9未示，可参考前述图4)，另外第一导电型态区域100中还包含有多个区域，例如第一区域100A、第二区域100B、第三区域100C以及第四区域100D等，各区域之间以浅沟隔离13相互分隔。在本实施例中，第一区域100A内包含有至少一冠状外延层150A、第二区域100B中内包含有至少一次外延层240B、第三区域100C中内包含有至少一牙状外延层250C、第四区域100D中则包含有一冠状外延层260D，其中冠状外延层260D的厚度与冠状外延层150A不同。本实施例中所述的冠状外延层、次外延层以及牙状外延层等，其结构特征与制作方法都与上述本案第一至第三实施例所述相同，在此不另外赘述。
值得注意的是，图9所示仅为本发明的其中一实施例，但本发明不限于此。在本发明的其他实施例中，一半导体结构的同一个导电型态区域中，所包含区域的数量，或者是各区域内形成的外延层形状，都可以依照实施需求调整，本发明不以此为限。
综上所述，本发明的特征在于，在同一个半导体结构之中，不同的导电型态区域内，包含有不同形状的外延层。或着是同一个半导体结构的同一个导电型态区域内，包含有不同区域，且各区域分别包含不同形状的外延层。本发明将不同形状的外延层制作于同一半导体结构中，可提高半导体结构在应用上的灵活性。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种半导体元件，包含：
基底，其上定义有一第一导电型区域以及一第二导电型区域；
多条第一鳍状结构，位于该基底上并位于该第一导电型区域内，以及多条第二鳍状结构，位于该基底上并位于该第二导电型区域内；
多个第一栅极结构，位于该第一导电型区域内，横跨该多条第一鳍状结构，以及多个第二栅极结构，位于该第二导电型区域内，横跨该多条第二鳍状结构；
至少一绝缘层，位于该第一栅极结构以及该第二栅极结构的两侧；以及
至少两第一冠状外延层，设置于该第一导电型区域内，且位于各该第一栅极结构的两侧，以及多个第二外延层，设置于该第二导电型区域内，位于各该第二栅极结构的两侧，其中该第一冠状外延层位于该第一栅极结构的两侧的一第一凹槽内，该第一凹槽具有一平坦底面，且同时接触该多条第一鳍状结构，另外该第二外延层的形状与该第一冠状外延层不同，其中从一剖面图来看，各该第一冠状外延层不直接接触该绝缘层，其中一个该第一冠状外延层位于多条第一鳍状结构的侧面并同时接触多条第一鳍状结构，且该第一冠状外延层不直接覆盖于各该第一鳍状结构的正上方。
2.如权利要求1所述的半导体元件，其中该第一导电型区域为一p型晶体管区域，该第二导电型区域为一n型晶体管区域。
3.如权利要求1所述的半导体元件，其中该第一导电型区域为一n型晶体管区域，该第二导电型区域为一p型晶体管区域。
4.如权利要求1所述的半导体元件，其中各该第一冠状外延层具有平坦底面以及平坦顶面。
5.如权利要求1所述的半导体元件，其中该第二外延层包含有多个次外延结构，其中每一个次外延结构跨于各该第二鳍状结构的三个表面。
6.如权利要求1所述的半导体元件，其中该第二外延层包含有至少一第二冠状外延层，位于该第二栅极结构旁的两第二凹槽内，该第二凹槽具有平坦底面，且该至少一第二冠状外延层直接接触该多条第二鳍状结构。
7.如权利要求6所述的半导体元件，其中该第二冠状外延层的厚度与该第一冠状外延层的厚度不同。
8.如权利要求6所述的半导体元件，其中该第二冠状外延层位于多个第二鳍状结构的侧面，且该第二冠状外延层不直接覆盖于各该第二鳍状结构的正上方。
9.如权利要求1所述的半导体元件，其中该第二外延层包含牙状外延层，该牙状外延层的一上表面包含一凹凸轮廓。
10.如权利要求9所述的半导体元件，其中该第二导电型区域的该第二栅极结构两侧的该基底定义有多条次鳍状结构，该多条次鳍状结构由该多条第二鳍状结构延伸出来，并且该多条次鳍状结构的高度较该多条第二鳍状结构的高度低，且该牙状外延层直接覆盖于各该次鳍状结构的正上方。
11.一种半导体元件，包含：
基底，其上定义有一第一导电型区域，该第一导电型区域内包含有第一区域以及第二区域；
多条第一鳍状结构，位于该基底上并位于该第一区域内，以及多条第二鳍状结构位于该基底上并位于该第二区域内；
多个第一栅极结构，位于该第一区域内，横跨该多条第一鳍状结构，以及多个第二栅极结构，位于该第二区域内，横跨该多条第二鳍状结构；
至少一绝缘层，位于该第一栅极结构以及该第二栅极结构的两侧；以及
至少两第一冠状外延层，设置于该第一区域内，且位于各该第一栅极结构的两侧，以及多个第二外延层，设置于该第二区域内，位于各该第二栅极结构的两侧，其中该第一冠状外延层位于该第一栅极结构的两侧的一第一凹槽内，该第一凹槽具有一平坦底面，且同时接触该多条第一鳍状结构,另外该第二外延层的形状与该第一冠状外延层不同，其中从一剖面图来看，各该第一冠状外延层不直接接触该绝缘层，其中一个该第一冠状外延层位于多条第一鳍状结构的侧面并同时接触多条第一鳍状结构，且该第一冠状外延层不直接覆盖于各该第一鳍状结构的正上方。
12.如权利要求11所述的半导体元件，其中该第一导电型区域为一p型晶体管区域或一n型晶体管区域。
13.如权利要求11所述的半导体元件，其中各该第一冠状外延层具有一平坦底面以及一平坦顶面。
14.如权利要求11所述的半导体元件，其中该第二外延层包含有多个次外延结构，其中每一个次外延结构跨于各该第二鳍状结构的三个表面。
15.如权利要求11所述的半导体元件，其中该第二外延层包含有至少一第二冠状外延层，位于该第二栅极结构旁的两第二凹槽内，该第二凹槽具有平坦底面，且该至少一第二冠状外延层直接接触该多条第二鳍状结构。
16.如权利要求15所述的半导体元件，其中该第二冠状外延层的厚度与该第一冠状外延层的厚度不同。
17.如权利要求15所述的半导体元件，其中该第二冠状外延层位于多个第二鳍状结构的侧面，且该第二冠状外延层不直接覆盖于各该第二鳍状结构的正上方。
18.如权利要求11所述的半导体元件，其中该第二外延层的包含牙状外延层，该牙状外延层的一上表面包含一凹凸轮廓。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI683395B (zh) 2015-11-12 2020-01-21 聯華電子股份有限公司 鰭狀電晶體與鰭狀電晶體的製作方法
US10453943B2 (en) * 2016-11-29 2019-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. FETS and methods of forming FETS
US10658225B2 (en) * 2018-01-19 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices and methods of forming the same
CN113611743B (zh) 2021-06-11 2022-06-07 联芯集成电路制造(厦门)有限公司 半导体晶体管结构及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130122668A1 (en) * 2010-09-07 2013-05-16 International Business Machines Corporation Method for forming and structure of a recessed source/drain strap for a mugfet
US20150104913A1 (en) * 2013-10-11 2015-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous Formation of Source/Drain Openings with Different Profiles
CN104733312A (zh) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN107026084A (zh) * 2016-02-02 2017-08-08 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8362575B2 (en) 2009-09-29 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling the shape of source/drain regions in FinFETs
US8426923B2 (en) 2009-12-02 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate semiconductor device and method
US9231106B2 (en) * 2013-03-08 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with an asymmetric source/drain structure and method of making same
US9570586B2 (en) * 2013-11-20 2017-02-14 Globalfoundries Inc. Fabrication methods facilitating integration of different device architectures
KR102193493B1 (ko) * 2014-02-03 2020-12-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9647113B2 (en) * 2014-03-05 2017-05-09 International Business Machines Corporation Strained FinFET by epitaxial stressor independent of gate pitch
US9257505B2 (en) * 2014-05-09 2016-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and formation methods of finFET device
CN105514161B (zh) * 2014-09-26 2019-05-03 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US9484461B2 (en) * 2014-09-29 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
KR102159924B1 (ko) * 2014-10-14 2020-09-25 삼성전자 주식회사 Esd 보호 회로를 포함하는 반도체 장치
KR102352153B1 (ko) * 2015-03-25 2022-01-17 삼성전자주식회사 집적회로 장치 및 이의 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130122668A1 (en) * 2010-09-07 2013-05-16 International Business Machines Corporation Method for forming and structure of a recessed source/drain strap for a mugfet
US20150104913A1 (en) * 2013-10-11 2015-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous Formation of Source/Drain Openings with Different Profiles
CN104733312A (zh) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN107026084A (zh) * 2016-02-02 2017-08-08 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法

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