CN110620150A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN110620150A
CN110620150A CN201910412594.XA CN201910412594A CN110620150A CN 110620150 A CN110620150 A CN 110620150A CN 201910412594 A CN201910412594 A CN 201910412594A CN 110620150 A CN110620150 A CN 110620150A
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China
Prior art keywords
epitaxial layer
concentration
semiconductor device
source
layer
Prior art date
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Pending
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CN201910412594.XA
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English (en)
Inventor
金东宇
金度希
金孝珍
文康薰
李始炯
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110620150A publication Critical patent/CN110620150A/zh
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Abstract

本发明提供了一种半导体器件，包括：多个有源鳍，所述多个有源鳍在衬底上；栅电极，所述栅电极与所述多个有源鳍交叉；以及源/漏极区，所述源/漏极区在所述多个有源鳍上，并在所述栅电极的第一侧和第二侧延伸。所述源/漏极区包括在所述多个有源鳍中一些上的多个下外延层。所述多个下外延层包含具有第一浓度的锗(Ge)。上外延层在所述多个下外延层上并且包含具有高于所述第一浓度的第二浓度的锗。所述多个下外延层具有凸的上表面，并且在所述有源鳍之间彼此连接。

Description

半导体器件
相关申请的交叉引用
本申请要求2018年6月20日在韩国知识产权局提交的韩国专利申请No.10-2018-0070878的优先权，其公开内容通过引用整体并入本文。
技术领域
本发明构思涉及半导体器件。
背景技术
随着对半导体器件的高性能、高速度和/或多功能性的需求增加，半导体器件的集成度也增加了。当制造具有对应于半导体器件的高集成趋势的精细图案的半导体器件时，可能需要实现具有精细宽度或精细分隔距离的图案。此外，为了克服平面金属氧化物半导体FET(MOSFET)的元件特性的限制，已经开发了包括具有三维结构的沟道的FinFET的半导体器件。
发明内容
本发明构思的一些实施例提供了具有低接触电阻并具有低接触电阻变化和低性能变化的半导体器件。
根据本发明构思的示例实施例，一种半导体器件，包括：多个有源鳍，所述多个有源鳍在衬底上；栅电极，所述栅电极与所述多个有源鳍交叉；以及源/漏极区，所述源/漏极区在所述多个有源鳍上，并在所述栅电极的第一侧和第二侧延伸。所述源/漏极区包括上外延层和多个下外延层。所述多个下外延层在所述多个有源鳍上并且包含具有第一浓度的锗(Ge)。所述上外延层在所述多个下外延层上并且包含具有高于所述第一浓度的第二浓度的锗。所述多个下外延层具有凸的上表面，并且在所述有源鳍之间彼此连接。
根据本发明构思的示例实施例，一种半导体器件包括：多个有源鳍，所述多个有源鳍在衬底上；栅电极，所述栅电极与所述多个有源鳍交叉；以及源/漏极区，所述源/漏极区在所述多个有源鳍上，并在所述栅电极的第一侧和第二侧延伸。所述源/漏极区包括第一外延层、第二外延层、第三外延层和第四外延层。所述第一外延层在所述多个有源鳍中的一些上并且包含具有第一浓度的锗。所述第二外延层在所述第一外延层上并且包含具有高于所述第一浓度的第二浓度的锗。所述第三外延层在所述第二外延层上并且包含具有高于所述第二浓度的第三浓度的锗。所述第四外延层包含具有高于所述第三浓度的第四浓度的锗并覆盖所述第三外延层。所述第三外延层具有凸的上表面，并且在所述多个有源鳍中的一些之间彼此连接。
根据本发明构思的示例实施例，一种半导体器件，包括：多个有源鳍，所述多个有源鳍在衬底上；栅电极，所述栅电极与所述多个有源鳍交叉；源/漏极区，所述源/漏极区在所述多个有源鳍上，并在所述栅电极的第一侧和第二侧延伸，以及在所述源/漏极区上的接触插塞。所述源/漏极区包括第一外延层、第二外延层、第三外延层和第四外延层。所述第一外延层在所述多个有源鳍中的一些上并且包含具有第一浓度的锗。所述第二外延层在所述第一外延层上并且包含具有高于所述第一浓度的第二浓度的锗。所述第三外延层在所述第二外延层上并且包含具有高于所述第二浓度的第三浓度的锗。所述第四外延层包含具有高于所述第三浓度的第四浓度的锗并覆盖所述第三外延层。所述第三外延层具有凸的上表面，并且在所述多个有源鳍中的一些之间的位置中彼此连接，所述接触插塞与所述第四外延层接触。
附图说明
通过以下结合附图的详细描述，将更清楚地理解本公开的上述和其他方面、特征和其他优点，其中：
图1是示出根据一些实施例的半导体器件的透视图；
图2A和图2B是示出根据一些实施例的图1的半导体器件分别沿着线I-I'和II-II'切割的横截面视图；
图3至图6是示出根据一些实施例的半导体器件的透视图；
图7至图16是示出根据一些实施例的制造半导体器件的方法的图示；以及
图17和图18是示出根据比较示例实施例的半导体器件的透视图和横截面视图。
具体实施方式
应当注意，关于一个实施例描述的发明构思的各方面可以并入不同的实施例中，尽管没有相对于其具体描述。也就是说，所有实施例和/或任何实施例的特征可以以任何方式和/或组合进行组合。在下面阐述的说明书中详细解释了本发明构思的这些和其他目的和/或方面。如这里所使用的，术语“和/或”包括相关所列项目中的一个或更多个的任何和所有组合。在元件列表之后的诸如“至少一个”之类的表达式会修饰整个元件列表，而不修饰列表的个别元件。
在下文中，将参考附图详细描述本公开的示例实施例。
图1是示出根据示例实施例的半导体器件的透视图。图2A和图2B是示出图1的半导体器件沿着I-I'和II-II'线切割的横截面视图。为了便于说明，图1中仅示出了主要部件，图1中省略了图2A和图2B中的层间绝缘层160。
参照图1至图2B，半导体器件100可以包括衬底101、有源鳍105、源/漏极区110、栅极结构140和接触插塞180。半导体器件100还可以包括元件隔离层107、间隔物150以及层间绝缘层160。
根据示例实施例的半导体器件100可以是其中有源鳍105具有鳍形状的场效应晶体管(FinFET)。
衬底101可以具有在X方向和Y方向上延伸的上表面。衬底101可以包含半导体材料，例如，IV族半导体、III-V族化合物半导体或II-VI族化合物半导体。例如，IV族半导体可以包含硅、锗或硅锗。衬底101可以设置为单晶硅晶片、绝缘体上硅(SOI)衬底等。
元件隔离层107可以在衬底101中限定有源鳍105，并且可以将有源鳍105彼此分隔开。元件隔离层107可以由绝缘材料形成。可以使用例如浅沟槽隔离(STI)工艺来形成元件隔离层107。元件隔离层107可以包含例如氧化物、氮化物或其组合。
有源鳍105可以由衬底101中的元件隔离层107限定，并且可以设置为在第一方向(例如，Y方向)上延伸。有源鳍105可以具有从衬底101突出的鳍形状。有源鳍105可以由衬底101的一部分形成，并且可以包括从衬底101生长的外延层。
源/漏极区110可以设置在栅极结构140的两侧的有源鳍105上。源/漏极区110可以是设置在栅极结构140的两侧的区域中的嵌入式源/漏极，衬底101上的有源鳍105的一部分从该区域被移除。源/漏极区110可以设置为半导体器件100的源极区或漏极区。
源/漏极区110可以具有在两个有源鳍105上的连接的或合并的结构。然而，源/漏极区110的连接的或合并的结构下方的有源鳍105的数量不限于附图中所示的数量。在示例实施例中，源/漏极区110可以具有在三个或更多个有源鳍105上的连接的或合并的结构。
源/漏极区110可以包含例如硅或硅锗(SiGe)。例如，当源/漏极区110包含硅锗时，可以将压应力施加到沟道区，即由硅(Si)形成的有源鳍105的区域，使得可以改善空穴的迁移率。
源/漏极区110可以包括多个外延层。每个源/漏极区110可以包括第一外延层111、第二外延层113、第三外延层115和第四外延层117，第一外延层111、第二外延层113、第三外延层115和第四外延层117包括可以为彼此不同浓度的锗(Ge)。源/漏极区110还可以包括覆盖第四外延层117的覆盖层119。
第一外延层111分别设置在有源鳍105上，而第二外延层113可以分别设置在第一外延层111上。第三外延层115分别设置在第二外延层113上，第三外延层115可以具有凸的上表面。第三外延层115可以在相邻的有源鳍105之间的元件隔离层107上/上方彼此连接。在一些实施例中，第三外延层115可以彼此连接以提供单个外延区。
第四外延层117设置在第三外延层115上，并且可以具有相对于衬底101的上表面倾斜的倾斜侧表面117S。第四外延层117的侧表面117S可以对应于晶体学平面。例如，当第四外延层117由硅锗(SiGe)形成时，第四外延层117的侧表面117S可以是{111}晶面。位于侧表面117S之间的第四外延层117的上表面可以是平坦表面。
可以在相邻的有源鳍105之间的位置处在源/漏极区110与元件隔离层107之间设置气隙108。
第一外延层111、第二外延层113、第三外延层115和第四外延层117可以包含彼此浓度不同的元素和/或掺杂元素。
例如，第一外延层111可以包含具有第一浓度的锗(Ge)，第二外延层113可以包含具有高于第一浓度的第二浓度的锗，以及第三外延层115可以包含具有高于第二浓度的第三浓度的锗。第四外延层117可以包含具有高于第三浓度的第四浓度的锗。
锗的第一浓度可以为5at％(原子百分比)至25at％，而锗的第二浓度可以为25at％至45at％。此外，锗的第三浓度可以为45at％至60at％，而锗的第四浓度可以为60at％至90at％。
第一外延层111、第二外延层113、第三外延层115和第四外延层117可以包含彼此浓度不同的掺杂元素(杂质)。硼(B)可以用作杂质的掺杂元素。例如，第一外延层111可以包含具有第一浓度的硼，而第二外延层113可以包含具有高于第一浓度的第二浓度的硼。另外，第三外延层115可以包含具有高于第二浓度的第三浓度的硼，而第四外延层117可以包含具有高于第三浓度的第四浓度的硼。
第一外延层111、第二外延层113和第三外延层115可以包含不同浓度的锗，同时包含具有不同浓度的各个掺杂元素。在一些实施例中，锗浓度或掺杂元素浓度中只有一者可以是不同。
覆盖层119可以被设置为包围第四外延层117的外表面，并且覆盖层119可以在后续工艺期间保护第四外延层117。覆盖层119可以由硅(Si)形成。当第四外延层117由具有相对低熔点的硅锗形成时，覆盖层119由硅形成，使得第四外延层117可以在后续工艺期间受到保护。换句话说，第四外延层117的熔点可以比覆盖层119的熔点低。
栅极结构140可以设置为与有源鳍105交叉，并且可以包括栅极绝缘层142、第一栅电极145和第二栅电极147。栅极结构140可以覆盖有源鳍105的上表面的一部分。间隔物150可以设置在栅极结构140的两个侧表面中的每一个侧表面上。
栅极绝缘层142可以设置在有源鳍105与第一栅电极145之间以及间隔物150与第一栅电极145之间。栅极绝缘层142可以包含氧化硅、氮化硅、氮氧化硅或高k材料。高k材料可以指介电常数可以高于氧化硅(SiO2)膜的介电常数的介电材料。高k材料可以是例如氧化铝(Al2O3)、氧化钽(Ta2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、氧化锆(ZrO2)、氧化锆硅(ZrSixOy)、氧化铪(HfO2)、氧化铪硅(HfSixOy)、氧化镧(La2O3)、氧化镧铝(LaAlxOy)、氧化镧铪(LaHfxOy)、氧化铪铝(HfAlxOy)和/或氧化镨(Pr2O3)。在示例实施例中，栅极绝缘层142可以设置在第一栅电极145的下表面上。
第一栅电极145和第二栅电极147可以顺序地设置在栅极绝缘层142上。第一栅电极145和第二栅电极147可以由不同的材料形成。第一栅电极145可以包含例如TiN、TaN、WN、WCN、TiAl、TiAlC、TiAlN或其组合。第二栅电极147可以包含诸如铝(Al)、钨(W)、钼(Mo)等的金属材料，或诸如掺杂多晶硅的半导体材料。在示例实施例中，栅电极可以包括单层。例如，可以省略第二栅电极147。
间隔物150可以使得源/漏极区110与第一栅电极145和第二栅电极147隔离开。间隔物150可以由氧化硅、氮化硅、氮氧化硅、低k材料或其组合形成。间隔物150可以形成为单层膜或多层膜。例如，间隔物150可以具有氮化硅和低k材料的堆叠结构。低k材料可以指介电常数低于氧化硅(SiO2)膜的介电常数的介电材料。低k材料可以包含SiCN、SiOC、SiON、SiOCN等。
接触插塞180设置在源/漏极区110上，并且在半导体器件100的俯视图中可以具有细长形状。换句话说，接触插塞180可以具有在栅极结构140的延伸方向(即，X方向)上延伸的形状，并且可以为诸如矩形、椭圆形等的形状。
接触插塞180可以穿过第一层间绝缘层162和第二层间绝缘层164以连接到源/漏极区110。接触插塞180设置在源/漏极区110的上表面被蚀刻到预定深度的部分中，以连接到源/漏极区110。
在示例实施例中，接触插塞180的下端可以与源/漏极区110的第四外延层117接触。因此，即使源/漏极区110的上表面被刻蚀的深度在形成用于形成接触插塞180的接触孔OP的操作中不同(参见图15)，接触插塞180与源/漏极区110之间的接触电阻的变化可能较低或不存在。即使当接触插塞180的下端的位置改变时，接触插塞180与源/漏极区110之间的接触电阻的变化也可能较低或不存在。然而，在图17和图18的半导体器件400作为比较示例的情况下，接触插塞180连接到源/漏极区410的第三外延层415和第四外延层417。因此，根据接触插塞180的下端的位置，接触插塞180与源/漏极区410之间的接触电阻可能改变。
在示例实施例中，接触插塞180连接到第四外延层117。在这种情况下，当第四外延层117包含具有高浓度的锗时，接触插塞180与源/漏极区110之间的肖特基势垒的高度降低了，因此接触插塞180与源/漏极区110之间的接触电阻会减小。此外，当第四外延层117包含具有高浓度的硼时，接触插塞180与源/漏极区110之间的肖特基势垒的宽度减小，因此接触插塞180与源极/漏区110之间的接触电阻会减小。
接触插塞180可以包含硅化物层182以及第一导电层184和第二导电层186。硅化物层182可以设置为与源/漏极区110接触。硅化物层182可以是其中第一导电层184的一部分被源/漏极区110硅化的层，或者可以根据示例实施例省略。硅化物层182可以是例如硅化钛。第一导电层184可以形成在源/漏极区110的上部上以及接触插塞180的侧壁上。第一导电层184可以包含例如氮化钛(TiN)膜、氮化钽(TaN)膜或氮化钨(WN)膜中的至少一种金属氮化物膜。第二导电层186可以包含诸如铝(Al)、铜(Cu)、钨(W)、钼(Mo)等的导电材料。
层间绝缘层160可以包含第一层间绝缘层162和第二层间绝缘层164，并且可以设置为覆盖衬底101、源/漏极区110和栅极结构140。第一层间绝缘层162的上表面可以与栅极结构140的上表面的高度基本相同。然而，第一层间绝缘层162和第二层间绝缘层164是在工艺中区分的层，界面的相对高度和位置不限于附图中所示的那些。在一些示例实施例中，第一层间绝缘层162和第二层间绝缘层164可以设置为单层。第一层间绝缘层162和第二层间绝缘层164可以由绝缘材料形成。例如，第一层间绝缘层162可以是聚硅氮烷(TOSZ)膜，而第二层间绝缘层164可以是正硅酸乙酯(TEOS)膜。
图3至图6是示出根据示例实施例的半导体器件的透视图。参照图3，半导体器件100a可以包括衬底101、有源鳍105、源/漏极区110a、栅极结构140和接触插塞180。半导体器件100a还可以包括元件隔离层107和间隔物150。
每个源/漏极区110a可以包括第一外延层111、第二外延层113、第三外延层115和第四外延层117a，以及覆盖层119。在根据示例性实施例的半导体器件100a中，位于倾斜侧表面117S之间的第四外延层117a的上表面可以具有向下凹的形状，这不同于与图1的半导体器件100。第四外延层117a的上表面可以是向下凹的形状。
参照图4，半导体器件100b可以包括衬底101、有源鳍105、源/漏极区110b、栅极结构140和接触插塞180。半导体器件100b还可以包括元件隔离层107和间隔物150。
每个源/漏极区110b可以包括第一外延层111、第二外延层113、第三外延层115和第四外延层117b，以及覆盖层119。在根据示例实施例的半导体器件100b中，位于倾斜侧表面117S之间的第四外延层117b的上表面可以具有凹槽，其方式与图1的半导体器件100不同。凹槽的侧表面可以相对于衬底101的上表面倾斜。
参照图5，半导体器件100c可以包括衬底101、有源鳍105、源/漏极区110c、栅极结构140和接触插塞180。半导体器件100c还可以包括元件隔离层107和间隔物150。
源/漏极区110c可以设置为连接在三个有源鳍105上。每个源/漏极区110c可以包括第一外延层111、第二外延层113、第三外延层115c和第四外延层层117c，以及覆盖层119。
形成在三个有源鳍105上的第三外延层115c彼此连接以形成单个第三外延层。第四外延层117c可以覆盖第三外延层115c，并且可以具有倾斜侧表面117S。第四外延层117c可以具有位于倾斜侧表面117S之间的平坦上表面。在示例实施例中，第四外延层117c的上表面可以在有源鳍105之间的位置具有向下凹的形式的曲度，其方式类似于图3所示的方式。在示例实施例中，第四外延层117c的上表面可以在有源鳍105之间的位置具有沟槽，其方式类似于图4所示的方式。
参照图6，透视图，半导体器件100d可以包括衬底101、有源鳍105、源/漏极区110d、栅极结构140和接触插塞180。半导体器件100d还可以包括元件隔离层107和间隔物150。
除了第一外延层111、第二外延层113、第三外延层115和第四外延层117之外，每个源/漏极区110d还可以包括第五外延层114。第五外延层114可以设置在第二外延层113与第三外延层115之间，并且可以包括浓度不同于第二外延层113和第三外延层115的锗。例如，第五外延层114可以包含具有大于第二外延层113的第二浓度并小于第三外延层115的第三浓度的第五浓度的锗。
图7至图16是根据描述根据示例实施例的制造半导体器件的方法的工艺顺序示出的图示。图15示出了沿图14中的线III-III'切割的横截面。
参照图7，对衬底101进行图案化以形成有源鳍105。此外，可以设置覆盖有源鳍105的下部的元件隔离层107。
在衬底101上形成掩模图案，并且使用掩模图案对衬底101进行各向异性蚀刻，以形成限定有源鳍105的沟槽。沟槽可以具有高纵横比，并且可以具有朝向下部更窄的宽度。因此，有源鳍105可以具有朝向上部更窄的宽度。
可以用绝缘材料填充沟槽并且可以执行平坦化。在平坦化期间可以去除掩模图案的至少一部分。在示例实施例中，在沟槽中提供相对薄的衬垫层，然后可以填充沟槽。
可以去除填充沟槽的绝缘材料的一部分，因此可以允许有源鳍105从元件隔离层107突出。因此，有源鳍105可以突出预定高度H5，并且突出的高度H5可以改变。
参照图8，可以设置虚设栅极绝缘层132、虚设栅电极135和间隔物150，它们在与有源鳍105交叉的同时延伸。
可以通过使用例如掩模图案层136执行蚀刻来设置虚设栅极绝缘层132和虚设栅电极135。
虚设栅极绝缘层132和虚设栅电极135可以设置在将要设置栅极绝缘层142以及第一栅电极145和第二栅电极147(参见图1)的区域中，并可在后续过程中去除。例如，虚设栅极绝缘层132可以包含氧化硅，而虚设栅电极135可以包含多晶硅。
在均匀厚度的膜设置在虚设栅极绝缘层132、虚设栅电极135和/或掩模图案层136的上部上之后，可以通过各向异性地蚀刻该膜来提供间隔物150。间隔物150可以具有其中堆叠多个膜的结构。
参照图9，可以从间隔物150的两侧选择性地去除有源鳍105。
从间隔物150的两侧去除一部分有源鳍105以设置凹陷。可以通过形成单独的掩模层或者通过使用掩模图案层136和间隔物150作为掩模蚀刻一部分有源鳍105来设置凹陷。例如，可以通过依次施加干法蚀刻工艺和湿法蚀刻工艺来设置凹陷。选择性地，在形成凹陷之后，可以通过单独的工艺执行对有源鳍105的表面的固化。在示例实施例中，已经蚀刻的有源鳍105的上表面可以位于与元件隔离层107的上表面的高度相同的高度上。在示例实施例中，已经蚀刻的有源鳍105的上表面可以位于比元件隔离层107的上表面更高或更低的位置。
在形成凹陷之前或之后，可以执行将杂质注入到虚设栅电极135的两侧的有源鳍105中。
在下文中，参照图10和图11描述可以使用例如选择性外延生长(SEG)工艺来执行形成源/漏极区110。
参照图10，源/漏极区110的第一外延层111、第二外延层113和第三外延层115可以在间隔物150的两侧的已经被蚀刻的有源鳍105上顺序形成。
作为用于减少由与有源鳍105的晶格常数差异引起的缺陷的发生的缓冲层，可以设置包含具有相对低的第一浓度的锗的第一外延层111。包含具有高于第一浓度的第二浓度的锗的第二外延层113可以设置在第一外延层111上。包含具有高于第二浓度的第三浓度的锗的第三外延层115可以设置在第二外延层113上。第三外延层115在生长的同时彼此连接以提供单个外延层。
在源/漏极区110的第一外延层111、第二外延层113和第三外延层115的生长期间，可以原位掺杂诸如硼的杂质。
参照图11，可以在源/漏极区110的第三外延层115上提供包含具有第四浓度的锗的第四外延层117。
第四外延层117的侧表面117S可以相对于衬底101的上表面倾斜。第四外延层117可以包含具有高于第三外延层115的第三浓度的第四浓度的锗。此外，第四外延层117可以包含诸如硼的掺杂元素，其浓度高于第三外延层115的浓度，但是不限于此。
由于上述操作，可以设置包括第一外延层111、第二外延层113、第三外延层115c和第四外延层117以及覆盖层119的源/漏极区110。
参照图12，可以在源/漏极区110上设置第一层间绝缘层162。
可以通过形成绝缘材料层、覆盖掩模图案层136、间隔物150和源/漏极区110，并且平坦化绝缘材料层以暴露虚设栅电极135上表面来提供第一层间绝缘层162。因此，在上述操作中，可以去除掩模图案层136。
第一层间绝缘层162可以包含例如氧化硅、氮化硅、氮氧化硅或低k材料中的至少一种。
可以去除虚设栅极绝缘层132和虚设栅电极135。可以相对于元件隔离层107和有源鳍105选择性地去除虚设栅极绝缘层132和虚设栅电极135，因此可以设置用于暴露元件隔离层107和有源鳍105的开口E。可以使用干法蚀刻工艺或湿法蚀刻工艺中的至少一种来执行去除虚设栅极绝缘层132和虚设栅电极135。
参照图13，可以在开口E中顺序形成栅极绝缘层142、第一栅电极145和第二栅电极147，从而形成栅极结构140。
栅极绝缘层142沿着开口E的侧壁和下表面基本上共形地形成。栅极绝缘层142可以包含氧化硅、氮化硅、氮氧化硅或高k材料。
第一栅电极145和第二栅电极147可以包含金属、金属氮化物或半导体材料。
参照图14和图15，层间绝缘层162和164被图案化以提供接触孔OP。
可以设置第二层间绝缘层164。然后，通过使用诸如光致抗蚀剂图案的单独掩模层，可以从将要设置接触插塞180的区域移除第一层间绝缘层162和第二层间绝缘层164(参见图1)。因此，可以设置接触孔OP。在去除第一层间绝缘层162和第二层间绝缘层164期间，可以一起去除源/漏极区110的一部分。因此，源/漏极区110的一部分可以通过接触孔OP暴露。
参照图16，导电材料可以嵌入接触孔OP中以形成接触插塞180。
顺序地沉积第一导电层184和第二导电层186，从而可以由此嵌入接触孔OP。在上述操作中或在随后的操作中，随着第一导电层184的材料和源/漏极区110的材料彼此反应，可以设置形成在源/漏极区110的界面处的硅化物层182(参见图2A)。
图17和图18是示出根据比较示例的半导体器件的透视图和横截面视图。图18示出了沿图17的线IV-IV'切割的横截面。
参照图17和图18，半导体器件400可以包括衬底101、有源鳍105、源/漏极区410、栅极结构140和接触插塞180。半导体器件400还可以包括元件隔离层107和间隔物150。
源/漏极区410可以设置为连接在两个有源鳍105上。此外，每个源/漏极区410可以包括第一外延层411、第二外延层413、第三外延层415和第四外延层417。
第一外延层411设置在有源鳍105上，而第二外延层413可以设置在第一外延层411上。第三外延层415可以从第二外延层413生长，并且可以在有源鳍105上彼此连接。第三外延层415可以具有相对于衬底101的上表面倾斜的表面415S。第三外延层415的表面415S可以对应于晶体学表面。例如，当第三外延层415由硅锗形成时，第三外延层415的表面415S可以是平面，例如{111}面。
第四外延层417可以设置在第三外延层415的连接区域上。第四外延层417可以设置在第三外延层415的倾斜表面415S上，在第三外延层415之间彼此相邻以“V”形状彼此相对。
第一外延层411、第二外延层413、第三外延层415和第四外延层417可以包含不同浓度的元素和/或掺杂元素。
例如，第一外延层411可以包含具有第一浓度的锗，第二外延层413可以包含具有高于第一浓度的第二浓度的锗，以及第三外延层415可以包含具有高于第二浓度的第三浓度的锗。第四外延层417可以包含具有高于第三浓度的第四浓度的锗。
接触插塞180的下端可以同时连接到具有不同的锗浓度和硼浓度的第三外延层415和第四外延层417。随着在形成接触孔期间蚀刻深度的变化，与接触插塞180的下端接触的第三外延层415与第四外延层417的比率变得不同，因此可能发生接触插塞180与源/漏极区410之间的接触电阻的变化。在形成接触孔期间，当蚀刻深度加深时，可能增加接触电阻。另一方面，当蚀刻深度浅时，可能降低接触电阻。
如上所述，根据本发明构思的示例实施例，可以提供具有低接触电阻和改进功能的半导体器件。
此外，可以提供具有低接触电阻变化和低功能变化的半导体器件。
虽然已经在上面示出和描述了示例实施例，但是对于本领域技术人员来说显而易见的是，在不脱离由所附权利要求限定的本公开的范围的情况下，可以进行各种修改和变化。

Claims (20)

1.一种半导体器件，所述半导体器件包括：
多个有源鳍，所述多个有源鳍在衬底上；
栅电极，所述栅电极与所述多个有源鳍交叉；以及
源/漏极区，所述源/漏极区在所述多个有源鳍上，并在所述栅电极的第一侧和第二侧延伸，所述源/漏极区包括上外延层和多个下外延层；
其中，所述多个下外延层分别在所述多个有源鳍上并且包含具有第一浓度的锗，
其中，所述上外延层在所述多个下外延层上并且包含具有高于所述第一浓度的第二浓度的锗，并且
其中，所述多个下外延层具有凸的上表面，并且在所述有源鳍之间彼此连接。
2.根据权利要求1所述的半导体器件，
其中，所述上外延层包括相对于所述衬底的上表面倾斜的倾斜侧表面，并且
其中，所述上外延层的上部与彼此连接的所述多个下外延层交叠。
3.根据权利要求2所述的半导体器件，其中，所述上外延层具有上表面，所述上表面是平坦的并且在所述倾斜侧表面之间。
4.根据权利要求2所述的半导体器件，其中，所述上外延层具有上表面，所述上表面是凹的并且在所述倾斜侧表面之间。
5.根据权利要求2所述的半导体器件，
其中，所述上外延层具有在所述倾斜侧表面之间的凹槽，并且
其中，所述上外延层具有尖的突出部分。
6.根据权利要求1所述的半导体器件，
其中，所述源/漏极区包含硅和锗，
其中，所述锗的第一浓度为45at％至60at％，并且
其中，所述锗的第二浓度为60at％至90at％。
7.根据权利要求1所述的半导体器件，所述半导体器件还包括：
接触插塞，所述接触插塞在所述源/漏极区上，
其中，所述接触插塞与所述上外延层接触。
8.根据权利要求7所述的半导体器件，其中，所述接触插塞包括物理地接触所述源/漏极区的硅化物层。
9.根据权利要求1所述的半导体器件，
其中，所述多个有源鳍在所述栅电极的所述第一侧和所述第二侧具有凹陷区域，并且
其中，所述源/漏极区在所述凹陷区域中。
10.根据权利要求1所述的半导体器件，其中，所述上外延层所包含的掺杂剂的第三浓度高于所述多个下外延层中的所述掺杂剂的第四浓度。
11.根据权利要求1所述的半导体器件，所述半导体器件还包括：
元件隔离层，所述元件隔离层用于将所述多个有源鳍彼此分隔开，以及
气隙，所述气隙位于所述多个下外延层与所述元件隔离层之间。
12.根据权利要求1所述的半导体器件，
其中，所述源/漏极区还包括在所述上外延层上的覆盖层，并且
其中，所述覆盖层包含硅。
13.一种半导体器件，所述半导体器件包括：
多个有源鳍，所述多个有源鳍在衬底上；
栅电极，所述栅电极与所述多个有源鳍交叉；以及
源/漏极区，所述源/漏极区在所述多个有源鳍上，并在所述栅电极的第一侧和第二侧延伸，所述源/漏极区包括第一外延层、第二外延层、第三外延层和第四外延层，
其中，所述第一外延层在所述多个有源鳍中的一些有源鳍上并且包含具有第一浓度的锗，
其中，所述第二外延层在所述第一外延层上并且包含具有高于所述第一浓度的第二浓度的锗，
其中，所述第三外延层在所述第二外延层上并且包含具有高于所述第二浓度的第三浓度的锗，
其中，所述第四外延层包含具有高于所述第三浓度的第四浓度的锗，
其中，所述第四外延层在所述第三外延层上，并且
其中，所述第三外延层具有凸的上表面，并且在所述多个有源鳍中的一些有源鳍之间彼此连接。
14.根据权利要求13所述的半导体器件，
其中，所述第四外延层包括相对于所述衬底的第一上表面倾斜的倾斜侧表面，并且
其中，所述第四外延层还包括第二上表面，所述第二上表面在所述倾斜侧表面之间是平坦的或凹的。
15.根据权利要求13所述的半导体器件，
其中，所述第四外延层包括相对于所述衬底的第一上表面倾斜的倾斜侧表面，并且
其中，所述第四外延层还包括在所述倾斜侧表面之间的凹槽。
16.根据权利要求13所述的半导体器件，
其中，所述源/漏极区包含硅和锗，
其中，所述锗的第一浓度为5at％至25at％，
其中，所述锗的第二浓度为25at％至45at％，
其中，所述锗的第三浓度为45at％至60at％，并且
其中，所述锗的第四浓度为60at％至90at％。
17.根据权利要求13所述的半导体器件，所述半导体器件还包括：
在所述源/漏极区上并与所述第四外延层接触的接触插塞。
18.根据权利要求13所述的半导体器件，其中，所述第一外延层、所述第二外延层、所述第三外延层和所述第四外延层包含不同浓度的硼。
19.根据权利要求13所述的半导体器件，
其中，所述源/漏极区还包括在所述第四外延层上的覆盖层，并且
其中，所述覆盖层由硅形成。
20.一种半导体器件，包括：
多个有源鳍，所述多个有源鳍在衬底上；
栅电极，所述栅电极与所述多个有源鳍交叉；
源/漏极区，所述源/漏极区在所述多个有源鳍上，并在所述栅电极的第一侧和第二侧延伸，以及
接触插塞，所述接触插塞在所述源/漏极区上，
其中，所述源/漏极区包括第一外延层、第二外延层、第三外延层和第四外延层，
其中，所述第一外延层在所述多个有源鳍中的一些有源鳍上并且包含具有第一浓度的锗，
其中，所述第二外延层在所述第一外延层上并且包含具有高于所述第一浓度的第二浓度的锗，
其中，所述第三外延层在所述第二外延层上并且包含具有高于所述第二浓度的第三浓度的锗，
其中，所述第四外延层包含具有高于所述第三浓度的第四浓度的锗，
其中，所述第四外延层在所述第三外延层上，
其中，所述第三外延层具有凸的上表面，并且在所述多个有源鳍中的一些有源鳍之间彼此连接，并且
其中，所述接触插塞与所述第四外延层接触。
CN201910412594.XA 2018-06-20 2019-05-17 半导体器件 Pending CN110620150A (zh)

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