US9633905B2 - Semiconductor fin structures and methods for forming the same - Google Patents

Semiconductor fin structures and methods for forming the same Download PDF

Info

Publication number
US9633905B2
US9633905B2 US13/452,516 US201213452516A US9633905B2 US 9633905 B2 US9633905 B2 US 9633905B2 US 201213452516 A US201213452516 A US 201213452516A US 9633905 B2 US9633905 B2 US 9633905B2
Authority
US
United States
Prior art keywords
plurality
fin
sti
fins
semiconductor fins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US13/452,516
Other versions
US20130277759A1 (en
Inventor
Ryan Chia-Jen Chen
Yih-Ann Lin
Chia Tai Lin
Chao-Cheng Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co (TSMC) Ltd filed Critical Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
Priority to US13/452,516 priority Critical patent/US9633905B2/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, CHIA TAI, LIN, YIH-ANN, CHEN, CHAO-CHENG, CHEN, RYAN CHIA-JEN
Publication of US20130277759A1 publication Critical patent/US20130277759A1/en
Application granted granted Critical
Publication of US9633905B2 publication Critical patent/US9633905B2/en
Application status is Active legal-status Critical
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Abstract

A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

Description

BACKGROUND

With the increasing down-scaling of integrated circuits and the increasingly demanding requirements to the speed of integrated circuits, transistors need to have higher drive currents with smaller dimensions. Fin Field-Effect Transistors (FinFET) were thus developed. FinFETs have increased channel widths. The increase in the channel width is achieved by forming channels that include portions on the sidewalls of the fins and portions on the top surfaces of the fins.

With the increasing down-scaling of integrated circuits, fins also become increasingly thinner, and the aspect ratios of the gaps between the fins become increasingly greater. The formation processes of the fins thus are more prone to the process variations in the respective manufacturing processes. In conventional FinFET manufacturing processes, the hard masks for forming the fins are defined first. The hard masks are then used as etching masks to etch the underlying semiconductor substrates, and the patterns of the hard masks are transferred to the underlying semiconductor substrates to from fins. In the etching of the semiconductor substrates, since the hard masks have pattern-dense regions and pattern-sparse regions, the pattern loading effect causes the fins in the pattern-dense regions and the pattern-sparse regions to be different from each other. The respective FinFETs are thus adversely affected.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 18 are cross-sectional views of intermediate stages in the manufacturing of Fin Field-Effect Transistors (FinFET) in accordance with some exemplary embodiments; and

FIGS. 19 through 24B are cross-sectional views of intermediate stages in the manufacturing of FinFETs in accordance with some alternative embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.

A method of forming semiconductor fins, which may be used for forming Fin Field-Effect Transistors (FinFETs), and the respective structures are provided in accordance with various exemplary embodiments. The intermediate stages of forming the semiconductor fins are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS. 1 through 18 illustrate cross-sectional views of intermediate stages in the formation of semiconductor fins, isolation regions, and FinFETs in accordance with various embodiments. FIG. 1 illustrates wafer 100, which includes substrate 20 and overlying layers. Substrate 20 may be formed of a semiconductor material such as silicon, silicon germanium, or the like. In some embodiments, substrate 20 is a crystalline semiconductor substrate such as a crystalline silicon substrate. Pad oxide layer 22 and hard mask 24 are formed over substrate 20. In accordance with embodiments, pad oxide layer 22 comprises silicon oxide. Hard mask 24 may be formed of silicon nitride.

A plurality of layers is formed over hard mask 24. In some exemplary embodiments, the plurality of layers includes oxide layers 26 and 30, hard masks 28, 32, and 38, silicon oxynitride layer 40, and Bottom Anti-Reflective Coating (BARC) 42. It is appreciated that the layers illustrated in FIG. 1 is exemplary. In alternative embodiments, different layers may be formed over substrate 20, and the number of layers may also be different from what is shown in FIG. 1. Oxide layers 26 and 30 may be Plasma Enhanced (PE) oxides, which may be silicon oxide layers that are formed using Plasma Enhanced Chemical Vapor Deposition (PECVD). Hard mask 28 and 32 may comprise an Ashing Removable Dielectric (ARD) material, and hence is referred to as ARDs 28 and 32 hereinafter, although they may also be formed of other materials. In some embodiments, hard mask 38, which may also be an ARD, may include amorphous carbon. Silicon oxynitride layer 40 may be formed over hard mask 38. BARC 42 and silicon oxynitride layer 40 may be used for lithography purposes, for example, for reducing the reflection of the yellow light used in the exposure of the overlying photo resist 44.

FIGS. 1 and 2 also illustrate a lithography process for patterning ARD 32. Photo resist 44 is formed over BARC 42, and is then patterned. Layers 32, 38, 40, 42, and photo resist 44 are used to form patterns with small pitches, which may be less than the minimum pitch allowed by the lithography process used for forming the integrated circuits. Layers 22, 26, 28, and 30 are used to transfer the small pitches to substrate 20. In some embodiments, the minimum pitch P1 of photo resist 44 may be close to, or equal to, the minimum pitch allowed by the technology for developing photo resist 44 and for performing the etch using photo resist 44 as an etching mask.

BARC 42, silicon oxynitride layer 40, and ARDs 38 and 32 are etched, for example, using plasma-assisted dry etching, followed by the removal of photo resist 44, BARC 42, and layers 40 and 38. The resulting structure is shown in FIG. 2. The remaining portions of hard mask 32 are referred to as mandrels 46 hereinafter. The pitches of mandrels 46 may be substantially equal to the respective pitch P1 of photo resist 44 (FIG. 1).

Next, as shown in FIG. 3, spacer layer 48 is deposited using a conformal deposition method. In some embodiments, spacer layer 48 is deposited using Atomic Layer Deposition (ALD), which may form a high quality film that has a low etching rate. The ALD may be performed using DiChloroSilane (DCS) and ammonia as precursors, and the resulting spacer layer 48 may include silicon nitride or silicon-rich nitride. In alternative embodiments, other conformal deposition methods, such as Low-Pressure Chemical Vapor Deposition (LPCVD), may be performed. Thickness T1 of spacer layer 48 may be less than a half of, and may be close to about a third of, pitch P1 of mandrels 46 in some exemplary embodiments.

Referring to FIG. 4, the horizontal portions of spacer layer 48 are removed, for example, through an anisotropic etching step. The vertical portions of spacer layer 48 are left, and are referred to as spacers 50 hereinafter. Next, as shown in FIG. 5, mandrels 46 are removed in an etching step, and spacers 50 remain. Pitches P2 of spacers 50 may be a half of pitch P1 in FIG. 1. In some embodiments, pitch P2 is smaller than the minimum pitch.

FIGS. 6 through 8B illustrate the first patterning process of spacers 50. Referring to FIG. 6, bottom layer 52 is formed over spacers 50. Bottom layer 52 may contain a photo resist. Middle layer 54 is then formed over bottom layer 52. Middle layer 54 may be formed of an oxide-like photo resist, although other materials may be used. Bottom layer 52 and middle layer 54 may be formed using spin-on coating. Following the formation of middle layer 54, photo resist 56 is formed and patterned.

Middle layer 54 and bottom layer 52 are patterned according to the pattern of photo resist 56. Photo resist 56 is then removed. The resulting structure is shown in FIGS. 7A and 7B. FIG. 7A illustrates a cross-sectional view and FIG. 7B illustrates a top view. It is illustrated that spacers 50 include a plurality of strips that are parallel to each other. The strips 50 may have a uniform pitch P2. The patterned bottom layer 52 and middle layer 54 form masks that cover portions of spacers 50, while some other portions of spacers 50 are not covered.

In FIGS. 8A and 8B, which are a cross-sectional view and a top view, respectively, the exposed portions of spacers 50 that are not covered by bottom layer 52 and middle layer 54 are removed. Accordingly, spacers 50 are cut into a plurality of separate shorter strips. Bottom layer 52 and middle layer 54 are then removed.

FIGS. 9 and 10 illustrate the patterning of an additional pattern that is used to etch substrate 20, which pattern may have a greater width than the widths of spacers 50. Referring to FIG. 9, bottom layer 58 and middle layer 60 are formed, and photo resist 62 is formed over layers 58 and 60, and then patterned. Bottom layer 58 and middle layer 60 are then patterned, as shown in FIG. 10. Photo resist 62 is then removed. Next, as shown in FIG. 11, hard mask layer 28 is etched using spacers 50 and the patterned bottom layer 58 and middle layer 60 as an etching mask. The patterns of spacers 50 and the patterned bottom layer 58 and middle layer 60 are thus transferred into hard mask 28.

Next, hard mask 28 is used as an etching mask to etch underlying layers including pad oxide layer 22, silicon nitride layer 24, and PE oxide layer 26. Substrate 20 is also etched. Hard mask 28 is then removed, and the resulting structure is shown in FIG. 12. The portions of substrate 20 underlying spacers 50 (FIG. 10) form semiconductor fins 64. Recesses 66 are also formed in substrate 20, and separate semiconductor fins 64 from each other. Semiconductor fins 64 include two edge fins, and inner fins between the edge fins. The inner fins 64 have substantially the same width W2 (critical dimension, also see width W2 in FIG. 23) as the edge fins 64. Furthermore, the profiles of the inner fins 64 are substantially the same as that of edge fins 64, wherein the profiles may include for example, shapes, the tilt angles of edges, and the like.

Next, as shown in FIG. 13, substrate 20 is further etched to extend recesses 66 downwardly. This step may be referred to as Shallow Trench Isolation (STI) etching since the extended portions of recesses 66 that are formed in this step will be filled to form STI regions later, while the portions of fins 64 formed in the step in FIG. 12 may be used to form the fins of FinFETs. The portions of substrate 20, which form strips between the extended portions of recesses 66, are referred to as fin extensions 68 hereinafter, although fin extensions 68 are also parts of fins. At the same time fins 64 and fin extensions 68 are formed, large active region 69 is also formed.

FIGS. 14 through 17B illustrate second patterning process for the further patterning of fins 64. In FIG. 14, bottom layer 70 and middle layer 72 are formed, followed by the formation and the patterning of photo resist 74. Bottom layer 70 may be formed of a material similar to the material of bottom layer 52 (FIG. 6). Middle layer 72 may also be formed of a material similar to the material of middle layer 54. Next, as shown in FIG. 15, photo resist 74 is used as an etching mask to pattern bottom layer 70 and middle layer 72. In some embodiments, the patterned bottom layer 70 and middle layer 72 overlap large active region 69 and a first plurality of fins 64, and do not overlap a second plurality of fins 64. Photo resist 74 is then removed.

Next, as shown in FIG. 16A, the second plurality of fins 64 is removed, and the first plurality of fins 64 remains un-removed. In some embodiments, some bottom portions of fin extensions 68 also remain, and are referred to as fin extension residues 68′ hereafter. The height H1 of the remaining fin extension residues 68′ may be greater than about 50 Å in some embodiments, although height H1 may also be greater or smaller. FIG. 16B illustrates a top view of the structure shown in FIG. 16A, wherein fin extension residues 68′ are illustrated using dashed lines. Next, as shown in FIGS. 17A and 17B, which illustrate a cross-sectional view and a top view, respectively, the patterned bottom layer 70 and middle layer 72 are removed.

Referring to FIG. 18, isolation regions such as STI regions 76 are filled into recesses 66, and then recessed. A Chemical Mechanical Polish (CMP) is performed to level the top surface of STI regions 76. STI regions 76 have bottom surfaces 76A substantially level with each other. Fin extension residues 68′ may extend into edge STI regions 76 from the bottom surfaces of the edge STI regions 76. Furthermore, the top surfaces of fin extension residues 68′ may contact bottom surfaces 76B of the edge STI region 76. The remaining portions of layers 22 and 24 are also removed.

As also shown in FIG. 18, FinFET 82 is formed on fins 64. FinFET 82 includes gate dielectric 78 and gate electrode 80. In the resulting structure, it is observed that fin extension residues 68′ extend up into edge STI regions 76, and are encircled by edge STI regions 76. It is also observed that pitch P2 of fin extension residues 68′ and its neighboring fin 64 may be the same as pitch P2 between neighboring fin extensions 68. Furthermore, widths W2 of fin extensions 68 may be substantially the same as widths W2 of fin extension residues 68′.

FIGS. 19 through 24B illustrate cross-sectional views of intermediate stages in the formation of fins and FinFETs in accordance with alternative embodiments. Unless specified otherwise, the materials and formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments shown in FIGS. 1 through 18. The formation details of the embodiments shown in FIGS. 19 through 24B may thus be found in the discussion of the embodiments shown in FIGS. 1 through 18.

The initial steps of these embodiments are essentially the same as shown in FIGS. 1 through 12. In a subsequent step as in FIG. 19, the STI etch as shown in FIG. 13 is skipped. Instead, bottom layer 70 and middle layer 72 are formed, followed by the formation of photo resist 74. Next, as shown in FIG. 20, photo resist 74 is used as an etching mask to pattern bottom layer 70 and middle layer 72. In some embodiments, the patterned bottom layer 70 and middle layer 72 overlap large active region 69 and a first plurality of fins 64, and do not overlap a second plurality of fins 64. Photo resist 74 is then removed. In subsequent steps as shown in FIGS. 20 and 21, bottom layer 70 and middle layer 72 are used as an etching mask to etch portions of layers 22 and 24 that are not covered, until the second plurality of fins 64 is exposed. Next, as shown in FIGS. 21 and 22, the second plurality of fins 64 is etched. In some embodiments, at the same time the second plurality of fins 64 is etched, bottom layer 70 and middle layer 72 are also etched, so that recess 84 is formed in substrate 20. Bottom layer 70 and middle layer 72 are then removed, and the resulting structure is shown in FIG. 23.

Referring to FIG. 23, fin extension residue 68′ is formed as a resulting of the etching, and extends into recess 84 from bottom. Recess 84 includes portions 84A on opposite sides of fin extension residue 68′. Recess 84 further includes portion 84B over and joined to portions 84A, wherein the bottom surface of portion 84B is higher than the bottom surface of portions 84A. One of recess portions 84A may have pitch P2 from the nearest fin 64, which pitch may be the same as the pitch P2 of fins 64. Furthermore, the width W2 of recess portions 84A may be substantially the same as the width W2 of fins 64. In Addition, width W3 of fin extension residue 68′ may be substantially the same as fin spacing S1 between fins 64.

FIG. 24A illustrates the formation of FinFET 82, and the corresponding gate dielectric 78 and gate electrode 80. STI region 76 is also formed in recess 84 and then recessed. In the source and drain regions of FinFET 82, the epitaxially grown semiconductor region 86 merge with each other to form a crown-shaped region 86.

FIG. 24B illustrates FinFET 82 in accordance with alternative embodiments, wherein STI portions 76″ (and the corresponding STI regions) are formed between fin extension residues 68′. STI portion 76″ has a first bottom surface, whose bottom surface is lower than the bottom surface of STI portion 76′.

In FIGS. 18, 24A, and 24B, it is observed that STI regions 76 have non-flat bottom surfaces. Furthermore, the topography of the bottom surfaces of STI regions 76 reflects the patterns of spacers 50 (FIG. 5). Accordingly, the spacings and the widths of some portions of STI regions 76 are the same as the spacings and widths (such as S1, W2, W3, and the like), of respective spacers 50.

By using the embodiments, the semiconductor fins are patterned after their formation. Accordingly, since the dense and isolation regions, which are the results of the patterning, occur after the formation of fins 64, the pattern loading effect is avoided.

In accordance with embodiments, a device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. An STI region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

In accordance with other embodiments, a device includes a semiconductor substrate, a plurality of STI regions in the semiconductor substrate, and a plurality of semiconductor fins parallel to each other and in the semiconductor substrate. A plurality of fin extensions is disposed underlying and aligned to the plurality of semiconductor fins, wherein the plurality of STI regions is disposed between the plurality of fin extensions. An edge STI region is disposed on a side of the plurality of fin extensions, wherein the edge STI region has a first bottom surface substantially level with bottom surfaces of the plurality of STI regions, and a second bottom surface higher than the first bottom surface. A fin extension residue has a bottom substantially level with bottoms of the plurality of fin extensions, wherein the fin extension residue extends into the edge STI region. A top surface of the fin extension residue is in contact with the second bottom surface of the edge STI region.

In accordance with yet other embodiments, a method includes forming a patterned mask including a plurality of strips, and etching a semiconductor substrate underlying the patterned mask to form a first and the second plurality of semiconductor fins. The patterned mask is used as an etching mask. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. A recess is formed in the semiconductor substrate by the step of etching the second plurality of semiconductor fins. The recess is filled with a dielectric material to form an isolation region, wherein the first plurality of semiconductor fins is over a top surface of the isolation region.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.

Claims (9)

What is claimed is:
1. A device comprising:
a semiconductor substrate;
a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate;
a Shallow Trench Isolation (STI) region on a side of the plurality of semiconductor fins, wherein the STI region comprises a top surface and a non-flat bottom surface, and wherein the plurality of semiconductor fins is over the top surface of the STI region;
a plurality of STI regions in the semiconductor substrate;
a plurality of fin extensions underlying and aligned to the plurality of semiconductor fins, wherein sidewalls of the plurality of fin extensions are in contact with sidewalls of the plurality of STI regions; and
a fin extension residue having a bottom substantially level with bottom surfaces of the plurality of fin extensions, wherein the fin extension residue extends into the STI region from a bottom surface of the STI region.
2. The device of claim 1, wherein the plurality of fin extensions has a first pitch, and wherein the fin extension residue and a nearest one of the plurality of semiconductor fins have a second pitch substantially equal to the first pitch.
3. The device of claim 1, wherein the fin extension residue has a width substantially equal to a width of one of the plurality of fin extensions.
4. A device comprising:
a semiconductor substrate;
a plurality of Shallow Trench Isolation (STI) regions in the semiconductor substrate;
a plurality of semiconductor fins parallel to each other and in the semiconductor substrate;
a plurality of fin extensions underlying and aligned to the plurality of semiconductor fins, wherein the plurality of STI regions is disposed between the plurality of fin extensions;
an edge STI region on a side of the plurality of fin extensions, wherein the edge STI region comprises a first bottom surface substantially level with bottom surfaces of the plurality of STI regions, and a second bottom surface higher than the first bottom surface; and
a fin extension residue having a bottom substantially level with bottoms of the plurality of fin extensions, wherein the fin extension residue extends into the edge STI region, and wherein a top surface of the fin extension residue is in contact with the second bottom surface of the edge STI region.
5. The device of claim 4, wherein the first bottom surface of the edge STI region comprises portions on opposite sides of the second bottom surface of the edge STI region.
6. The device of claim 4, wherein the edge STI region comprises portions encircling the fin extension residue.
7. The device of claim 4 further comprising:
a gate dielectric on sidewalls and top surfaces of the plurality of semiconductor fins; and
a gate electrode over the gate dielectric, wherein the gate electrode overlaps the edge STI region.
8. The device of claim 4, wherein the fin extension residue and a nearest one of the plurality of fin extensions have a pitch substantially equal to a pitch of the plurality of semiconductor fins.
9. The device of claim 4, wherein the fin extension residue has a width substantially equal to a width of one of the plurality of fin extensions.
US13/452,516 2012-04-20 2012-04-20 Semiconductor fin structures and methods for forming the same Active 2034-06-06 US9633905B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/452,516 US9633905B2 (en) 2012-04-20 2012-04-20 Semiconductor fin structures and methods for forming the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/452,516 US9633905B2 (en) 2012-04-20 2012-04-20 Semiconductor fin structures and methods for forming the same
US15/493,663 US10083872B2 (en) 2012-04-20 2017-04-21 Methods for forming Fin field-effect transistors
US16/024,220 US20180323108A1 (en) 2012-04-20 2018-06-29 Methods for Forming Fin Field-Effect Transistors

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/493,663 Division US10083872B2 (en) 2012-04-20 2017-04-21 Methods for forming Fin field-effect transistors

Publications (2)

Publication Number Publication Date
US20130277759A1 US20130277759A1 (en) 2013-10-24
US9633905B2 true US9633905B2 (en) 2017-04-25

Family

ID=49379313

Family Applications (3)

Application Number Title Priority Date Filing Date
US13/452,516 Active 2034-06-06 US9633905B2 (en) 2012-04-20 2012-04-20 Semiconductor fin structures and methods for forming the same
US15/493,663 Active US10083872B2 (en) 2012-04-20 2017-04-21 Methods for forming Fin field-effect transistors
US16/024,220 Pending US20180323108A1 (en) 2012-04-20 2018-06-29 Methods for Forming Fin Field-Effect Transistors

Family Applications After (2)

Application Number Title Priority Date Filing Date
US15/493,663 Active US10083872B2 (en) 2012-04-20 2017-04-21 Methods for forming Fin field-effect transistors
US16/024,220 Pending US20180323108A1 (en) 2012-04-20 2018-06-29 Methods for Forming Fin Field-Effect Transistors

Country Status (1)

Country Link
US (3) US9633905B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180033740A1 (en) * 2016-07-29 2018-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy Fin Etch to Form Recesses in Substrate

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9515184B2 (en) * 2013-09-12 2016-12-06 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with multiple-height fins and substrate trenches
US20150206759A1 (en) 2014-01-21 2015-07-23 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US9190496B2 (en) * 2014-01-23 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
CN105374871A (en) 2014-08-22 2016-03-02 联华电子股份有限公司 Method of forming a fin structure and
TWI621210B (en) * 2014-08-27 2018-04-11 聯華電子股份有限公司 Method for fabricating semiconductor device
US9536985B2 (en) 2014-09-29 2017-01-03 Globalfoundries Inc. Epitaxial growth of material on source/drain regions of FinFET structure
KR20160087231A (en) 2015-01-13 2016-07-21 삼성전자주식회사 Semiconductor device and the fabricating method thereof
CN105990149A (en) * 2015-03-03 2016-10-05 联华电子股份有限公司 Method for manufacturing semiconductor device
TWI648857B (en) 2015-05-07 2019-01-21 聯華電子股份有限公司 Semiconductor device and manufacturing method thereof
US10147805B2 (en) * 2015-07-31 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd Structure and formation method of semiconductor device structure with a dummy fin structure
US9607985B1 (en) 2015-09-25 2017-03-28 United Microelectronics Corp. Semiconductor device and method of fabricating the same
TW201717314A (en) 2015-11-12 2017-05-16 聯華電子股份有限公司 FinFET and method of fabricating the same
US9466534B1 (en) * 2015-12-09 2016-10-11 International Business Machines Corporation Cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning with improved design flexibility
US9941279B2 (en) * 2016-05-23 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure having fins and method for manufacturing the same
CN108417631A (en) * 2017-02-09 2018-08-17 联华电子股份有限公司 The method of insulating layer and removal fin structure by fin structure
US10217633B2 (en) * 2017-03-13 2019-02-26 Globalfoundries Inc. Substantially defect-free polysilicon gate arrays
US10283639B2 (en) * 2017-09-28 2019-05-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for forming the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7719043B2 (en) * 2004-07-12 2010-05-18 Nec Corporation Semiconductor device with fin-type field effect transistor and manufacturing method thereof.

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100577565B1 (en) * 2004-02-23 2006-05-08 삼성전자주식회사 and method for manufacturing fin Field Effect Transistor
US8217435B2 (en) * 2006-12-22 2012-07-10 Intel Corporation Floating body memory cell having gates favoring different conductivity type regions
US8461008B2 (en) * 2011-08-15 2013-06-11 GlobalFoundries, Inc. Methods for fabricating FinFET integrated circuits in bulk semiconductor substrates
JP2013058688A (en) * 2011-09-09 2013-03-28 Toshiba Corp Semiconductor device manufacturing method
US8669186B2 (en) * 2012-01-26 2014-03-11 Globalfoundries Inc. Methods of forming SRAM devices using sidewall image transfer techniques

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7719043B2 (en) * 2004-07-12 2010-05-18 Nec Corporation Semiconductor device with fin-type field effect transistor and manufacturing method thereof.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180033740A1 (en) * 2016-07-29 2018-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy Fin Etch to Form Recesses in Substrate
US10297555B2 (en) * 2016-07-29 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure having crown-shaped semiconductor strips and recesses in the substrate from etched dummy fins

Also Published As

Publication number Publication date
US20170229348A1 (en) 2017-08-10
US20130277759A1 (en) 2013-10-24
US10083872B2 (en) 2018-09-25
US20180323108A1 (en) 2018-11-08

Similar Documents

Publication Publication Date Title
US8927362B2 (en) CMOS device and method of forming the same
US9324866B2 (en) Structure and method for transistor with line end extension
KR101302956B1 (en) A cmos finfet device and method of forming the same
US9269632B2 (en) FinFET device and method of manufacturing same
US8723271B2 (en) Voids in STI regions for forming bulk FinFETs
US9147594B2 (en) Method for fabricating a strained structure
US8617996B1 (en) Fin removal method
CN103066123B (en) FinFET device and manufacturing method thereof
US8679925B2 (en) Methods of manufacturing semiconductor devices and transistors
US9953885B2 (en) STI shape near fin bottom of Si fin in bulk FinFET
US8895446B2 (en) Fin deformation modulation
US20080113483A1 (en) Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures
TWI572035B (en) Semiconductor device and manufacturing method thereof
KR101496519B1 (en) Dummy FinFET Structure and Method of Making Same
US9466696B2 (en) FinFETs and methods for forming the same
US20160225765A1 (en) Multi-Fin Device and Method of Making Same
CN102054705B (en) Method of forming an integrated circuit structure
US20090186475A1 (en) Method of manufacturing a MOS transistor
KR20140111575A (en) Finfet with rounded source/drain profile
US9543210B2 (en) Forming crown active regions for FinFETs
TWI508147B (en) Semiconductor devices and methods for forming the same
TWI542007B (en) Method therewith element
KR101871748B1 (en) Method for forming pattern of semiconductor device
US9508850B2 (en) Epitaxial block layer for a fin field effect transistor device
KR101546161B1 (en) High efficiency finfet diode

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, RYAN CHIA-JEN;LIN, YIH-ANN;LIN, CHIA TAI;AND OTHERS;SIGNING DATES FROM 20120411 TO 20120418;REEL/FRAME:028555/0738

STCF Information on status: patent grant

Free format text: PATENTED CASE