TW201730987A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201730987A
TW201730987A TW105124582A TW105124582A TW201730987A TW 201730987 A TW201730987 A TW 201730987A TW 105124582 A TW105124582 A TW 105124582A TW 105124582 A TW105124582 A TW 105124582A TW 201730987 A TW201730987 A TW 201730987A
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Taiwan
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gate
layer
gate structure
dielectric layer
semiconductor device
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TW105124582A
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TWI619178B (zh
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謝志宏
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台灣積體電路製造股份有限公司
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract

一種半導體裝置，包含第一鰭式場效電晶體與第二鰭式場效電晶體，二者分別具有第一通道區與第二通道區。第一鰭式場效電晶體與第二鰭式場效電晶體分別具有第一閘結構與第二閘結構。第一閘結構與第二閘結構具有形成於第一通道區與第二通道區上方的第一閘介電層與第二閘介電層、形成於第一閘介電層與第二閘介電層上方的第一閘極層與第二閘極層。第一閘結構與第二閘結構沿著第一方向對準。第一閘結構與第二閘結構藉由一絕緣材料製的一分離插塞而分離。上述第一閘極層是與上述分離插塞的一側壁接觸。

Description

半導體裝置及其製造方法
本發明是關於一種半導體積體電路，特別是關於具有鰭結構的一種半導體裝置及其製造方法。
為了追求更高的裝置密度、更高的效能以及更低的成本，半導體工業已經發展到奈米技術的製程，伴隨而來的是來自製造與設計二者的議題的挑戰，結果發展出例如鰭式場效電晶體(fin field-effect transistor；Fin FET)等的三維的設計。鰭式場效電晶體通常具有高的高寬比的半導體鰭，而半導體電晶體裝置的通道區、源極區、汲極區則形成於上述半導體鰭中。閘極則沿著上述鰭結構的側面形成且形成在其上方，利用通道區、源極區、汲極區的增加的表面積以製造更快速、具有更高可靠度且可更良好地控制的半導體電晶體裝置。在鰭式場效電晶體中，通常使用與具有高介電常數的一高介電常數的閘介電層配合的一金屬閘結構，且此金屬閘結構是藉由一閘取代技術而製造。
本發明的一實施形態是提供一種半導體裝置，其包含：一第一鰭式場效電晶體與一第二鰭式場效電晶體。上述第一鰭式場效電晶體具有一第一鰭結構與一第一閘結構，上述 第一鰭結構在一第一方向延伸，上述第一閘結構具有一第一閘介電層與一第一閘極層，上述第一閘介電層形成於上述第一鰭結構的上方，上述第一閘極層形成於該第一閘介電層的上方並在垂直於上述第一方向的一第二方向延伸。上述第二鰭式場效電晶體具有一第二鰭結構與一第二閘結構，上述第二鰭結構在上述第一方向延伸，上述第二閘結構具有一第二閘介電層與一第二閘極層，上述第二閘介電層形成於上述第二鰭結構的上方，上述第二閘極層形成於上述第二閘介電層的上方並在垂直於上述第二方向延伸。上述第一閘結構與上述第二閘結構是沿著上述第二方向對準，上述第一閘結構與上述第二閘結構是藉由一絕緣材料製的一分離插塞而分離。上述第一閘極層是與上述分離插塞的一側壁接觸。
在上述半導體裝置的一實施例中，上述第一閘極層包含複數個第一底層與一第一主要金屬閘極層，上述第一底層與上述第一主要金屬閘極層是形成在上述第一鰭結構的上方。此外，上述第一主要金屬閘極層是與上述分離插塞的上述側壁接觸。
在上述半導體裝置的一實施例中，上述分離插塞是由氮化矽類的材料構成。
在上述半導體裝置的一實施例中，上述第二閘極層包含一第二底層與一第二主要金屬閘極層，上述第二底層與上述第二主要金屬閘極層是形成在上述第二鰭結構的上方。此外，上述第二主要金屬閘極層是與上述分離插塞的上述側壁接觸。
在上述半導體裝置的一實施例中，上述第一閘介電層之沿著上述第二方向的一最上部是位於上述第一鰭結構的上方。
在上述半導體裝置的一實施例中，上述第一底層之沿著上述第二方向的最上部是位於上述第一鰭結構的上方。
在上述半導體裝置的一實施例中，上述第一閘結構具有一第一端與一第二端；上述分離插塞是置於上述第一端。此外，另一分離插塞是置於上述第二端。
在上述半導體裝置的一實施例中，上述第一閘結構具有一第一端與一第二端；上述分離插塞是置於上述第一端。此外，無任何分離插塞置於上述第二端。
在上述半導體裝置的一實施例中，在上述第二端，上述第一閘極層並未與另一分離插塞的側壁接觸。
本發明的另一實施形態是提供一種半導體裝置，其包含：一第一鰭式場效電晶體與一第二鰭式場效電晶體。上述第一鰭式場效電晶體具有一半導體基底的一第一通道區與一第一閘結構，上述第一閘結構具有一第一閘介電層與一第一閘極層，上述第一閘介電層是形成於上述第一通道區的上方，上述第一閘極層是形成於上述第一閘介電層的上方並在一第一方向延伸。上述第二鰭式場效電晶體具有上述半導體基底的一第二通道區與一第二閘結構，上述第二閘結構具有一第二閘介電層與一第二閘極層，上述第二閘介電層是形成於上述第二通道區的上方，上述第二閘極層是形成於上述第二閘介電層的上方並沿著上述第一方向延伸。上述第一閘結構與上述第二閘 結構是沿著上述第一方向對準；上述第一閘結構與上述第二閘結構是藉由一絕緣材料製的一分離插塞而分離。上述第一閘極層是與上述分離插塞的一側壁接觸。
在上述半導體裝置的一實施例中，上述第一閘極層包含複數個第一底層與一第一主要金屬閘極層，上述第一底層與上述第一主要金屬閘極層是形成在上述第一鰭結構的上方。此外，上述第一主要金屬閘極層是與上述分離插塞的上述側壁接觸。
本發明的又另一實施形態是提供一種半導體裝置的製造方法，包含在形成於一基底的上方的複數個通道區的上方，形成一虛設閘結構，上述虛設閘結構具有一虛設閘極層、一虛設閘介電層與置於上述虛設閘介電層的二側的側壁間隔層。此方法還包含在上述虛設閘結構的二側形成層間介電層。此方法還包含在形成上述層間介電層之後，移除上述虛設閘極層，而形成一電極空間。此方法還包含在上述電極空間中形成一閘結構，上述閘結構具有一閘極層。此方法還包含圖形化上述閘結構，而將上述閘結構分離成至少二個分離的閘結構，其具有被一分離開口分離的一第一閘結構與一第二閘結構。此方法還包含藉由以一絕緣材料填入上述分離開口，形成一分離插塞。其中在上述第一閘結構內的上述閘極層是與上述分離插塞的一側壁接觸。
在上述半導體裝置的製造方法的一實施例中，在圖形化上述閘結構的步驟中，將上述閘結構分成三個或超過三個的分離的閘結構。
在上述半導體裝置的製造方法的一實施例中，在形成上述分離開口之後，上述閘極層是被曝露於上述分離開口中。
在上述半導體裝置的製造方法的一實施例中，上述閘結構的圖形化包含：在上述閘結構與該層間介電層的上方形成一罩幕層；圖形化上述罩幕層以形成一開口圖形；以及蝕刻上述閘結構之在上述開口圖形下的部分，以形成上述分離開口。
在上述半導體裝置的製造方法的一實施例中，上述閘極層包含複數個底層與一主要金屬閘極層，上述底層與上述主要金屬閘極層是形成在上述通道區的上方。此外，上述主要金屬閘極層是與上述分離插塞的上述側壁接觸。
在上述半導體裝置的製造方法的一實施例中，上述虛設閘結構還具有一虛設閘介電層與置於上述虛設閘介電層的二側的側壁間隔層。此外，上述電極空間是藉由移除上述虛設閘極層與上述虛設閘介電層而形成。
在上述半導體裝置的製造方法的一實施例中，在上述電極空間中形成上述閘結構的步驟中，上述閘結構是包含一閘介電層。
在上述半導體裝置的製造方法的一實施例中，上述閘結構在被分離之前具有一第一端與一第二端；上述第一閘結構具有上述第一端且上述第一端是與形成上述分離插塞之處的相反端。此外，另一分離插塞是形成於上述第一端。
在上述半導體裝置的製造方法的一實施例中，上 述閘結構在被分離之前具有一第一端與一第二端；上述第一閘結構具有上述第一端且上述第一端是與形成上述分離插塞之處的相反端。此外，無任何分離插塞是形成於上述第一端。
10‧‧‧基底
20‧‧‧鰭結構
25‧‧‧通道區
50、50’‧‧‧絕緣材料層
70、70’‧‧‧層間介電層
80‧‧‧側壁絕緣層
100‧‧‧硬罩幕圖形
105‧‧‧閘絕緣層
106‧‧‧墊氧化物層
107‧‧‧氮化矽罩幕層
110‧‧‧閘層
120‧‧‧閘線開口
130、130’‧‧‧閘介電層
132、132’‧‧‧介面層
134、134’‧‧‧介電材料
140、140’‧‧‧金屬閘極層
142、142’‧‧‧阻障層
144、144’‧‧‧功函數調整層
146、146’‧‧‧黏著或黏結層
148、148’‧‧‧主要的金屬層
150‧‧‧罩幕圖形
155‧‧‧開口
160‧‧‧開口
170、170’‧‧‧分離插塞
B1、B3、B4‧‧‧區域
B2‧‧‧部分
B5、Y1‧‧‧線
D1‧‧‧距離
H1‧‧‧高度
W1、W2‧‧‧寬度
X1‧‧‧線
X、X’、Y、Z‧‧‧方向
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第2圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第3圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第4A圖是一俯視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第4B圖是一透視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第4C圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第4D圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第5A圖是一俯視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第5B圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第5C圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第6A圖是一俯視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第6B圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第6C圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第6D圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第7A圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第7B圖是一透視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第7C圖是一俯視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第8A圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第8B圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第8C圖是一透視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第9A圖是一俯視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第9B圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第9C圖是一剖面圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第9D圖是一透視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第9E圖是一透視圖，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一個階段。
第10A圖是一俯視圖，顯示本發明的另一實施例的具有場效電晶體的半導體裝置的一例示的結構。
第10B圖是一剖面圖，顯示本發明的另一實施例的具有場效電晶體的半導體裝置的一例示的結構。
第11A圖是一俯視圖，顯示本發明的一實施例的具有場效電晶體的半導體裝置的一例示的結構。
第11B圖是一剖面圖，顯示本發明的一實施例的具有場效電晶體的半導體裝置的一例示的結構。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。以下將配合所 附圖式詳述本發明之實施例，其中同樣或類似的元件將盡可能以相同的元件符號表示。在圖式中可能誇大實施例的形狀與厚度以便清楚表面本發明之特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第一特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本說明書以下的揭露內容可能在各個範例中使用重複的元件符號，以使說明內容更加簡化、明確，但是重複的元件符號本身並未指示不同的實施例及/或結構之間的關係。
此外，其與空間相關用詞。例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
另外，在本案專利說明書中，在數值相關敘述後接「以上」、「以下」之詞來敘述數值範圍的情況中，除非另有加註，相關的數值範圍是包含上述「以上」、「以下」之詞前接的數值。
第1~9E圖是一系列的剖面圖、俯視圖及透視圖等，顯示用以製造本發明的一實施例的具有場效電晶體的半導體裝置的例示的製程步驟的一系列的階段。要瞭解的是，在第1~9E圖所示的任一步驟之前、之中或之後，可加入一或多個附加的步驟、操作程序等，且以下所述的部分製程步驟可被取代、刪減或移除，而作為此方法的其他實施例。這些步驟、操作程序等的順序有可能會互換。
第1圖是顯示一例示的剖面圖，其中在一基底10的上方形成有複數個鰭結構20。為了製造如鰭結構20的一鰭結構，會藉由例如一熱氧化製程、一化學氣相沈積(chemical vapor deposition：CVD)或其組合，在如基底10的一基底(例如一半導體晶圓)上，形成一罩幕層。上述基底是例如一p型矽基底，其摻雜物的濃度在約1×1015至約5×1015cm-3的範圍。在其他實施例中，上述基底是一n型矽基底，其摻雜物的濃度在約1×1015至約5×1015cm-3的範圍。
取代上述形態，基底10亦可包含其他的元素半導體、化合物半導體或上述之組合。作為前述其他的元素半導體者，例如為鍺等。上述化合物半導體可以是IV-IV族化合物半導體或III-V族化合物半導體。作為前述IV-IV族化合物半導體者，例如為SiC與SiGe等之一或其組合。作為前述III-V族化合物半導體者，例如為GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP與GaInAsP等之一或其組合。在一實施例中，基底10是一絕緣層上覆矽(SOI；silicon-on insulator)基底的一矽層。使用一絕緣層上覆矽基底 時，上述鰭結構可從上述絕緣層上覆矽基底的上述矽層突出，或可以從上述絕緣層上覆矽基底的絕緣層突出。在後者的情況，上述絕緣層上覆矽基底的矽層是用來形成上述鰭結構。例如無晶形矽、無晶形碳化矽等的無晶形基底或是例如氧化矽等的絕緣材料，亦可用來作為基底10。基底10可包含已被適當地有摻雜不純物(例如具有p型導電形態或n型導電形態)的各種區域。
在某些實施例中，上述罩幕層可包含例如一墊氧化物(pad oxide；例如為氧化矽)層106與一氮化矽罩幕層107。墊氧化物層106的形成，可藉由使用熱氧化或化學氣相沈積製程；而氮化矽罩幕層107的形成，可藉由物理氣相沈積(physical vapor deposition；PVD)製程、化學氣相沈積製程、原子層沈積製程、其他適當的製程或上述之任意組合。作為物理氣相沈積製程者，例如為濺鍍製程等；作為化學氣相沈積製程的選項，例如為電漿增益化學氣相沈積(plasma-enhanced chemical vapor deposition；PECVD)製程、常壓化學氣相沈積(atmospheric pressure chemical vapor deposition；APCVD)製程、低壓化學氣相沈積製程(low-pressure CVD；LPCVD)、高密度化學氣相沈積製程(high density plasma CVD；HDPCVD)等。
在某些實施例中，墊氧化物層106的厚度是在約2nm~約15nm的範圍，而氮化矽罩幕層107的厚度是在約2nm~約50nm的範圍。進一步在上述罩幕層上形成一罩幕圖形。此罩幕圖形例如是藉由微影法而形成的一光阻圖形。
藉由使用上述罩幕圖形作為一蝕刻罩幕，而形成墊氧化物層106與氮化矽罩幕層107的一硬罩幕圖形100。
藉由使用硬罩幕圖形100作為一蝕刻罩幕，藉由使用一乾蝕刻法、一溼蝕刻法之一或其組合的溝槽蝕刻製程，將基底10圖形化而成為複數個鰭結構20。
在一實施例中，鰭結構20是置於基底10的上方而且是以相同於基底10的材料製成，並且是連續性地延伸自基底10。鰭結構20可以是本徵半導體，或亦可以是被適當地摻雜有n型不純物或p型不純物者。
在第1圖中，設置四個鰭結構20。這些鰭結構20是用來作為p型鰭式場效電晶體、n型鰭式場效電晶體或其組合。而鰭結構20的數量並不限於四，而可以是小至一個或是超過四個。此外，可設置一或多個虛設(dummy)鰭結構，使其鄰接鰭結構20以改善在圖形化製程中的圖形的保真度(fidelity)。在某些實施例中，鰭結構20的寬度W1是在約5nm~約40nm的範圍；在一些特定的實施例中，鰭結構20的寬度W1是在約7nm~約20nm的範圍。在某些實施例中，鰭結構20的高度H1是在約100nm~約300nm的範圍；在一些特定的實施例中，鰭結構20的高度H1是在約50nm~約100nm的範圍。當鰭結構的高度不平均時，從基底起算的高度可以從對應於鰭結構的平均高度的平面來測量。
如第2圖所示，在基底10的上方，形成用來形成一隔離絕緣層的一絕緣材料層50，而完全覆蓋鰭結構20。
用於絕緣材料層50的絕緣材料是由例如二氧化矽 構成者，此二氧化矽是藉由低壓化學氣相沈積、電漿化學氣相沈積或流動式化學氣相沈積(flowable chemical vapor deposition)而形成。在流動式化學氣相沈積中，是沈積流動式的介電材料而不是沈積氧化矽。沈積流動式的介電材料，顧名思義是在沈積的過程中可以「流動」以填滿具有高度的高/寬比的空隙或空間。通常，在含矽的前驅物添加各種化學物質，以促使已沈積的膜流動。在某些實施例中，是添加氮氫鍵。流動式介電質前驅物-特別是流動式氧化物前驅物，是包含矽酸鹽、矽氧烷、甲基倍半矽氧烷(methyl silsesquioxane；MSQ)、含氫倍半矽氧烷(hydrogen silsesquioxane；HSQ)、MSQ/HSQ(甲基矽酸鹽類與含氫矽酸鹽類的組合)、全氫矽氮烷(perhydrosilazane；TCPS)、全氫聚矽氮烷(perhydro-polysilazane；PSZ)、四乙氧基矽烷(tetraethyl orthosilicate；TEOS)或例如三甲矽烷胺(trisilylamine)等的甲矽烷胺(silyl-amine)。這些流動式氧化矽材料是在一多重作業製程(multiple-operation process)中形成。在沈積上述流動式薄膜之後，將其熟化(cure)然後施以退火以移除不需要的元素，以形成氧化矽。當移除上述不需要的元素時，上述流動式薄膜則緻密化且收縮。在某些實施例中，是導入多重退火製程(multiple anneal processes)，而不只一次地對上述流動式薄膜進行熟化及退火。絕緣材料層50可以是旋塗玻璃(SOG)、SiO、SiON、SiOCN或摻氟的二氧化矽(fluorine-doped silicate glass；FSG)。此外，絕緣材料層50可被摻雜有硼、磷或其組合。
在形成絕緣材料層50之後，執行一平坦化作業， 以移除絕緣材料層50的上部及包含墊氧化物層106與氮化矽罩幕層107的硬罩幕圖形100(罩幕層)。然後，進一步地移除絕緣材料層50，而曝露出鰭結構20之即將成為通道區的上部，如第3圖所示。
在形成絕緣材料層50之後，會視需求實施例如一退火製程的一加熱製程，以改善絕緣材料層50的品質。在一些特定的實施例中，是藉由使用在例如氮氣氛、氬氣氛或氦氣氛的非化學活性氣體的氣氛中且在約900℃~約1050℃的範圍的溫度歷時約1.5秒至約10秒的快速熱退火(rapid thermal annealing；RTA)，執行上述加熱製程。
在將鰭結構20的上部曝露於絕緣材料層50之外之後，在絕緣材料層50與曝露的鰭結構20的上方，形成一閘絕緣層105與一複晶矽層，然後施以圖形化作業以獲得由複晶矽構成的一閘層110，如第4A~4D圖所示。閘絕緣層105可以是藉由化學氣相沈積、物理氣相沈積、原子層沈積、電子束蒸鍍或其他適當的製程形成的氧化矽。在某些實施例中，上述複晶矽層的厚度是在約5nm~約100nm的範圍。在參考本實施例所敘述的閘取代技術中，閘絕緣層105與閘層110均為虛設層，而在最終會被移除。
在圖形化上述複晶矽層之後，亦在閘層110的雙側的側面形成側壁絕緣層80(側壁間隙壁)。側壁絕緣層80是由一或多層的氧化矽或例如SiN、SiCN、SiON或SiOCN的氮化矽類材料構成。在一實施例中，是使用氮化矽作為側壁絕緣層80。
在形成側壁絕緣層80之後，在閘層110與側壁絕緣 層80的上方形成一絕緣層，其即將被用來作為一接觸蝕刻停止層(contact-etch stop layer；CESL)。上述接觸蝕刻停止層是由一或多層的氧化矽或例如SiN、SiCN、SiON或SiOCN的氮化矽類材料構成。在一實施例中，是使用氮化矽作為上述接觸蝕刻停止層。
另外，在附帶側壁絕緣層80(與上述接觸蝕刻停止層，如果形成上述接觸蝕刻停止層的話)的閘層110之間的空間中、且在閘層110的上方，形成一層間介電層(interlayer dielectric layer；ILD)70。層間介電層70可包含氧化矽、氮化矽、氧氮化矽(SiON)、氧碳氮化矽(SiOCN)、摻氟的二氧化矽或一低介電常數介電材料，且可由化學氣相沈積或其他適當的製程製造。用於絕緣材料層50的絕緣材料可相同於或異於用於層間介電層70的絕緣材料。
施行一平坦化作業例如一回蝕製程、一化學機械研磨(chemical mechanical polishing；CMP)製程或其組合，以獲得示於第4A~4D圖的結構。第4A圖與第4B圖分別是形成閘層110與層間介電層70之後的鰭式場效電晶體的平面圖(俯視圖)與X方向、Y方向及Z方向的三維方向的透視圖。第1~3與4C圖是對應於沿著第4A圖中的線X1-X1的剖面視圖，而第4B圖是對應於第4A圖中的封閉的虛線圍起的部分B1。
如第4A與4B圖所示，閘層110是被形成為具有一固定間距而在一方向(X方向)延伸的線與面配置(line-and-space arrangement)。閘層110可包含在垂直於上述一方向的另一方向(Y方向)延伸的另一種線與面配置、以及具有不同尺寸的另一 種線與面配置。
閘層110覆蓋了使用鰭結構20形成的鰭式場效電晶體的通道區。換句話說，閘層110是形成於上述通道區的上方。未被閘層110覆蓋的鰭結構20將會藉由適當的源極/汲極製造作業，變成源極區/汲極區。
接下來，如第5A~5C圖所示，在用以曝露閘層110的上述平坦化操作之後，藉由使用乾蝕刻、溼蝕刻或其組合，移除閘層110與閘絕緣層105(皆可稱為虛置層)，藉此形成複數個閘線開口120，如第5A~5C圖所示。
接下來，如第6A~6D圖所示，在閘線開口120中，形成具有一閘介電層130與一金屬閘極層140的金屬閘結構。第6D圖是顯示第6B圖中的封閉的虛線圍起的部分B2的放大圖。
在一些特定的實施例中，閘介電層130包含一介面層132與一或多層的介電材料134，介面層132是由氧化矽構成，介電材料134是例如氧化矽、氮化矽、高介電常數介電材料、其他適當的介電材料或上述之任意組合。高介電常數材料的例子包含HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿一氧化鋁(HfO2-Al2O3)合金、其他適當的高介電常數介電材料或上述的任意組合。介面層132是藉由例如將鰭結構20的上述通道區熱氧化而形成。介電材料134是藉由化學氣相沈積或原子層氣相沈積，而形成於鰭結構20的上述通道區的上方與絕緣材料層50的上表面的上方。
在一些特定的實施例中，金屬閘極層140包含複數 個底層與一主要的金屬層148，上述底層具有一阻障層142、一功函數調整層144與一黏著或黏結層146。前述各層例如為以以下敘述順序堆疊：阻障層142、功函數調整層144、黏著或黏結層146與主要的金屬層148，如第6D圖所示。
在第6B圖中，雖然為了繪示上的方便將鰭結構20的上述通道區的上部繪示成具有一矩形(直角)的形狀，但是鰭結構20的上述通道區的頂部一般是具有弧形的形狀，如第6D圖所示。
阻障層142是由例如TiN、TaN、TiAlN、TaCN、TaC或TaSiN所構成。在一實施例中，是使用TaN作為阻障層142。
功函數調整層144是由一導體材料構成，上述導體材料例如為由單層的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC所構成或是由上述材料的二種或更多的多層結構所構成。在用於n通道場效電晶體的情況，是使用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi與TaSi中的一或多種作為功函數調整層144；在用於p通道場效電晶體的情況，是使用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC與Co中的一或多種作為功函數調整層144。功函數調整層144可藉由原子層氣相沈積、物理氣相沈積、化學氣相沈積、電子束蒸鍍或其他適當的製程來形成。另外，為了可能使用不同金屬層的n通道鰭式場效電晶體與p通道鰭式場效電晶體，可分離地形成功函數調整層144。
黏著或黏結層146是由例如TiN、TaN、TiAlN、TaCN、TaC或TaSiN所構成。在一實施例中，是使用TiN作為黏 著或黏結層146。
主要的金屬層148包含一或多層的任何適用的金屬材料，例如鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金其他適當的金屬或上述的任意組合。
在形成上述金屬閘結構的步驟中，可藉由適當的薄膜形成方法來形成閘介電層130與金屬閘極層140。例如化學氣相沈積或原子層氣相沈積是適用於閘介電層160，而化學氣相沈積、物理氣相沈積、原子層氣相沈積或電鍍是適用於各個金屬層。然後，施行例如化學機械研磨等的一平坦化作業。
在形成上述金屬閘結構之後，在第6A~6D圖的結果的結構的上方，形成一罩幕圖形150。第7A圖是對應於沿著第7C圖中的線X1-X1的剖面視圖，而第7B圖是對應於第4A圖中的區域B1的的區域的X方向、Y方向及Z方向的三維的透視圖，而第7C圖是一俯視圖。
罩幕圖形150是藉由例如對於形成上述金屬閘結構的金屬材料具有高蝕刻選擇比的一材料而形成。在一實施例中，罩幕圖形150是由氧化矽或氮化矽形成。罩幕圖形150具有一開口155。在某些實施例中，開口155之沿著X方向的寬度是在約5nm~約100nm的範圍；在其他實施例中，開口155之沿著X方向的寬度是在約10nm~約30nm的範圍。開口155之沿著Y方向的寬度W2是被調整而曝露出所需數量的閘結構。在第7C圖中，開口155之沿著Y方向的寬度W2是使二個閘結構被曝露於開口155中的長度，且開口155之沿著Y方向的邊緣是位於層 間介電層70上方的相鄰的閘結構之間。
如第8A~8C圖所示，藉由使用罩幕圖形150作為一蝕刻罩幕，移除一部分的金屬閘極層140與一部分的閘介電層130，以獲得將上述閘結構分離的一開口160。在某些實施例中，藉由電漿蝕刻，來施行上述金屬閘極層140的蝕刻。
如第8A圖所示，沿著Y方向，金屬閘極層140是曝露在開口160中；且如第8B圖所示，沿著X方向，是藉由閘介電層130而形成開口160。
在某些實施例中，如第8A~8C圖所示，是從開口160的底部完全移除閘介電層130。另外，亦可以將開口160內的閘介電層130完全移除，而使無任何介電層殘留於開口160中。在其他實施例中，閘介電層130是留在開口160的底部。
請注意開口160的剖面視圖具有一矩形的形狀，如第8B圖所示，但是在某些實施例中，開口160是具有上寬下窄的梯形的形狀。
然後，如第9A~9E圖所示，在開口160中形成一分離插塞170。第9A圖是一俯視圖，第9B圖是沿著第9A圖中的線X1-X1的剖面視圖，而第9C圖是沿著第9A圖中的線Y1-Y1的剖面視圖，而第9E圖是第9B圖的區域B3的一放大圖。
為了形成分離插塞170，藉由使用化學氣相沈積或原子層沈積，將一絕緣材料的一毯覆層填入開口160並將其形成於金屬閘極層140的上方且在層間介電層70的上方，然後施以例如一化學機械研磨製程等的一平坦化作業。在上述化學機械研磨製程中，施以上述化學機械研磨製程以曝露金屬閘極層 140的上表面，如第9A與9B圖所示。換句話說，金屬閘極層140是作為在上述化學機械研磨製程的終止層。藉由此平坦化作業，形成一分離插塞170。
分離插塞170例如是由氧化矽或例如SiN、SiCN、SiON或SiOCN的氮化矽類材料所構成。
在本實施例中，是在形成閘介電層130與金屬閘極層140之後，形成開口160與分離插塞170。因此，如第9E圖所示，主要的金屬層148是與分離插塞170的側壁接觸。另外，閘介電層130之沿著Y方向的最上部是位於鰭結構20的上方，而作為金屬閘極層140的底層的阻障層142、功函數調整層144及黏著或黏結層146之沿著Y方向的最上部亦是位於鰭結構20的上方。沿著X方向，金屬閘極層140與閘介電層130是具有相同的高度。
在前述的實施例中，是將上述金屬閘結構分離成二個金屬閘極層140，且每個金屬閘極層140具有閘介電層130，如第7A~8C圖所示。然而在其他實施例中，是藉由上述圖形化作業，將上述金屬閘結構分離成超過二個閘極層。在這樣的情況，如第10A圖所示，各自包含金屬閘極層140與閘介電層130的多重金屬閘結構是藉由分離插塞170對準並分離。
另外，在上述分離作業之前，上述金屬閘結構在其長度方向是具有兩端。在某些實施例中，分離插塞170是形成在上述兩端中的至少一端，如第10A圖的區域B3所示。在這樣的情況中，包含金屬閘極層140與閘介電層130的上述被分離的閘結構是被三明治狀地夾於二個分離插塞170之間。
在其他實施例中，分離插塞170並未形成在上述兩端中的至少一端，如第10A圖的區域B4所示。在這樣的情況中，包含金屬閘極層140與閘介電層130的上述閘結構的一端具有一分離插塞170，上述閘結構的另一端具有示於第10B圖的結構。第10B圖是沿著第10A的線B5的剖面視圖。如第10B圖所示，上述閘結構-特別是閘介電層130是與層間介電層70接觸；而金屬閘極層140-特別是主要的金屬層148則未與層間介電層70接觸。
若藉由分離上述虛設閘極並填充上述被分離的虛設閘極之間的一開口而先形成分離插塞、然後藉由將金屬閘材料填入藉由移除上述被分離的虛設閘極而形成的空間，則閘介電層及例如一阻障層、一功函數調整層與一黏著或黏結層等的底層金屬層會被形成在上述分離插塞的側表面上。在這樣的情況中，在如第9E圖所示的分離插塞與鰭結構之間的距離D1則不可設定得過小，因為較小的距離D1可能會使主要的金屬層148無法完全填滿分離插塞與鰭結構之間的空間。
相反地，在本實施例中，由於在上述分離插塞的側表面上並未形成有任何的閘介電層、亦未形成有任何的底層金屬層，即便距離D1變得較小，主要的金屬層148仍可完全填滿分離插塞170與鰭結構20之間的空間。因此，可以縮小半導體裝置的尺寸。
在另一實施例中，一閘絕緣層105並非一虛置層，而是由最終使用於場效電晶體裝置的介電材料構成。在這樣的情況中，可使用上述的高介電常數介電材料作為閘絕緣層 105。當閘絕緣層105並非一虛置層，則不會在形成金屬閘極層140之前沈積閘介電層130。
要瞭解的是第9A~9E圖所示的結構會歷經進一步的互補式金屬-氧化物-半導體(CMOS)製程，以形成各種構件，例如為互連結構的介層構件、互連結構的金屬層、鈍化層等等。
在以上的實施例中，是使用一鰭式場效電晶體。然而，上述技術上可應用於如第11A與11B圖所示的一平面式場效電晶體。如第11A與11B圖所示，此場效電晶體具有一半導體基底的複數個通道區25與複數個閘結構。每個上述閘結構具有一閘介電層130’與一金屬閘極層140’，閘介電層130’是形成於通道區25的上方，金屬閘極層140’是形成於閘介電層130’的上方。類似於閘介電層130，閘介電層130’包含一介面層132’與一或多層的介電材料134’。類似於金屬閘極層140，金屬閘極層140’具有以下敘述順序堆疊之一阻障層142’、一功函數調整層144’、一黏著或黏結層146’與一主要的金屬層148’。層間絕緣層70’是置於沿著X’方向延伸的金屬閘極層140’之間，藉由一絕緣材料層50’所形成的一隔離絕緣層將複數個通道區25分離，且藉由一分離插塞170’將二個閘結構分離。
在本說明書所敘述的各種實施例或範例，提供了許多優於現存技術的優點及技術功效。例如，由於在分離插塞的側表面未形成任何的閘介電層亦未形成任何的底層金屬層，在將被金屬閘材料填充的閘空間之在Y方向的寬度可以變大。在具有被擴大的閘開口之下，上述閘開口可以被例如為一 金屬閘極材料等的上述金屬閘材料所填滿，而不會形成空孔。因此，這使得上述分離插塞與上述鰭結構之間的距離變小，而可以縮減半導體裝置的尺寸。
要瞭解的是在本說明書中並未討論所有的優點或技術功效，並非所有的實施例或範例都提供某一特定的優點或技術功效，而每個個別的實施例或範例可提供不同的優點或技術功效。
根據本發明的一實施例，是提供一種半導體裝置，其包含：一第一鰭式場效電晶體與一第二鰭式場效電晶體。上述第一鰭式場效電晶體具有一第一鰭結構與一第一閘結構，上述第一鰭結構在一第一方向延伸，上述第一閘結構具有一第一閘介電層與一第一閘極層，上述第一閘介電層形成於上述第一鰭結構的上方，上述第一閘極層形成於該第一閘介電層的上方並在垂直於上述第一方向的一第二方向延伸。上述第二鰭式場效電晶體具有一第二鰭結構與一第二閘結構，上述第二鰭結構在上述第一方向延伸，上述第二閘結構具有一第二閘介電層與一第二閘極層，上述第二閘介電層形成於上述第二鰭結構的上方，上述第二閘極層形成於上述第二閘介電層的上方並在垂直於上述第二方向延伸。上述第一閘結構與上述第二閘結構是沿著上述第二方向對準，上述第一閘結構與上述第二閘結構是藉由一絕緣材料製的一分離插塞而分離。上述第一閘極層是與上述分離插塞的一側壁接觸。
根據本發明的另一實施形態，是提供一種半導體裝置，其包含：一第一鰭式場效電晶體與一第二鰭式場效電晶 體。上述第一鰭式場效電晶體具有一半導體基底的一第一通道區與一第一閘結構，上述第一閘結構具有一第一閘介電層與一第一閘極層，上述第一閘介電層是形成於上述第一通道區的上方，上述第一閘極層是形成於上述第一閘介電層的上方並在一第一方向延伸。上述第二鰭式場效電晶體具有上述半導體基底的一第二通道區與一第二閘結構，上述第二閘結構具有一第二閘介電層與一第二閘極層，上述第二閘介電層是形成於上述第二通道區的上方，上述第二閘極層是形成於上述第二閘介電層的上方並沿著上述第一方向延伸。上述第一閘結構與上述第二閘結構是沿著上述第一方向對準；上述第一閘結構與上述第二閘結構是藉由一絕緣材料製的一分離插塞而分離。上述第一閘極層是與上述分離插塞的一側壁接觸。
根據本發明的又另一實施形態，是提供一種半導體裝置的製造方法，包含在形成於一基底的上方的複數個通道區的上方，形成一虛設閘結構，上述虛設閘結構具有一虛設閘極層、一虛設閘介電層與置於上述虛設閘介電層的二側的側壁間隔層。此方法還包含在上述虛設閘結構的二側形成層間介電層。此方法還包含在形成上述層間介電層之後，移除上述虛設閘極層，而形成一電極空間。此方法還包含在上述電極空間中形成一閘結構，上述閘結構具有一閘極層。此方法還包含圖形化上述閘結構，而將上述閘結構分離成至少二個分離的閘結構，其具有被一分離開口分離的一第一閘結構與一第二閘結構。此方法還包含藉由以一絕緣材料填入上述分離開口，形成一分離插塞。其中在上述第一閘結構內的上述閘極層是與上述 分離插塞的一側壁接觸。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
20‧‧‧‧‧‧鰭結構
50‧‧‧絕緣材料層
130‧‧‧閘介電層
132‧‧‧介面層
134‧‧‧介電材料
140‧‧‧金屬閘極層
142‧‧‧阻障層
144‧‧‧功函數調整層
146‧‧‧黏著或黏結層
148‧‧‧主要的金屬層
170‧‧‧分離插塞
D1‧‧‧距離

Claims (10)

  1. 一種半導體裝置，包含：一第一鰭式場效電晶體(fin field-effect transistor；Fin FET)，具有一第一鰭結構與一第一閘結構，該第一鰭結構在一第一方向延伸，該第一閘結構具有一第一閘介電層與一第一閘極層，該第一閘介電層形成於該第一鰭結構的上方，該第一閘極層形成於該第一閘介電層的上方並在垂直於該第一方向的一第二方向延伸；以及一第二鰭式場效電晶體，具有一第二鰭結構與一第二閘結構，該第二鰭結構在該第一方向延伸，該第二閘結構具有一第二閘介電層與一第二閘極層，該第二閘介電層形成於該第二鰭結構的上方，該第二閘極層形成於該第二閘介電層的上方並在垂直於該第二方向延伸；其中，該第一閘結構與該第二閘結構是沿著該第二方向對準；該第一閘結構與該第二閘結構是藉由一絕緣材料製的一分離插塞而分離；以及該第一閘極層是與該分離插塞的一側壁接觸。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一閘極層包含複數個第一底層與一第一主要金屬閘極層，該些第一底層與該第一主要金屬閘極層是形成在該第一鰭結構的上方；以及該第一主要金屬閘極層是與該分離插塞的該側壁接觸。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該第二閘極 層包含一第二底層與一第二主要金屬閘極層，該第二底層與該第二主要金屬閘極層是形成在該第二鰭結構的上方；以及該第二主要金屬閘極層是與該分離插塞的該側壁接觸。
  4. 一種半導體裝置，包含：一第一鰭式場效電晶體，具有一半導體基底的一第一通道區與一第一閘結構，該第一閘結構具有一第一閘介電層與一第一閘極層，該第一閘介電層是形成於該第一通道區的上方，該第一閘極層是形成於該第一閘介電層的上方並在一第一方向延伸；以及一第二鰭式場效電晶體，具有該半導體基底的一第二通道區與一第二閘結構，該第二閘結構具有一第二閘介電層與一第二閘極層，該第二閘介電層是形成於該第二通道區的上方，該第二閘極層是形成於該第二閘介電層的上方並沿著該第一方向延伸；其中，該第一閘結構與該第二閘結構是沿著該第一方向對準；該第一閘結構與該第二閘結構是藉由一絕緣材料製的一分離插塞而分離；以及該第一閘極層是與該分離插塞的一側壁接觸。
  5. 如申請專利範圍第4項所述之半導體裝置，其中該第一閘極層包含複數個第一底層與一第一主要金屬閘極層，該些第一底層與該第一主要金屬閘極層是形成在該第一鰭結構的上方；以及 該第一主要金屬閘極層是與該分離插塞的該側壁接觸。
  6. 一種半導體裝置的製造方法，包含：在形成於一基底的上方的複數個通道區的上方，形成一虛設閘結構，該虛設閘結構具有一虛設閘極層、一虛設閘介電層與置於該虛設閘介電層的二側的側壁間隔層；在該虛設閘結構的二側形成層間介電層；在形成該些層間介電層之後，移除該虛設閘極層，而形成一電極空間；在該電極空間中形成一閘結構，該閘結構具有一閘極層；圖形化該閘結構，而將該閘結構分離成至少二個分離的閘結構，其具有被一分離開口分離的一第一閘結構與一第二閘結構；以及藉由以一絕緣材料填入該分離開口，形成一分離插塞；其中，在該第一閘結構內的該閘極層是與該分離插塞的一側壁接觸。
  7. 如申請專利範圍第6項所述之半導體裝置的製造方法，其中在形成該分離開口之後，該閘極層是被曝露於該分離開口中。
  8. 如申請專利範圍第6項所述之半導體裝置的製造方法，其中該閘結構的圖形化包含：在該閘結構與該層間介電層的上方形成一罩幕層；圖形化該罩幕層以形成一開口圖形；以及蝕刻該閘結構之在該開口圖形下的部分，以形成該分離開口。
  9. 如申請專利範圍第6項所述之半導體裝置的製造方法，其中該閘極層包含複數個底層與一主要金屬閘極層，該些底層與該主要金屬閘極層是形成在該些通道區的上方；以及該主要金屬閘極層是與該分離插塞的該側壁接觸。
  10. 如申請專利範圍第6項所述之半導體裝置的製造方法，其中該虛設閘結構還具有一虛設閘介電層與置於該虛設閘介電層的二側的側壁間隔層；該電極空間是藉由移除該虛設閘極層與該虛設閘介電層而形成；以及在該電極空間中形成該閘結構的步驟中，該閘結構是包含一閘介電層。
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