TW201730918A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201730918A
TW201730918A TW105124581A TW105124581A TW201730918A TW 201730918 A TW201730918 A TW 201730918A TW 105124581 A TW105124581 A TW 105124581A TW 105124581 A TW105124581 A TW 105124581A TW 201730918 A TW201730918 A TW 201730918A
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layer
semiconductor
fin structure
semiconductor layer
fin
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TW105124581A
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TWI611459B (zh
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王聖禎
李凱璿
世海 楊
游佳達
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台灣積體電路製造股份有限公司
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Abstract

在一種半導體的製造方法中，形成第一及第二半導體層的疊層。藉由圖案化第一及第二半導體層形成鰭結構。形成覆蓋層於鰭結構的底部部分上以覆蓋鰭結構的底部側壁及鰭結構的上部側壁之底部部分。形成絕緣層於具有覆蓋層的鰭結構上方，使得鰭結構嵌入絕緣層中。移除鰭結構之上部的一部分，從而形成開口於絕緣層之中。在開口中形成第三半導體層於第二半導體層之殘留層上。凹蝕絕緣層使得第三半導體層的一部分從絕緣層中暴露，並形成閘極結構。

Description

半導體裝置及其製造方法
本揭露係關於半導體積體電路，特別係具有鰭結構的半導體裝置及其製造製程。
隨著半導體產業已進展到奈米技術製程節點以追求更高的裝置密度、更高的性能及更低的成本，來自製造及設計問題所帶來的挑戰促成了諸如鰭式場效電晶體(FinFET)的三維設計之開發。FinFET裝置一般包括具有高高寬比的半導體鰭，並在其中形成半導體電晶體裝置的通道及源極/汲極區。沿著鰭結構的側壁並在其上方形成閘極，利用通道及源極/汲極區之間增加的表面區域，以產生更快、更可靠且更好控制的半導體電晶體裝置。在一些裝置中，可使用鍺或矽鍺(SiGe)作為通道區以提高載子移動率。
根據本揭露之一面向，在一種半導體的製造方法中，形成第一半導體層於基板上。形成第二半導體層於第一半導體層上。藉由圖案化第一及第二半導體層形成鰭結構。鰭結構包括由第一半導體層所構成的底部及由第二半導體層所構成的上部。形成覆蓋層於鰭結構的底部部分上以覆蓋鰭結構的 底部側壁及鰭結構的上部側壁之底部部分。形成絕緣層於具有覆蓋層的鰭結構上方，使得鰭結構嵌入絕緣層中。移除鰭結構上部的一部分，從而形成開口於絕緣層之中，且第二半導體層的一層殘留在開口的底部中。在開口中形成第三半導體層於第二半導體層之殘留層上。凹蝕絕緣層使得第三半導體層的至少一部分從絕緣層中暴露。形成閘極結構於暴露的第三半導體層上方。
根據本揭露之另一面向，在一種半導體的製造方法中，形成第一半導體層於基板上。形成第二半導體層於第一半導體層上。藉由圖案化第一及第二半導體層形成第一鰭結構及一第二鰭結構，第一及第二鰭結構分別包括由第一半導體層所構成的底部及由第二半導體層所構成的上部；形成覆蓋層於第一及第二鰭結構的底部部分上以覆蓋第一及第二鰭結構的底部側壁及第一及第二鰭結構的上部側壁之底部部分。形成絕緣層於具有覆蓋層的第一及第二鰭結構上方，使得第一及第二鰭結構嵌入絕緣層中。移除第一鰭結構上部的一部分，從而形成開口於絕緣層之中，且第二半導體層的一層殘留在開口的底部中，同時保護第二鰭結構之上部免於被蝕刻。在開口中形成第三半導體層於第二半導體層之殘留層上。凹蝕絕緣層使得第三半導體層的至少一部分及第二鰭結構之上部的一部分從絕緣層中暴露。形成第一閘極結構於暴露的第三半導體層上方，並形成第二閘極結構於第二鰭結構之暴露的部分上方。
根據本揭露之另一面向，一種半導體裝置包括第一FinFET裝置。第一FinFET裝置包括第一鰭結構，以第一方向 延伸並從隔離絕緣層中突出。設置於基底上方的第一鰭結構及隔離絕緣層。第一鰭結構包括由第一半導體材料所構成的第一層、設置於第一層上方並由第二半導體材料所構成的第二層及設置於第二層上方並由第三半導體材料所構成的第三層。第一FinFET更包括第一覆蓋層，其設置於第一鰭結構之底部部分上，以覆蓋第一鰭結構的底部側壁及第一鰭結構的上部側壁之底部部分。第一FinFET更包括具有閘電極層及閘介電層的第一閘極堆疊，覆蓋第一鰭結構的一部分並以垂直於第一方向的第二方向延伸。第三層作為該第一FinFET的通道區。第一半導體層包括Si(1-x)Gex，第二半導體層包括Si(1-y)Gey，及第三半導體層包括Ge或Si(1-z)Gez，其中y小於x且z大於y。
10‧‧‧鰭結構
20‧‧‧鰭結構
100‧‧‧基底
110‧‧‧第一半導體層
110A‧‧‧鰭結構
110B(10’、20’)‧‧‧鰭結構
120‧‧‧第二半導體層
120’‧‧‧第五半導體層
120A‧‧‧通道區
125‧‧‧第二半導體層
125’‧‧‧第四半導體層
130‧‧‧罩幕層第一層
140‧‧‧罩幕層第二層
150‧‧‧罩幕圖案
160‧‧‧保護層
170‧‧‧犧牲層
180‧‧‧隔離絕緣層
190‧‧‧開口
190’‧‧‧開口
200‧‧‧保護硬罩幕層
210‧‧‧第三半導體層
210A‧‧‧通道區
220‧‧‧閘介電層
230‧‧‧閘電極層
240‧‧‧源極/汲極
245‧‧‧空乏區
H1‧‧‧高度
H2‧‧‧厚度
H3‧‧‧厚度
H4‧‧‧高度
D1‧‧‧深度
D2‧‧‧厚度
D3‧‧‧厚度
D4‧‧‧高度
以下將配合所附圖式詳述本揭露之實施例。應注意的是，依照工業上的標準實施，各種圖示並未按照比例繪製且僅用於說明之目的。事實上，可能任意的放大或縮小元件的尺寸以便清楚表現出本揭露的特徵。
第1-12圖係在本揭露一實施例中，製造半導體FET裝置的連續製程之例示性剖面圖。
第13圖係相應於第12圖之例示性透視圖。
第14A及14B圖係源極/汲極結構之例示性剖面圖。
第15及16圖係在本揭露修飾的實施例中，用於製造半導體FET裝置的連續製程之剖面圖。
第17-24圖係在本揭露另一實施例中，用於製造半導體FET裝置的連續製程之例示性剖面圖。
應當理解以下提供許多不同的實施方法或是實例來實行各種實施例之不同特徵。以下描述具體的元件及其排列的例子以闡述本揭露。當然這些僅是例子且不該以此限定本揭露的範圍。例如，元件的尺寸並非限制於本揭露之範圍或數值，而可取決於製程條件及/或裝置期望的特性。此外，在描述中提及第一個元件形成於第二個元件上時，其可以包括第一個元件與第二個元件直接接觸的實施例，也可以包括有其他元件形成於第一個與第二個元件之間的實施例，其中第一個元件與第二個元件並未直接接觸。為了簡化並明確化，可任意地以不同比例繪製各種特徵。
此外，其中可能用到與空間相關的用詞，像是“在…下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些關係詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖示中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。此外，用詞”由...所組成”可代表”包括”或”包含”。
第1-10圖係在本揭露一實施例中，製造半導體FET裝置的連續製程之例示性剖面圖。應當理解，可於第1-10圖所示之操作進行前、進行中及/或進行後提供額外的操作，且在另外的實施例中，以下所述的一些操作可被取代或刪除，且操作的順序可以交換。
在第1圖中，提供基底100並形成第一半導體層110於基底100上方。再者，形成第二半導體層120於第一半導體層上方。
基底100之實例為具有雜質濃度約1x1015cm-3至1x1016cm-3的p型矽基底。在其它實施例中，基底100為具有雜質濃度約1x1015cm-3至1x1016cm-3的n型矽基底。或者，基底100可另包括元素半導體，諸如鍺；化合物半導體，包括諸如SiC及SiGe的IV-IV化合物半導體，諸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的III-V化合物半導體；或上述之組合。在一實施例中，基底100為絕緣體上半導體(semiconductor-on-insulator,SOI)基底之矽層。當使用SOI基底時，鰭結構可從SOI基底之矽層中突出或可從SOI基底之絕緣層中突出。在後者的情況下，使用SOI基底之矽層來形成鰭結構。基底100可包括已被雜質(例如p型或n型傳導性)適當摻雜的各種區域。摻雜劑之實例為硼(BF2)、磷及/或砷。在此實施例中，基底為矽基底(晶圓)。
如第1圖所示，第一半導體層110磊晶生長於基底100之表面上方，且第二半導體層120磊晶生長於第一半導體層110上方。再者，形成包含第一層130及第二層140的罩幕層於第二半導體層120上方。
第一半導體層110的實例為Si(1-x)Gex，其中x為約0.1至0.5。在一些實施例中，Si(1-x)Gex之x可為約0.2至0.4。在本揭露中，Si(1-x)Gex可簡稱為SiGe。在一些實施例中，SiGe第一半導體層110的厚度為約0.5μm至2μm。藉由生長相對較厚的 SiGe層110於矽基底100上方，可減少並緩和SiGe層110中所引起的應力。在一些實施例中，SiGe第一半導體層110的厚度為約1μm至1.5μm。在特定的實施例中，可使用Ge層或Si(1-x)Gex作為第一半導體層110，其中x小於約0.1。在其它實施例中，可使用諸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的III-V化合物半導體作為第一半導體層110。
第一半導體層110可被摻雜或不摻雜。可於第一半導體層110的磊晶生長期間實行摻雜或可藉由離子植入來實行摻雜。
第二半導體層120的實例為Si或Si(1-y)Gey，其中y小於約0.1。在此實施例中，第二半導體層120為磊晶生長的矽。在一些實施例中，第二半導體層120具有約30nm至200nm的厚度。在特定的實施例中，第二半導體層120的厚度為約50nm至150nm。
在一些實施例中，罩幕層之實例可包括墊氧化物(例如氧化矽)層130及氮化矽罩幕層140。在一些實施例中，墊氧化物層的厚度為約2nm至15nm及氮化矽罩幕層的厚度為約10nm至50nm。
如第2圖所示，將第一及第二半導體層的堆疊層圖案化成鰭結構。
藉由使用包括微影及蝕刻的圖案化操作，將罩幕層圖案化成罩幕圖案150。在一些實施例中，各個圖案150的寬度為約5nm至40nm，或在其它的實施例中可為約10nm至 30nm。藉由使用罩幕圖案150作為蝕刻罩幕，並透過使用乾蝕刻方法及/或濕蝕刻方法的溝槽蝕刻，將第一及第二半導體層圖案化成鰭結構10及20。如第2圖所示，實行溝槽蝕刻使其穿過第二半導體層120並至第一半導體層110中間。鰭結構110A的底部係由第一半導體層所組成，且鰭結構120的上部係由第二半導體層所組成。
在此實施例中，鰭結構10係用於p型FinFET及鰭結構20係用於n型FinFET。雖然在第2圖中係將鰭結構10及20設置為彼此相鄰，但亦可將用於p型FinFET的鰭結構10設置為遠離用於n型FinFET的鰭結構20。再者，鰭結構的數量不限於一個(或兩個)，其數量可為兩個或更多。此外，可設置一或更多虛設鰭結構相鄰於鰭結構10及/或鰭結構20的兩側，以增進圖案化製程的圖案保真度。鰭結構10及20以Y方向延伸，並以與Y方向交叉的X方向排列。
在一些實施例中，鰭結構10及20的寬度為約5nm至40nm，且在特定的實施例中可為約7nm至15nm。在一些實施例中，鰭結構10及20的高度H1為約50nm至300nm，且在其它實施例中可為約100nm至200nm。在一些實施例中，相鄰於鰭結構之間的間隔為約5nm至80nm，且在其它實施例中可為約7nm至15nm。第一半導體層110殘留的厚度H2為約500μm至800μm。當鰭結構的高度不均勻時，可從相應於鰭結構底部的平均高度之平面測量鰭結構從底部的高度H1。同樣地，可從基底100的上表面至平面測量H2。
再者，雖然在第2圖中，鰭結構10及20具有大致垂 直的側壁，但在一些實施例中，鰭結構10及20可具有頂寬小於底寬的錐形。若鰭結構10及20從頂部至底部的寬度不均勻，可將寬度定義為平均寬度，即於垂直中點處的寬度或於第一及第二半導體層之間介面處的寬度。然而，本領域之技藝人士應當理解，全文所述之尺寸及數值僅為舉例說明，其可改變以符合不同尺寸的積體電路。
如第3圖所示，在形成鰭結構之後，形成保護(覆蓋)層160以覆蓋鰭結構10及20。保護層160由可防止底層(第一半導體層)免於氧化的材料所組成。在一些實施例中，保護層160由一或多層的氮化矽(SiN)、SiC、SiN及SiCN所形成。在一些實施例中，保護層160的厚度為約1nm至10nm。在特定的實例中，保護層160的厚度為約2nm至5nm。在此實施例中，使用SiN作為保護層160。
保護層160係藉由化學氣相沉積(CVD)、電漿輔助化學氣相沈積(PECVD)、常壓化學氣相沈積(APCVD)、低壓CVD(LPCVD)、高密度電漿CVD(HDPCVD)、原子層沉積(ALD)及/或其它合適的製程所形成。
在膜形成製程期間，基底溫度為約300℃至500℃。在一些實施例中，基底溫度可為約350℃至450℃。在膜形成製程期間，藉由維持基底溫度相對低於一般CVD製程的溫度，則可能抑制第一半導體層的鍺擴散至第二半導體層中。在一些實施例中，使用PECVD。
如第4圖所示，在形成保護層160之後，形成犧牲層170使得鰭結構10及20嵌入犧牲層170之中。鰭結構10及20可 完全或部分嵌入犧牲層170之中。在一些實施例中，犧牲層170由諸如光阻層的有機材料或用於底部抗反射塗佈(BRAC)的材料所組成。
接著，如第5圖所示，藉由諸如回蝕製程來減少犧牲層170的厚度以暴露部分鰭結構。在特定的實施例中，可藉由使用包括O2及至少CF4及CHF3之一的電漿，並於約0℃至300℃的溫度及於約1至10托耳(torr)的壓力下實行回蝕製程。藉由調整蝕刻時間，可得到殘留犧牲層所期望的厚度。在本揭露中，藉由D1之大小調整厚度H3使其大於第一半導體層110A與第二半導體層120之間介面的高度。在一些實施例中，距離D1為約5nm至60nm，或在其它實施例中可為約20nm至50nm。
另外，亦可藉由直接調整例如膜的形成條件而非回蝕厚犧牲層，以形成具有目標厚度的薄犧牲層。
接著，如第6圖所示，藉由諸如乾蝕刻及/或濕蝕刻移除從犧牲層170中暴露的保護層160之上部。在特定的實施例中，硬罩幕圖案150也可於此製程中移除。藉由例如灰化製程及/或濕清洗製程移除殘留的犧牲層170。
接著，如第7圖所示，形成隔離絕緣層180。隔離絕緣層180由一或多層諸如二氧化矽、SiO、SiON、SiN、氟摻雜矽酸鹽玻璃(FSG)或任何其它合適的介電材料所組成。當隔離絕緣層180由氧化矽所組成時，氧化矽可摻雜諸如硼及/或磷。
在本揭露一些實施例中，可藉由可流動的CVD(flowable CVD,FCVD)形成隔離絕緣層180。在FCVD中， 沉積可流動的介電材料而非氧化矽。可流動介電材料，如其名稱所示，可於沉積期間”流動”以填滿具有高深寬比的間隙或間隔。通常，加入各種化學物質至含矽前驅物以允許沉積膜流動。在一些實施例中，加入氮氫鍵(nitrogen hydride bonds)。可流動的介電前驅物之範例，特別是可流動的氧化矽前驅物，包括矽酸鹽、矽氧烷、甲基倍半矽氧烷(methylsilsesquioxane,MSQ)、氫倍半矽氧烷(hydrogen silsesquioxane,HSQ)、MSQ/HSQ、全氫矽氮烷(perhydrosilazane,TCPS)、全氫聚矽氮烷(perhydro-polysilazane,PSZ)、四乙基正矽酸鹽(TEOS)或諸如三甲矽烷基胺(TSA)的矽烷基胺。這些可流動的氧化矽材料於多重操作製程中形成。
在沉積可流動膜之後，將其固化並退火以移除不期望的成分而形成氧化矽。當移除不期望的成分時，該可流動膜收縮並緻密化。在一些實施例中，執行多重退火製程。將可流動膜固化並退火一次以上。
在本實施例中，也可將退火溫度調整至相對較低的溫度，例如約500℃至800℃。藉由利用低溫CVD，則可能抑制第一半導體層110(110A)與第二半導體層120之間的Ge擴散。
由於鰭結構10及20的底部110A之側壁被保護層160所覆蓋，因此在用以形成隔離絕緣層180的熱製程期間，鰭結構10及20的底部110A不會被氧化。
如第8圖所示，藉由例如化學機械研磨(CMP)方法或其它諸如回蝕製程的平坦化方法來移除隔離絕緣層180的上部及罩幕圖案150。可稍微蝕刻鰭結構之上層120的頂部。
接著，如第9圖所示，形成諸如氮化矽之單層(在一些實施例約10nm至50nm)或氮化矽(在一些實施例約5nm至50nm)及氧化矽(在一些實施例約10nm至50nm)之雙層的保護硬罩幕層200於隔離絕緣層180上方，該隔離絕緣層180位在用於n型FinFET區的鰭結構20上方。保護硬罩幕層200係保護鰭結構20免於被隨後實行於用在p型FinFET的鰭結構10上之製程破壞。
藉由乾蝕刻及/或濕蝕刻部分移除由鰭結構10之第二半導體層120所組成的上部，從而形成開口190及殘留的第二半導體層125。可藉由乾蝕刻及/或濕蝕刻實行第二半導體層120之蝕刻。
在一些實施例中，殘留的第二半導體層125之厚度D2為約5nm至50nm，或在其它實施例中可為5nm至25nm。藉由調整蝕刻時間及/或條件，可得到殘留的第二半導體層125所期望厚度。在一些實施例中，保護層160上端與殘留的第二半導體層125上表面之間的距離D3為約5nm至20nm，或在其它實施例中可為約5nm至10nm。
接著，如第10圖所示，將第三半導體層210磊晶生長於殘留的第二半導體層125之上表面以填滿開口190。第三半導體層可為Ge或Si(1-z)Gez，其中z大於第一半導體層110(Si(1-x)Gex)之x。在一些實施例中，z等於或大於約0.5，且在其它實施例中可為約0.5至0.75。如第10圖所示，第三半導體層210也可形成於隔離絕緣層180之上表面上方。
在形成第三半導體層210之後，藉由諸如CMP的平 坦化操作移除形成於隔離絕緣層180之上表面上方的保護硬罩幕層200及部分第三半導體層210。
接著，如第11圖所示，藉由諸如回蝕製程移除(凹蝕)隔離絕緣層180之上部，使得第二半導體層120之上部及第三半導體層210之上部從隔離絕緣層180中暴露。將隔離絕緣層180凹蝕至一程度，使隔離絕緣層180之上表面與保護層160之上端具有大致相同的高度。可藉由使用乾蝕刻或濕蝕刻實行回蝕製程。藉由調整蝕刻時間，可得到殘留的隔離絕緣層180所期望的厚度。在一些實施例中，隔離絕緣層180之上表面可位於保護層160上端之下方，或位於保護層160上端之上方。
暴露的第二半導體層120之上部成為用於n型FinFET的通道區120A，且暴露的第三半導體層210之上部成為用於p型FinFET的通道區210A。在一些實施例中，暴露的上部之高度D4為約20nm至80nm，且在其它實施例中可為約30nm至60nm。
在第11圖中，殘留的第二半導體層125並未從隔離絕緣層180中暴露，且通道區的底部嵌入隔離絕緣層180之中。
接著，如第12圖所示，形成閘極結構於部分的通道區120A及210A上方。形成閘介電材料及閘電極材料於隔離絕緣層180及通道區120A及210A上方，接著實行圖案化操作以得到包括閘電極層230及閘介電層220的閘極結構。閘電極層230由一或更多導電材料所形成，例如多晶矽、Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、其它導電材料。可使用諸如ALD、CVD、PVD、電鍍或其組合來形成用於 閘電極層230的電極層。
閘介電層220包括一或多層的氧化矽、氮化矽、氮氧化矽或高介電常數(high-k)介電質。高介電常數介電質可包括金屬氧化物。用於高介電常數介電質的金屬氧化物之實例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu及/或其混合之氧化物。高介電常數介電質材料之實例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其它合適的高介電常數介電質材料及/或其組合。可使用合適的操作形成閘介電層220，例如原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、熱氧化、UV-臭氧氧化或其組合。閘介電層220可進一步包括界面層(未繪示)以減少閘介電層220與通道區之間的損壞。界面層可包括氧化矽。
在一些實施例中，可插入一或更多功函數調整層(未繪示)於閘介電層220與閘電極層230之間。功函數調整層可包括單層或可選的多層結構，例如具有所選功函數的金屬層之各種組合以增進裝置效能(功函數金屬層)、襯層、潤濕層、黏著層、金屬合金或金屬矽化物。對於n通道FinFET，可使用一或多層的TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi作為功函數調整層；對於p通道FinFET，可使用一或多層的TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co作為功函數調整層。在一些實施例中，功函數調整層可選地包括多晶矽層。可藉由ALD、PVD、CVD、電子束蒸鍍或其它合適操作來 形成功函數調整層。再者，可分別對n通道FinFET及p通道FinFET形成功函數調整層，其可使用不同的金屬層。
在第12圖中，對n通道FinFET及p通道FinFET設置一閘極結構，可分別對n通道FinFET及p通道FinFET設置該閘極結構。
第13圖係相應於第12圖的例示性透視圖，繪示出第12圖其中之一的FinFET。
在形成閘極結構之後，形成源極及汲極240。在一些實施例中，可藉由形成矽化物層於未被閘極結構覆蓋的鰭結構之上部以形成源極及汲極240。在其它實施例中，將未被閘極結構覆蓋的鰭結構之上部凹蝕至隔離絕緣層180之上表面下方，並重新生長應變材料於凹陷的鰭結構上方。應變材料可包括一或多層的Si、SiC、SiCP、SiP、SiCP、SiGe或Ge。
第14A及14B圖係源極/汲極結構的例示性剖面圖。在本案實施例中，設置殘留的第二半導體層125(由例如Si所製成)於第一半導體層110與p型FinFET中的通道區210A之間。如第14A圖所示，利用此結構，即使位於源極/汲極240下方的空乏區245擴大，也不會有從源極/汲極至第一半導體層110及/或源極與汲極之間的電流洩漏路徑。相反地，如第14B圖所示，若沒有該殘留的第二半導體層125於第一半導體層110與通道區210A之間，則會有從源極/汲極至第一半導體層110及/或源極與汲極之間的電流洩漏路徑。
再者，藉由插入設置於第一半導體層110(由例如Si(1-x)Gex所形成，其中x為約0.1至0.5)與通道區210A(由例如Ge 或Si(1-z)Gez所製成，其中z大於第一半導體層110(Si(1-x)Gex)之x)之間的殘留之第二半導體層125(由例如Si所製成)，則可能抑制第一半導體層110與通道區210A之間的Ge擴散。此外，藉由降低用於隔離絕緣層180的退火溫度，可進一步抑制Ge擴散。
在一些實施例中，於形成第三半導體層210之後的熱操作期間，第一及/或第三半導體層中的Ge可擴散至殘留的第二半導體層125之中。因此，殘留的第二半導體層125可包含約10原子百分比或更少量的Ge。在其它實施例中，殘留的第二半導體層125中Ge的量可為小於約5原子百分比。
應當理解，FinFET裝置可經歷進一步的CMOS製程以形成各種特徵，例如接觸件/介層窗、互連金屬層、介電層、保護層等。
第15及16圖係在本揭露修飾的實施例中，用於製造半導體FET裝置的連續製程之剖面圖。
在上述實施例第9圖中，部分蝕刻用於p型FinFET的第二半導體層120，且第二半導體層120的底部部分殘留在開口190之中。可藉由乾蝕刻及/或濕蝕刻實行第二半導體層120之蝕刻。
在修飾的實施例中，如第15圖所示，用於p型FinFET的第二半導體層120大致被完全蝕刻，以暴露第一半導體層110A之上表面。接著，如第16圖所示，形成具有期望的厚度D2之第四半導體層125’於開口190中暴露的第一半導體層110A之上表面上方。第四半導體層125’由例如Si或Si(1-y)Gey所形成，其中y小於約0.1。在此修飾的實施例中，第四半導體層 的材料可獨立地選自n型FinFET中用於通道區120A(第二半導體層)的材料。再者，相較於部分蝕刻第二半導體層，可藉由對第四半導體層125’使用相對較慢的磊晶生長以更準確地控制厚度D2。此外，可能藉由改變來源氣體以連續性地形成第三半導體層210於第四半導體層125’上方。
第17-24圖係在本揭露另一實施例中，用於製造半導體FET裝置的連續製程之例示性剖面圖。應當理解，可於第17-24圖所示之操作進行前、進行中及/或進行後提供額外的操作，且在另外的實施例中，以下所述的一些操作可被取代或刪除，且操作的順序可以交換。再者，此實施例的一些特徵、材料、結構、製程及/或操作大致相同或相似於第1-16圖之前述實施例，且其詳細解釋可在此省略。
如第17圖所示，磊晶生長第一半導體層110於基底100之表面上方。再者，形成包含第一層130及第二層140的罩幕層於第二半導體層120上方。
第一半導體層110的實例為Si(1-x)Gex，其中x為約0.1至0.5。在一些實施例中，Si(1-x)Gex之x可為約0.2至0.4。在一些實施例中，SiGe第一半導體層110的厚度為約0.5μm至2μm。藉由生長相對較厚的SiGe層110於矽基底100上方，可減少並緩和SiGe層110中所引起的應力。在一些實施例中，SiGe第一半導體層110的厚度為約1μm至1.5μm。在特定的實施例中，可使用Ge層或Si(1-x)Gex作為第一半導體層110，其中x小於約0.1。在其它實施例中，可使用諸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP 及/或GaInAsP的III-V化合物半導體作為第一半導體層110。
第一半導體層110可被摻雜或不摻雜。可於第一半導體層110的磊晶生長期間實行摻雜或可藉由離子植入來實行摻雜。
在一些實施例中，罩幕層可包括例如墊氧化物(例如氧化矽)層130及氮化矽(SiN)罩幕層140。在一些實施例中，墊氧化物層的厚度為約2nm至15nm，且氮化矽罩幕層的厚度為約10nm至50nm。
如第18圖所示，將第一半導體層110圖案化成鰭結構。相似於第2圖，藉由使用罩幕圖案150作為蝕刻罩幕，並透過使用乾蝕刻方法及/或濕蝕刻方法的溝槽蝕刻，將第一半導體層110圖案化成鰭結構110B(10’及20’)。如第18圖所示，實行溝槽蝕刻使其穿透至第一半導體層110的中間。鰭結構10’係用於p型FinFET，鰭結構20’係用於n型FinFET。
在一些實施例中，鰭結構110B的寬度為約5nm至40nm，且在特定的實施例中可為約7nm至15nm。在一些實施例中，鰭結構110B的高度H1為約50nm至300nm，且在其它實施例中可為約100nm至200nm。在一些實施例中，相鄰於鰭結構之間的間隔為約5nm至80nm，且在其它實施例中可為約7nm至15nm。第一半導體層110殘留的厚度H2為約500μm至800μm。
如第19圖所示，相似於第3圖，在形成鰭結構之後，形成保護層160以覆蓋鰭結構110B。保護層160由可防止第一半導體層免於氧化的材料所形成。在一些實施例中，保護層160由一或多層的氮化矽(SiN)、SiC、SiN及SiCN所形成。在一 些實施例中，保護層160的厚度為約1nm至10nm。在特定的實例中，保護層160的厚度為約2nm至5nm。在此實施例中，使用SiN作為保護層160。保護層160係藉由化學氣相沉積(CVD)、電漿輔助化學氣相沈積(PECVD)、常壓化學氣相沈積(APCVD)、低壓CVD(LPCVD)、高密度電漿CVD(HDPCVD)、原子層沉積(ALD)及/或其它合適的製程所形成。
在膜形成製程期間，基底溫度為約300℃至500℃。在一些實施例中，基底溫度可為約350℃至450℃。在膜形成製程期間，藉由維持基底溫度相對低於一般CVD製程的溫度，則可能抑制第一半導體層的鍺擴散至第二半導體層中。在一些實施例中，利用PECVD。
如第4圖所示，在形成保護層160之後，形成犧牲層170使得鰭結構110B嵌入犧牲層170之中。鰭結構110B可完全或部分嵌入犧牲層170之中。在一些實施例中，犧牲層170由諸如光阻層的有機材料或用於底部抗反射塗佈(BRAC)的材料所組成。
接著，如第20圖所示，相似於第5圖，藉由諸如回蝕製程來減少犧牲層170的厚度以暴露部分鰭結構。在特定的實施例中，可藉由使用包括O2及至少CF4及CHF3之一的電漿，並於約0℃至300℃的溫度及於約1至10托耳(torr)的壓力下實行回蝕製程。藉由調整蝕刻時間，可得到殘留犧牲層所期望的厚度。在本揭露中，厚度H3為約20nm至80nm，且在其它實施例中可為約30nm至60nm。
另外，亦可藉由直接調整例如膜的形成條件而非 回蝕厚犧牲層，以形成具有目標厚度的薄犧牲層。
接著，如第21圖所示，相似於第6圖，藉由諸如乾蝕刻及/或濕蝕刻以移除從犧牲層170暴露的保護層160之上部。
接著，相似於第7圖，形成隔離絕緣層180。隔離絕緣層180由一或多層諸如二氧化矽、SiO、SiON、SiN、氟摻雜矽酸鹽玻璃(FSG)或任何其它合適的介電材料所組成。當隔離絕緣層180由氧化矽所組成時，氧化矽可摻雜諸如硼及/或磷。在一些實施例中，可藉由可流動的CVD(FCVD)形成隔離絕緣層180。
在沉積可流動膜之後，將其固化並退火以移除不期望的成分而形成氧化矽。當移除不期望的成分時，該可流動膜收縮並緻密化。在一些實施例中，執行多重退火製程。將可流動膜固化並退火一次以上。在本實施例中，也可將退火溫度調整至相對較低的溫度，例如約500℃至800℃。由於鰭結構110B的底部之側壁被保護層160所覆蓋，因此鰭結構110B的底部在用以形成隔離絕緣層180的熱製程期間不會被氧化。
如第22圖所示，相似於第8圖，藉由例如化學機械研磨(CMP)方法或其它諸如回蝕製程的平坦化方法移除隔離絕緣層180的上部及罩幕圖案150。
接著，如第23圖所示，部分凹蝕鰭結構110B之上部，從而形成開口190’。可藉由乾蝕刻及/或濕蝕刻實行鰭結構110B之上部的蝕刻。在此實施例中，將鰭結構110B之上部蝕刻至從保護層160的上端測量之深度D1。在一些實施例中，距離 D1為約10nm至60nm，或在其它實施例可為約20nm至50nm。
如第24圖所示，在形成開口190’之後，磊晶形成第五半導體層120’於開口190’之中。第五半導體120'之實例為Si或Si(1-y)Gey，其中y小於約0.1。在此實施例中，第二半導體層為Si。在一些實施例中，第五半導體層120’具有約30nm至200nm的厚度。在特定的實施例中，第五半導體層120’的厚度為約50nm至150nm。第24圖所示之最終結構大致相同於第8圖。
在形成第24圖的結構之後，實行第9-12或15-16圖之相似操作以得第12及13圖之結構。應當理解，FinFET裝置可經歷進一步的CMOS製程以形成各種特徵，例如接觸件/介層窗、互連金屬層、介電層、保護層等。
在此描述之各種實施例或實例提供一些優於現有技術之優點。在本揭露的一些實施例中，藉由插入設置於第一半導體層(由例如Si(1-x)Gex所製成，其中x為約0.1至0.5)與p型FET中的通道區(由例如Ge或Si(1-z)Gez所製成，其中z大於第一半導體層(Si(1-x)Gex)之x)之間的殘留之第二半導體層(由例如Si所製成)，則可能抑制第一半導體層與通道區之間的Ge擴散。此外，藉由降低用於隔離絕緣層的退火溫度，可進一步抑制Ge擴散。再者，有可能抑制源極汲極區的洩漏。
應當理解，並非所有優點都已必然在此討論，並非所有實施例或實例皆需具有特定的優點，且其他實施例或實例可提供不同的優點。
根據本揭露之一面向，在一種半導體的製造方法中，形成第一半導體層於基板上。形成第二半導體層於第一半 導體層上。藉由圖案化第一及第二半導體層形成鰭結構。鰭結構包括由第一半導體層所構成的底部及由第二半導體層所構成的上部。形成覆蓋層於鰭結構的底部部分上以覆蓋鰭結構的底部側壁及鰭結構的上部側壁之底部部分。形成絕緣層於具有覆蓋層的鰭結構上方，使得鰭結構嵌入絕緣層中。移除鰭結構上部的一部分，從而形成開口於絕緣層之中，且第二半導體層的一層殘留在開口的底部中。在開口中形成第三半導體層於第二半導體層之殘留層上。凹蝕絕緣層使得第三半導體層的至少一部分從絕緣層中暴露。形成閘極結構於暴露的第三半導體層上方。
根據本揭露之另一面向，在一種半導體的製造方法中，形成第一半導體層於基板上。形成第二半導體層於第一半導體層上。藉由圖案化第一及第二半導體層形成第一鰭結構及一第二鰭結構，第一及第二鰭結構分別包括由第一半導體層所構成的底部及由第二半導體層所構成的上部；形成覆蓋層於第一及第二鰭結構的底部部分上以覆蓋第一及第二鰭結構的底部側壁及第一及第二鰭結構的上部側壁之底部部分。形成絕緣層於具有覆蓋層的第一及第二鰭結構上方，使得第一及第二鰭結構嵌入絕緣層中。移除第一鰭結構上部的一部分，從而形成開口於絕緣層之中，且第二半導體層的一層殘留在開口的底部中，同時保護第二鰭結構之上部免於被蝕刻。在開口中形成第三半導體層於第二半導體層之殘留層上。凹蝕絕緣層使得第三半導體層的至少一部分及第二鰭結構之上部的一部分從絕緣層中暴露。形成第一閘極結構於暴露的第三半導體層上方， 並形成第二閘極結構於第二鰭結構之暴露的部分上方。
根據本揭露之另一面向，一種半導體裝置包括第一FinFET裝置。第一FinFET裝置包括第一鰭結構，以第一方向延伸並從隔離絕緣層中突出。設置於基底上方的第一鰭結構及隔離絕緣層。第一鰭結構包括由第一半導體材料所構成的第一層、設置於第一層上方並由第二半導體材料所構成的第二層及設置於第二層上方並由第三半導體材料所構成的第三層。第一FinFET更包括第一覆蓋層，其設置於第一鰭結構之底部部分上，以覆蓋第一鰭結構的底部側壁及第一鰭結構的上部側壁之底部部分。第一FinFET更包括具有閘電極層及閘介電層的第一閘極堆疊，覆蓋第一鰭結構的一部分並以垂直於第一方向的第二方向延伸。第三層作為該第一FinFET的通道區。第一半導體層包括Si(1-x)Gex，第二半導體層包括Si(1-y)Gey，及第三半導體層包括Ge或Si(1-z)Gez，其中y小於x且z大於y。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以更佳的了解本揭露的各個方面。本技術領域中具有通常知識者應該可理解，他們可以很容易的以本揭露為基礎來設計或修飾其它製程及結構，並以此達到相同的目的及/或達到與本揭露介紹的實施例相同的優點。本技術領域中具有通常知識者也應該了解這些相等的結構並不會背離本揭露的發明精神與範圍。本揭露可以作各種改變、置換、修改而不會背離本揭露的發明精神與範圍。
110‧‧‧第一半導體層
120A‧‧‧通道區
125‧‧‧第二半導體層
180‧‧‧隔離絕緣層
210A‧‧‧通道區
220‧‧‧閘介電層
230‧‧‧閘電極層

Claims (10)

  1. 一種半導體裝置的製造方法，包括：形成一第一半導體層於一基板上；形成一第二半導體層於該第一半導體層上；藉由圖案化該第一及第二半導體層形成一鰭結構，該鰭結構包括由該第一半導體層所構成的底部及由該第二半導體層所構成的上部；形成一覆蓋層於該鰭結構的底部部分上以覆蓋該鰭結構的底部側壁及該鰭結構的上部側壁之底部部分；形成一絕緣層於具有該覆蓋層的該鰭結構上方，使得該鰭結構嵌入該絕緣層中；移除該鰭結構上部的一部分，從而形成一開口於該絕緣層之中，且該第二半導體層的一層殘留在該開口的底部中；在該開口中形成一第三半導體層於該第二半導體層之殘留層上；凹蝕該絕緣層使得該第三半導體層的至少一部分從該絕緣層中暴露；及形成一閘極結構於該暴露的第三半導體層上方。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中：該第一半導體層包括Si(1-x)Gex；該第二半導體層包括Si(1-y)Gey；該第三半導體層包括Ge或Si(1-z)0Gez；y小於x；及 z大於y；其中x為0.1至0.5，y等於0或小於0.1，z等於或大於0.5。
  3. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中：在形成該第二半導體層於該第一半導體層上的步驟中，形成Si作為該第二半導體層；及在形成一閘極結構之後，該第二半導體結構的殘留層包括小於10原子百分比量的Ge。
  4. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該覆蓋層的形成包括：形成該覆蓋層材料的一毯覆層於該鰭結構上方；形成一犧牲層以覆蓋具有該毯覆層的該鰭結構之底部，使得具有該毯覆層的該鰭結構上部從該犧牲中暴露；及移除從該犧牲層中暴露的該鰭結構上部的該毯覆層。
  5. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該覆蓋層之上端較該第一半導體層與該第二半導體層之間的介面高10nm至60nm。
  6. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該覆蓋層包括氮化矽。
  7. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中藉由化學氣相沉積(CVD)並接著於低於800℃的溫度下退火以形成該絕緣層。
  8. 一種半導體裝置的製造方法，包括：形成一第一半導體層於一基板上； 形成一第二半導體層於該第一半導體層上；藉由圖案化該第一及第二半導體層形成一第一鰭結構及一第二鰭結構，該第一及第二鰭結構分別包括由該第一半導體層所構成的底部及由該第二半導體層所構成的上部；形成一覆蓋層於該第一及第二鰭結構的底部部分以覆蓋該第一及第二鰭結構底部之側壁及該第一及第二鰭結構上部之側壁的底部部分；形成一絕緣層於具有該覆蓋層的該第一及第二鰭結構上方，使得該第一及第二鰭結構嵌入該絕緣層中；移除該第一鰭結構上部的一部分，從而形成一開口於該絕緣層之中，且該第二半導體層的一層殘留在該開口的底部中，同時保護該第二鰭結構上部免於被蝕刻；在該開口中形成一第三半導體層於該第二半導體層之殘留層上；凹蝕該絕緣層使得該第三半導體層的至少一部分及該第二鰭結構上部的一部分從該絕緣層中暴露；及形成一第一閘極結構於該暴露的第三半導體層上方，並形成一第二閘極結構於該第二鰭結構之暴露的部分上方。
  9. 一種半導體裝置，包括一第一鰭式場效電晶體(FinFET)，該第一FinFET包括：一第一鰭結構，以第一方向延伸並從一隔離絕緣層中突出，該第一鰭結構及該隔離絕緣層設置於一基底上方，該第一鰭結構包括由一第一半導體材料所構成的一第一層、設置於該第一層上方並由一第二半導體材料所構成的一第 二層及設置於該第二層上方並由一第三半導體材料所構成的一第三層；一第一覆蓋層，設置於該第一鰭結構之底部部分上，以覆蓋該第一鰭結構的底部側壁及該第一鰭結構的上部側壁的底部部分；及一第一閘極堆疊，包括一閘電極層及一閘介電層，覆蓋該第一鰭結構的一部分並以垂直於第一方向的第二方向延伸，其中：該第三層作為該第一FinFET的通道區；該第一半導體層包括Si(1-x)Gex；該第二半導體層包括Si(1-y)Gey；該第三半導體層包括Ge或Si(1-z)Gez；y小於x；及z大於y。
  10. 如申請專利範圍第9項所述之半導體裝置，更包括一第二FinFET，該第二FinFET包括：一第二鰭結構，以第一方向延伸並從該隔離絕緣層中突出，該第一鰭結構及該隔離絕緣層設置於該基底上方，該第二鰭結構包括由該第一半導體材料所構成的一第一層及設置於該第一層上方並由該第二半導體材料所構成的一第二層；一第二覆蓋層，設置於該第二鰭結構之底部部分上，以覆蓋該第二鰭結構的底部側壁及該第二鰭結構的上部側壁的底部部分；及 一第二閘極堆疊，包括一閘電極層及一閘介電層，覆蓋該第二鰭結構的一部分並以垂直於第一方向的第二方向延伸；其中該第二層作為該第二FinFET的通道區。
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