TWI572035B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI572035B
TWI572035B TW104137844A TW104137844A TWI572035B TW I572035 B TWI572035 B TW I572035B TW 104137844 A TW104137844 A TW 104137844A TW 104137844 A TW104137844 A TW 104137844A TW I572035 B TWI572035 B TW I572035B
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Taiwan
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electrode
layer
gate
plug
dummy electrode
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TW104137844A
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TW201639161A (zh
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張哲誠
林志翰
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台灣積體電路製造股份有限公司
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Description

半導體裝置及其製造方法
本揭露係關於一種半導體積體電路，更具體而言，關於具有鰭結構之半導體裝置及其製程。
隨著半導體產業發展邁入奈米技術製程節點以追求更高之裝置密度、更高之性能、與較低之成本，來自製造與設計議題的挑戰帶來例如鰭式場效(Fin Field-Effect,Fin FET)電晶體之三維設計之發展。Fin FET裝置一般包括具有高寬高比之半導體鰭且於其中形成半導體電晶體裝置之通道與源極/汲極區。利用增大通道與源極/汲極區之表面面積的優點，沿著鰭結構之側邊且在鰭結構之側邊上方(例如，包裹)形成閘極，以產生更快、更可靠且更好控制之半導體電晶體裝置。一般在FinFET裝置中一起使用金屬閘極結構與具有高介電常數之高k閘極介電質，並藉由閘極替換技術製備金屬閘極結構。
為了解決現有技術中存在之問題，根據本揭露之一方面，提供一種半導體裝置，包含：第一FinFET電晶體，包括在第一方向延伸之第一鰭結構、形成於該第一鰭結構上方之第一閘極介電質、及形成於該第一閘極介電質上方且在與該第一方向垂直的第二方向延伸之第一閘極電極；第二FinFET電晶體，包括第二鰭結構、形成於該第二鰭結構 上方之第二閘極介電質、及形成於該第二閘極介電質上方且在該第二方向延伸之第二閘極電極；以及分離插塞，由絕緣材料製成且設置於該第一FinFET電晶體與該第二FinFET電晶體之間；其中，在沿著該第二方向且橫穿該第一閘極電極、該第二閘極電極及該分離插塞之剖面中，該分離插塞的最大寬度位於高度Hb處，該高度Hb小於該分離插塞的高度Ha之3/4。
在上述半導體裝置中，於該剖面中，該分離插塞具有錐形形狀，該錐形形狀之頂部寬度小於底部寬度。
在上述半導體裝置中，該分離插塞之底部處的該分離插塞之錐角為90度以上。
在上述半導體裝置中，該第一閘極電極包括一層或複數層第一功函數調整金屬、及第一金屬閘極材料；該第二閘極電極包括一層或複數層第二功函數調整金屬、及第二金屬閘極材料。
在上述半導體裝置中，該第一FinFET電晶體與該第二FinFET電晶體具有相同通道型。
在上述半導體裝置中，該第一FinFET電晶體之通道型與該第二FinFET電晶體之通道型不同。
在上述半導體裝置中，該第一FinFET電晶體包括兩個以上之該第一鰭結構。
根據本揭露之另一方面，提供一種製造半導體裝置之方法，包含：形成虛設電極結構，該虛設電極結構包括虛設電極層、及設置於該虛設電極層之兩側的層間介電層；圖案化該虛設電極層，以將該虛設電極層分成藉由開口分隔之至少第一虛設電極與第二虛設電極；藉由以絕緣材料填充該開口而形成分離插塞；去除該第一虛設電極與該第二虛設電極以形成第一電極空間與第二電極空間，該分離插塞暴露於該第一電極空間與該第二電極空間之間；蝕刻該暴露出的分離插塞；以 及分別於該第一電極空間與該第二電極空間中形成第一閘極結構與第二閘極結構；其中，於蝕刻該暴露出的分離插塞後，在橫穿該第一電極空間、該第二電極空間及該分離插塞之剖面中，該分離插塞的最大寬度位於高度Hb處，該高度Hb小於該分離插塞的高度Ha之3/4。
在上述方法中，於蝕刻該暴露出的分離插塞後，在該剖面中，該分離插塞具有錐形形狀，該錐形形狀之頂部寬度小於底部寬度。
在上述方法中，於蝕刻該暴露出的分離插塞後，該分離插塞之底部處的該分離插塞之錐角為90度以上。
在上述方法中，形成該分離插塞包含：於該圖案化的虛設電極上方及該開口中形成該絕緣材料；以及去除該絕緣材料之一部分，而形成填充於該開口中之該絕緣材料的該分離插塞。
在上述方法中，在去除該絕緣材料之一部分的步驟中使用化學機械拋光方法。
在上述方法中，形成該虛設電極結構包含：形成鰭結構；形成隔離層，以使該鰭結構之下部嵌入該隔離層中；於該鰭結構上方形成第一介電層；以及於該第一介電層上方形成該虛設電極層。
在上述方法中，在蝕刻該暴露出的分離插塞之步驟中，去除該第一介電層。
在上述方法中，形成該第一閘極結構與該第二閘極結構包含：形成第二介電層；於該第二介電層上方形成該第一閘極結構之一層或複數層第一功函數調整金屬；於該第二介電層上方形成該第二閘極結構之一層或複數層第二功函數調整金屬；於該一層或複數層第一功函數調整金屬上方形成第一金屬閘極材料；以及於該一層或複數層第二功函數調整金屬上方形成第二金屬閘極材料。
根據本揭露之更另一方面，提供一種製造半導體裝置之方法，包含：形成虛設電極結構，該虛設電極結構包括虛設電極層、及設置於 該虛設電極層之兩側的層間介電層；圖案化該虛設電極層，以將該虛設電極層分成藉由開口分隔之至少第一虛設電極與第二虛設電極；藉由以絕緣材料填充該開口而形成分離插塞；去除該第一虛設電極與該第二虛設電極以形成第一電極空間與第二電極空間，該分離插塞暴露於該第一電極空間與該第二電極空間之間；以及分別於該第一電極空間與該第二電極空間中形成第一閘極結構與第二閘極結構；其中，在形成該分離插塞前，該開口具有錐形形狀，該錐形形狀之該開口的頂部寬度小於該開口的底部寬度。
在上述方法中，在該開口中測量到的該開口之底部處的該開口之錐角為90度以下。
在上述方法中，圖案化該虛設電極層包含：於該虛設電極結構上方形成氧化矽層；圖案化該氧化矽層；以及藉由使用圖案化的該氧化矽層作為遮罩而蝕刻該虛設電極層。
在上述方法中，形成該分離插塞包含：於該圖案化的虛設電極上方及該開口中形成該絕緣材料；以及去除該絕緣材料之一部分及作為該遮罩使用之該圖案化的氧化矽層，而形成填充於該開口中之該絕緣材料的該分離插塞。
在上述方法中，在去除該絕緣材料之一部分及作為該遮罩使用之該圖案化的氧化矽層之步驟中，使用化學機械拋光方法。
1‧‧‧FinFET(Fin Field-Effect，鰭式場效)裝置
1A‧‧‧第一裝置區
1B‧‧‧第二裝置區
10‧‧‧基板
20、20A、20B‧‧‧鰭結構
25‧‧‧源極/汲極區
30‧‧‧閘極介電層
40‧‧‧閘極電極
42‧‧‧功函數調整層
45‧‧‧金屬閘極層
50‧‧‧隔離絕緣層
60‧‧‧分離插塞
70‧‧‧層間介電層
70A、70B、70C‧‧‧層
80‧‧‧側壁絕緣層
100‧‧‧遮罩層(硬罩圖案)
105‧‧‧閘極氧化物層
106‧‧‧襯墊氧化物層
107‧‧‧氮化矽遮罩層
110‧‧‧多晶矽閘極層
120‧‧‧遮罩圖案
125‧‧‧狹縫
130‧‧‧開口
135‧‧‧開口
200‧‧‧遮罩層
210‧‧‧光阻圖案
OA‧‧‧開口
自後述詳述說明與附屬圖式，可最佳理解本申請案之各方面。須注意，依據產業之標準實施方式，各種構件並非依比例繪製。實際上，為了清楚討論，可任意增大或減小各種構件之尺寸。
圖1A係根據本揭露之一實施例的具有鰭結構之半導體FET裝置(FinFET)的例示性剖面圖；圖1B係根據本揭露之一實施例的具有鰭結構之半導體FET裝置的例示性頂視圖；圖1C係根據本揭露之一 實施例的對應於圖1B中之框選部分的具有鰭結構之半導體FET裝置的例示性立體圖；圖2至圖12E係根據本揭露之一實施例顯示的用於製造FinFET裝置之例示性製程；以及圖13至圖18係根據本揭露之另一實施例顯示的製造FinFET裝置之例示性順序製程的剖面圖。
以下揭露之內容提供許多不同的實施例或範例，用於實施本案所提供之主題的不同特徵。元件與配置的特定範例之描述如下，以簡化本揭露。自然，此等僅為範例，並非用於限制本揭露。例如，元件之尺寸並未限制於所揭露之範圍或數值，但可取決於製程條件及/或期望之裝置性能。此外，以下在第二構件上或上方形成第一構件的敘述，可包含形成直接接觸之第一與第二構件的實施例，亦可包含在該第一與第二構件之間形成其他構件，因而該第一與第二構件並未直接接觸的實施例。為了簡化與清晰化，各種構件能夠以不同尺寸任意繪製。
另，為了易於描述，可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或構件與另一元件或構件的關係。空間對應詞語係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置可被定位(旋轉90度或是其他位向)，並可相應解釋本申請案使用的空間對應描述。此外，詞語「由…製成」可意指「包含」或「由…組成」。
圖1A係根據本揭露之一實施例的具有鰭結構之半導體FET裝置(FinFET)的例示性剖面圖；圖1B係根據本揭露之一實施例的具有鰭結構之半導體FET裝置的例示性頂視圖；圖1C係根據本揭露之一實施例的具有鰭結構之半導體FET裝置的例示性立體圖。圖1A係沿 著圖1B中之X-X線截取的剖面圖，且圖1C對應於圖1B中之框選部分A。於此等圖中，為了簡化而省略一些層/構件。圖1A至圖1C顯示在已形成金屬閘極結構之後的裝置結構。
FinFET裝置1包括第一裝置區1A與第二裝置區1B。第一裝置區1A包括一或複數個第一FinFET裝置；第二裝置區包括一或複數個第二FinFET裝置。第一FinFET電晶體之通道型與第二FinFET電晶體之通道型相同或不同。
於一實施例中，第一裝置區1A包括p型MOSFET，且第二裝置區1B包括n型MOSFET。於其他實施例中，第一與第二裝置區域包括p型MOSFET，第一與第二裝置區域包括n型MOSFET，或第一與第二裝置區域均包括p型與n型MOSFET。
除其他構件之外，FinFET裝置1包括基板10、鰭結構20、閘極介電質層30、及閘極電極40。於此一實施例中，基板10為矽基板。作為替代實施例，基板10可包括：其他元素半導體，如鍺；化合物半導體，包括如SiC與SiGe之IV-IV族化合物半導體、如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP之III-V族化合物半導體；或其等之組合。於一實施例中，基板10係SOI(絕緣層上覆矽)基板之矽層。當使用SOI基板時，鰭結構可從SOI基板之矽層突出或可從SOI基板之絕緣層突出。在後者之情況下，將SOI基板之矽層用於形成鰭結構。作為基板10，亦可使用例如非晶Si或非晶SiC之非晶質基板、或例如氧化矽之絕緣材料。基板10可包括已適當地摻雜雜質(例如，p型或n型導電性)之各種區域。
鰭結構20設置於基板10上方。鰭結構20可由與基板10相同之材料製成，且可從基板10連續地延伸。於此一實施例中，鰭結構由Si製成。鰭結構20之矽層可為本質，或適當摻雜n型雜質或p型雜質。
在圖1A中，分別於第一裝置區1A與第二裝置區1B中設置兩個鰭結構20。然而，鰭結構之數量並未限制為兩個(或四個)。數量可為一個、兩個、三個、五個或其以上。此外，可於鄰近鰭結構20之兩側設置複數個虛設鰭結構中之一個，以在圖案化製程中改善圖案保真度。在一些實施例中，鰭結構20的寬度W1界於約5nm至約40nm之範圍內，且在特定實施例中，鰭結構20的寬度W1可界於約7nm至約15nm之範圍內。在一些實施例中，鰭結構20的高度界於約100nm至約300nm之範圍內，且在其他實施例中，可界於約50nm到100nm之範圍內。
位於閘極電極40下方之鰭結構20的下部被稱作井層，而鰭結構20的上部被稱作通道層。在閘極電極40下方，井層嵌入至隔離絕緣層50中，且通道層從隔離絕緣層50突出。通道層的下部亦可嵌入隔離絕緣層50中約1nm至約5nm之深度。
在一些實施例中，井層的高度界於約60nm到100nm之範圍內，且通道層的高度界於約40nm到60nm之範圍內。
進一步，在鰭結構20間之空間，及/或一鰭結構與形成於基板10上方的另一元件間之空間，填充包括絕緣材料之隔離絕緣層50(或所謂的「淺溝槽隔離(shallow-trench-isolation,STI)」層)、及設置於隔離絕緣層50上方之層間介電層70。用於隔離絕緣層50及層間介電層70之絕緣材料，可包括氧化矽、氮化矽、氮氧化矽(SiON)、SiOCN、摻雜氟之矽酸鹽玻璃(FSG)、或低k介電材料。隔離絕緣層50之絕緣材料可與層間介電層70之絕緣材料相同或不同。
從隔離絕緣層50突出之鰭結構20的通道層被閘極介電層30覆蓋，且閘極介電層30進一步被閘極電極40覆蓋。通道層之未被閘極電極40覆蓋的部分，作為MOSFET之源極及/或汲極(見圖1B)使用。鰭結構20在第一方向延伸，而閘極電極40在與第一方向垂直之第二方 向延伸。
在特定實施例中，閘極介電層30包括介電材料，例如氧化矽、氮化矽、高k介電材料或其他合適之介電材料及/或其等之組合。高k介電材料之範例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、二氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適之高k介電材料及/或其等之組合。
閘極電極40包括任何合適之材料，例如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適之材料及/或其等之組合。在特定實施例中，閘極電極包括金屬閘極層45。
在本揭露之特定實施例中，亦可於閘極介電層30與金屬閘極層45之間設置一或複數功函數調整層42。功函數調整層可包括單層或以多層結構替代，例如具有選擇之功函數以提高裝置性能之金屬層(功函數金屬層)、襯層、潤濕層、黏著層、金屬合金或金屬矽化物之各種組合。功函數調整層由例如Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他合適之金屬材料之單層、或兩種以上此等材料之多層的導電材料製成。在一些實施例中，功函數調整層可包括用於P通道FinFET之第一金屬材料(例如，在第一裝置區1A中)、及用於n通道FinFET之第二金屬材料(例如，在第二裝置區1B中)。例如，用於n通道FinFET之第一金屬材料，可包括具有與基板導帶的功函數實質上對準的功函數，或與鰭結構20的通道層之導帶的功函數至少實質上對準的功函數之金屬。同樣地，例如，用於p通道FinFET之第二金屬材料，可包括具有與基板價帶的功函數實質上對準的功函數，或與鰭結構20的通道層之價帶的功函數至少實質上對準的功函數之金屬。在一些實施例中，功函數調整層亦可包括多晶矽層。功函數調整層可藉由ALD、 PVD、CVD、電子束蒸發、或其他合適之製程形成。此外，可單獨地形成用於n通道FinFET與p通道FinFET之功函數調整層，其等可使用不同的金屬層。
藉由在源極與汲極區中適當地摻雜雜質，亦於未被閘極電極40覆蓋之鰭結構中形成源極與汲極區。可在源極與汲極區25上形成Si或Ge之合金與例如Co、Ni、W、Ti或Ta之金屬。Si及/或SiGe層可於源極-汲極區中磊晶形成，以形成突起之源極-汲極結構並對通道層施加適當應力。
此外，側壁絕緣層80設置於閘極電極40之兩側。層間介電層70覆蓋閘極電極40與源極/汲極區，且設置必要之配線及/或通孔/接觸孔以完成半導體裝置。
在一些實施例中，包括功函數調整層42與金屬閘極層45之閘極電極40的寬度W2，界於約20nm到40nm之範圍內。在一些實施例中，當在寬度方向配置複數閘極電極40時(見圖1B)，閘極電極的間距界於約60nm至100nm之範圍內。
如圖1A至圖1C所示，鄰近的閘極電極40藉由分離插塞60而彼此分離，分離插塞60係由絕緣材料製成。在圖1A所示之剖面圖中，分離插塞60具有錐形形狀，該錐形形狀具有較小的頂部尺寸(寬度)與較大的底部尺寸(寬度)。在特定實施例中，分離插塞頂部的寬度W3小於約20nm，且在一些實施例中可界於約5nm至約15nm範圍內。在特定實施例中，分離插塞底部的寬度W4小於約35nm，且在一些實施例中可界於約10nm至約30nm範圍內。此處，分離插塞之頂部，對應於閘極電極40之上表面；且分離插塞60之底部，對應於閘極介電層30之底部，或隔離絕緣層50與層間介電層70間之介面。用於分離插塞60之絕緣材料可包括氧化矽、氮化矽、氮氧化矽(SiON)、SiOCN、摻雜氟之矽酸鹽玻璃(FSG)、或低K介電材料，且其可與用於隔離 絕緣層50及/或層間介電層70之絕緣材料的材料相同或不同。
用於分離插塞60之絕緣材料，可與用於隔離絕緣層50及/或層間介電層70之絕緣材料相同或不同。
圖2至圖12E係根據本揭露之一實施例顯示的製造FinFET裝置之例示性順序製程的剖面圖。應理解可在圖2至圖12E所示的製程之前、期間與之後提供另外的操作，且對於該方法之另一實施例，可替換或取消下述內容中的一些操作。操作/製程之順序可互換。此外，在美國專利公開號為2013/0161762中已公揭露藉由閘極替代技術在鰭結構上方製造金屬閘極結構之一般操作，將其全體內容皆引用作為本說明書之揭示內容。
為了製造鰭結構，例如，藉由熱氧化製程及/或化學氣相沉積(CVD)製程而於基板10上方形成遮罩層。基板10，例如係具有界於約1.12×1015cm-3至約1.68×1015cm-3範圍內之雜質濃度的p型矽基板。於其他實施例中，基板10係具有界於約0.905×1015cm-3至約2.34×1015cm-3範圍內之雜質濃度的n型矽基板。例如，在一些實施例中，遮罩層包括襯墊氧化物(例如氧化矽)層及氮化矽遮罩層。
襯墊氧化物層，可藉由使用熱氧化或CVD製程而形成。氮化矽遮罩層，可藉由物理氣相沉積(PVD)(例如濺鍍方法)、CVD、電漿增強化學氣相沉積(PECVD)、大氣壓力化學氣相沉積(APCVD)、低壓CVD(LPCVD)、高密度電漿CVD(HDPCVD)、原子層沉積(ALD)，及/或其他製程形成。
在一些實施例中，襯墊氧化物層的厚度界於約2nm至約15nm之範圍內，而氮化矽遮罩層的厚度界於約2nm至約50nm之範圍內。於遮罩層上方進一步形成遮罩圖案。遮罩圖案，例如係藉由光微影形成之光阻圖案。
藉由使用遮罩圖案作為蝕刻遮罩，而形成襯墊氧化物層106與氮 化矽遮罩層107之硬罩圖案100。在一些實施例中，硬罩圖案的寬度界於約5nm至約40nm之範圍內。在特定實施例中，硬罩圖案的寬度界於約7nm至約12nm之範圍內。
如圖2所示，藉由使用遮罩圖案作為蝕刻遮罩，藉由使用乾蝕刻方法及/或濕蝕刻方法之溝槽蝕刻將基板10圖案化為鰭結構20。鰭結構20的高度界於約100nm至約300nm之範圍內。在特定實施例中，鰭結構20的高度界於約50nm至約100nm之範圍內。當鰭結構的高度不均勻時，可從對應於鰭結構的平均高度之平面測量從基板起的高度。
於此一實施例中，使用矽塊材晶圓作為起始材料並構成基板10。然而，在一些實施例中，可使用其他類型之基板作為基板10。例如，可使用絕緣體上覆矽(SOI)晶圓作為起始材料，且SOI晶圓之絕緣層構成基板10，且將SOI晶圓之矽層使用在鰭結構20。
如圖3所示，於基板10上方形成隔離絕緣層50以完全覆蓋鰭結構20。
隔離絕緣層50，例如係由藉由LPCVD(低壓化學氣相沉積)、電漿CVD或可流動CVD形成之二氧化矽製成。在可流動CVD中，沉積可流動介電材料，而非氧化矽。正如其等之名稱所表示，可流動介電材料在沉積期間可「流動」以填充具有高寬高比之間隙或空間。一般而言，將各種化學物質加入含矽前驅物以允許沉積膜流動。在一些實施例中，添加氮氫鍵合物。可流動介電前驅物之範例，特別是可流動氧化矽前驅物之範例，包括矽酸鹽、矽氧烷、甲基倍半矽氧烷(methyl silsesquioxane,MSQ)、氫倍半矽氧烷(hydrogen silsesquioxane,HSQ)、MSQ/HSQ、全氫矽氮烷(perhydrosilazane,TCPS)、全氫聚矽氮烷(perhydro-polysilazane,PSZ)、四乙氧基矽烷(TEOS)、或矽烷基胺(silyl-amine)例如三甲矽烷基胺(trisilylamine,TSA)。在複數操 作製程中形成此等可流動氧化矽材料。於沉積可流動膜後，對可流動膜進行固化而後退火，去除非期望之元素而形成氧化矽。當去除非期望之元素後，可流動膜緻密化並收縮。在一些實施例中，進行複數退火製程。在例如約1000℃至約1200℃之範圍內的溫度，將可流動膜固化與退火一次以上，且一共持續例如30小時以上之時間段。隔離絕緣層50可藉由使用SOG而形成。在一些實施例中，可使用SiO、SiON、SiOCN或摻雜氟之矽酸鹽玻璃(FSG)作為隔離絕緣層50。
於形成隔離絕緣層50後，實施平坦化操作以去除隔離絕緣層50之部分、以及包括襯墊氧化物層106與氮化矽遮罩層107之遮罩層100。而後，進一步去除隔離絕緣層50，從而如圖4所示，暴露出鰭結構20之將成為通道層的上部。
於形成隔離絕緣層50後，可實施熱製程(例如退火製程)以改善隔離絕緣層50的品質。在特定實施例中，藉由使用快速熱退火(RTA)以實施熱製程，快速熱退火(RTA)之實施條件為：在惰性氣體環境中(例如N2、Ar或He環境中)，界於約900℃至約1050℃之範圍內的溫度，且持續時間為1.5秒至約10秒。
於隔離絕緣層50與暴露出之鰭結構20上方形成閘極氧化物層105與多晶矽層，而後實施圖案化操作以獲得由多晶矽製成之多晶矽閘極層110。閘極氧化物層105可為藉由CVD、PVD、ALD、電子束蒸發或其他合適之製程形成的氧化矽。在一些實施例中，多晶矽層的厚度界於約5nm至約100nm之範圍內。
側壁絕緣層80亦形成於多晶矽閘極層110之兩側。
此外，層間介電層70形成於多晶矽閘極層110、側壁絕緣層80之間的空間中，以及多晶矽閘極層110上方。施行平坦化操作，例如回蝕製程及/或化學機械拋光(CMP)製程，以獲得如圖5A至圖5C所示之結構。圖5A係形成多晶矽閘極層110與層間介電層70後之 FinFET裝置的剖面圖；圖5B係形成多晶矽閘極層110與層間介電層70後之FinFET裝置的頂視圖；圖5C係形成多晶矽閘極層110與層間介電層70後之FinFET裝置的立體圖。圖5A係沿著圖5B中之X-X線截取的剖面圖，而圖5C對應於圖5B中之框選部分B。
如圖5B與圖5C所示，在特定實施例中，多晶矽閘極層110形成為線與空間配置，在一方向上以固定間距延伸。多晶矽閘極層110可包括另一線與空間配置，在垂直於上述一方向之另一方向延伸。
如圖6所示，遮罩圖案120形成於圖5C中所示之結構的上方。遮罩圖案120，例如係藉由具有狹縫125之光阻層形成。在一些實施例中，狹縫125的寬度界於約5nm至約100nm之範圍內。
如圖7所示，藉由使用遮罩圖案120，蝕刻多晶矽閘極層之一部分。在圖7中與之後，省略層間介電層70之一層70A以顯示蝕刻的多晶矽閘極層110，但仍顯示其他層70B與70C。在一些實施例中，藉由電漿蝕刻實施多晶矽閘極層之蝕刻，電漿蝕刻係使用包括處於3mTorr至20mTorr之壓力下的CH4、CF4、CH2F2、CHF3、O2、HBr、Cl2、NF3、N2及/或He之氣體。
藉由灰化製程及/或濕清洗製程，而去除遮罩圖案120(光阻圖案)。
圖8顯示形成使多晶矽閘極層110分隔之開口130後的組合結構。在圖8中，開口130之頂部形狀呈圓形。然而，取決於結構之尺寸、遮罩圖案120之圖案化條件、及/或多晶矽閘極層110之蝕刻條件，該形狀可為矩形、具有圓角之矩形、或橢圓形。
須注意，開口130之剖面圖具有倒錐形形狀，該倒錐形形狀具有較大的頂部尺寸與較小的底部尺寸。
例如，藉由使用CVD製程，在圖8中所示之結構上方形成絕緣材料，並以絕緣材料填充開口130。CVD製程可包括LPCVD製程、電 漿CVD製程、及/或可流動CVD製程。在一些實施例中，於可流動CVD製程中，可使用包括SiH4、NH3、N2、O2、N2O、Cl2、及/或NO2的氣體，並在約200℃至約1000℃之範圍內的溫度實施沉積。
在多晶矽閘極層上方形成絕緣材料之非必要部分後，藉由平坦化操作去除側壁絕緣層與層間介電層，而獲得如圖9所示之分離插塞60。平坦化操作可包括CMP及/或回蝕製程。
於形成分離插塞60後，藉由乾蝕刻及/或濕蝕刻去除多晶矽閘極層110。如圖10所示，藉由去除多晶矽閘極層110，暴露出分離插塞60。由於鰭結構20之上部被閘極氧化物105層覆蓋，故鰭結構20在多晶矽閘極蝕刻製程中未被蝕刻。
此處，由於開口130之剖面具有倒錐形形狀，故該倒錐形形狀具有較大的頂部尺寸與較小的底部尺寸，而使暴露出之分離插塞60具有倒錐形形狀，該倒錐形形狀具有較大的頂部尺寸與較小的底部尺寸。
如圖11所示，對暴露出之分離插塞60實施另一蝕刻製程以使分離插塞之剖面具有較小的頂部尺寸與較大的底部尺寸之錐形形狀。在一些實施例中，藉由電漿蝕刻實施分離插塞之另一蝕刻，電漿蝕刻係使用包括處於3mTorr至20mTorr之壓力下的CH4、CF4、CH2F2、CHF3、O2、HBr、Cl2、NF3、N2及/或He之氣體。分離插塞的電漿蝕刻可包括非等向性蝕刻及其之等向性蝕刻。
圖12A至圖12E顯示其他蝕刻操作之具體細節與變化。在去除多晶矽閘極層110後，暴露出倒錐形之分離插塞60。分離插塞60之底部處的錐角θ，為界於約80度至約87度之範圍內的銳角(小於90度)。
如圖12B所示，藉由實施其他蝕刻操作，減小分離插塞之上部的寬度，而獲得錐形形狀之分離插塞60。分離插塞60之底部處的錐角θ為90度以上。在一些實施例中，錐角θ界於約93度至約100度之 範圍內。
如圖12C至圖12D所示，在一些實施例中，取決於其他蝕刻操作之條件，分離插塞60在剖面中之形狀可具有圓形、六邊形或圓桶形。在圖12C至圖12D中，剖面中的最大寬度位於高度Hb處，高度Hb小於分離插塞的高度Ha的3/4。在一些實施例中，Hb小於Ha的1/2。
在分離插塞60之形狀的此等變化中，由於暴露出之分離插塞的頂部寬度減小，故開口區域OA變得更寬。更寬之開口OA可使金屬閘極結構之金屬材料更為共形地填充藉由去除多晶矽閘極層110而形成的空間。
在圖11的操作後，於分離插塞之間的空間中形成金屬閘極結構，分離插塞之間的空間係藉由去除多晶矽閘極層110而創造，從而獲得圖1A至圖1C中所示之結構。
圖13至圖18係根據本揭露之另一實施例顯示的製造FinFET裝置之例示性順序製程的剖面圖。應理解，可在圖13至圖18所示的製程之前、期間與之後提供另外的操作，且對於該方法之另一實施例，可替換或取消下述內容中的一些操作。操作/製程之順序可互換。
於形成圖5A至圖5C中所示之結構後，在多晶矽閘極層110、側壁絕緣層80與層間介電層70上方形成遮罩層200。遮罩層係對多晶矽具有高蝕刻選擇性之材料。在特定例子中，遮罩層200為具有界於約10nm至約300nm之範圍內的厚度之氧化矽。如圖13所示，於遮罩層200上，形成具有開口之光阻圖案210。
如圖14所示，藉由使用光阻圖案210作為遮罩，將遮罩層200圖案化。
如圖15所示，藉由使用圖案化的遮罩層200作為蝕刻遮罩，而將多晶矽閘極層110圖案化，從而使開口135具有錐形形狀。在一些實施例中，在開口中測量到的開口135之底部處的錐角θ’為90度以下， 且可界於約80度至約87度之範圍內。
為了形成開口135，可使用電漿蝕刻。在一些實施例中，可使用處於約10Pa至約100Pa之壓力下的氟碳化合物氣體、氯碳化合物氣體、氟氯碳化物氣體或其等之混合物作為蝕刻氣體。
如圖16所示，藉由使用例如CVD製程，而在圖15中所示之結構上方形成絕緣材料，並以絕緣材料填充開口135。
如圖17所示，藉由包括CMP及/或回蝕製程之平坦化操作，去除絕緣材料之一部分與遮罩層200，從而獲得具有錐形形狀之分離插塞60。
於形成分離插塞60後，藉由乾蝕刻及/或濕蝕刻去除多晶矽閘極層110。如圖18所示，藉由去除多晶矽閘極層110，而暴露出分離插塞60。
在圖18中，分離插塞60之底部處的錐角θ為90度以上。在一些實施例中，錐角θ界於約93度至約100度之範圍內。
在圖18的操作後，於分離插塞之間的空間中形成金屬閘極結構，分離插塞之間的空間係藉由去除多晶矽閘極層110而創造，從而獲得圖1A至圖1C所示之結構。
本說明書中描述之各實施例或範例提供各種優於現有技術之優點。例如，由於分離插塞之頂部的寬度被減小為具有小於底部寬度之頂部寬度，在去除多晶矽閘極層後之開口區域變得更寬，特別是，頂部寬度變得更寬。該更寬之開口可使金屬閘極結構之金屬材料更為共形地填充藉由去除多晶矽閘極層而形成的空間。
此外，由於蝕刻分離插塞，分離插塞的總寬度變得更小。因此，兩個相鄰的鰭結構之間的距離(圖1所示之鰭結構20A與20B)變得更小。
應理解，並非所有的優點皆必須在本說明書中論述，並無特定優 點係所有實施例或範例所必須，其他實施例或範例可提供不同優點。
根據本揭露之一方面，一種半導體裝置包括：第一FinFET電晶體、第二FinFET電晶體、及設置於第一FinFET電晶體與第二FinFET電晶體之間的分離插塞。第一FinFET電晶體包括在第一方向延伸之第一鰭結構、形成於第一鰭結構上方之第一閘極介電質、及形成於第一閘極介電質上方且在與第一方向垂直的第二方向延伸之第一閘極電極。第二FinFET電晶體包括第二鰭結構、形成於第二鰭結構上方之第二閘極介電質、及形成於第二閘極介電質上方且在第二方向延伸之第二閘極電極。分離插塞由絕緣材料製成。在沿著第二方向且橫穿第一閘極電極、第二閘極電極及分離插塞之剖面中，分離插塞的最大寬度位於高度Hb處，高度Hb小於分離插塞的高度Ha之3/4。
根據本揭露之另一方面，一種製造半導體裝置之方法包括：形成虛設電極結構，虛設電極結構包括虛設電極層及設置於虛設電極層之兩側的層間介電層。圖案化虛設電極層，以將虛設電極層分成藉由開口分隔之至少第一虛設電極與第二虛設電極。藉由以絕緣材料填充開口而形成分離插塞。去除第一虛設電極與第二虛設電極以形成第一電極空間與第二電極空間，分離插塞暴露在第一電極空間與第二電極空間之間。蝕刻暴露出的分離插塞，以使在橫穿第一電極空間、第二電極空間及分離插塞之剖面中，分離插塞的最大寬度位於高度Hb處，高度Hb小於分離插塞的高度Ha之3/4。分別於第一電極空間與第二電極空間中形成第一閘極結構與第二閘極結構。
根據本揭露之更另一方面，一種製造半導體裝置之方法包括：形成虛設電極結構，虛設電極結構包括虛設電極層、及設置於虛設電極層之兩側的層間介電層。圖案化虛設電極層，以將虛設電極層分成藉由開口分隔之至少第一虛設電極與第二虛設電極。藉由以絕緣材料填充開口而形成分離插塞。去除第一虛設電極與第二虛設電極，以形成 第一電極空間與第二電極空間，分離插塞暴露於第一電極空間與第二電極空間之間。分別於第一電極空間與第二電極空間中形成第一閘極結構與第二閘極結構。在形成分離插塞前。開口具有錐形形狀，該錐形形狀具有小於開口的底部尺寸(寬度)之開口的頂部尺寸(寬度)。
以上內容概述若干實施例的特徵，因而所屬技術領域中通常知識者可更為理解本申請案揭示內容之各方面。所屬技術領域中具有通常知識者應理解可輕易使用本申請案揭示內容作為基礎，用於設計或修改其他製程與結構而與本文所述之實施例具有相同目的及/或達到相同優點。所屬技術領域中具有通常知識者亦應理解此均等架構並未脫離本揭露之精神與範圍，且在不脫離本揭露之精神與範圍的情況下，所屬技術領域中具有通常知識者可進行各種變化、取代與替換。
1‧‧‧FinFET(Fin Field-Effect，鰭式場效)裝置
1A‧‧‧第一裝置區
1B‧‧‧第二裝置區
10‧‧‧基板
20、20A、20B‧‧‧鰭結構
30‧‧‧閘極介電層
40‧‧‧閘極電極
42‧‧‧功函數調整層
45‧‧‧金屬閘極層
50‧‧‧隔離絕緣層
60‧‧‧分離插塞
70‧‧‧層間介電層
80‧‧‧側壁絕緣層

Claims (10)

  1. 一種半導體裝置，包含：第一FinFET(Fin Field-Effect，鰭式場效)電晶體，包括在第一方向延伸之第一鰭結構、形成於該第一鰭結構上方之第一閘極介電質、及形成於該第一閘極介電質上方且在與該第一方向垂直的第二方向延伸之第一閘極電極；第二FinFET電晶體，包括第二鰭結構、形成於該第二鰭結構上方之第二閘極介電質、及形成於該第二閘極介電質上方且在該第二方向延伸之第二閘極電極；以及分離插塞，由絕緣材料製成且設置於該第一FinFET電晶體與該第二FinFET電晶體之間；其中，在沿著該第二方向且橫穿該第一閘極電極、該第二閘極電極及該分離插塞之剖面中，該分離插塞的最大寬度位於高度Hb處，該高度Hb小於該分離插塞的高度Ha之3/4。
  2. 如申請專利範圍第1項之半導體裝置，其中，於該剖面中，該分離插塞具有錐形形狀，該錐形形狀之頂部寬度小於底部寬度。
  3. 如申請專利範圍第2項之半導體裝置，其中，該分離插塞之底部處的該分離插塞之錐角為90度以上。
  4. 如申請專利範圍第1項之半導體裝置，其中：該第一閘極電極包括一層或複數層第一功函數調整金屬、及第一金屬閘極材料；該第二閘極電極包括一層或複數層第二功函數調整金屬、及第二金屬閘極材料。
  5. 如申請專利範圍第1項之半導體裝置，其中，該第一FinFET電晶 體與該第二FinFET電晶體具有相同通道型。
  6. 如申請專利範圍第1項之半導體裝置，其中，該第一FinFET電晶體之通道型與該第二FinFET電晶體之通道型不同。
  7. 如申請專利範圍第1項之半導體裝置，其中，該第一FinFET電晶體包括兩個以上之該第一鰭結構。
  8. 一種製造半導體裝置之方法，包含：形成虛設電極結構，該虛設電極結構包括虛設電極層、及設置於該虛設電極層之兩側的層間介電層；圖案化該虛設電極層，以將該虛設電極層分成藉由開口分隔之至少第一虛設電極與第二虛設電極；藉由以絕緣材料填充該開口而形成分離插塞；去除該第一虛設電極與該第二虛設電極以形成第一電極空間與第二電極空間，該分離插塞暴露於該第一電極空間與該第二電極空間之間；蝕刻該暴露出的分離插塞；以及分別於該第一電極空間與該第二電極空間中形成第一閘極結構與第二閘極結構；其中，於蝕刻該暴露出的分離插塞後，在橫穿該第一電極空間、該第二電極空間及該分離插塞之剖面中，該分離插塞的最大寬度位於高度Hb處，該高度Hb小於該分離插塞的高度Ha之3/4。
  9. 如申請專利範圍第8項之製造半導體裝置之方法，其中，於蝕刻該暴露出的分離插塞後，在該剖面中，該分離插塞具有錐形形狀，該錐形形狀之頂部寬度小於底部寬度。
  10. 一種製造半導體裝置之方法，包含：形成虛設電極結構，該虛設電極結構包括虛設電極層、及設置於該虛設電極層之兩側的層間介電層； 圖案化該虛設電極層，以將該虛設電極層分成藉由開口分隔之至少第一虛設電極與第二虛設電極；藉由以絕緣材料填充該開口而形成分離插塞；去除該第一虛設電極與該第二虛設電極以形成第一電極空間與第二電極空間，該分離插塞暴露於該第一電極空間與該第二電極空間之間；以及分別於該第一電極空間與該第二電極空間中形成第一閘極結構與第二閘極結構；其中，在形成該分離插塞前，該開口具有錐形形狀，該錐形形狀之該開口的頂部寬度小於該開口的底部寬度。
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