CN110718582A - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
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- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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Abstract
一种半导体结构及其形成方法,其中,形成方法包括:提供基底,所述基底表面具有相邻的鳍部;分别形成横跨鳍部的伪栅结构,伪栅结构之间具有初始第一隔离结构,所述初始第一隔离结构的两侧分别与伪栅结构相接触;在所述基底顶部、鳍部的侧壁和顶部表面、伪栅结构的侧壁、以及初始第一隔离结构的侧壁形成第一介质层;去除伪栅结构,在第一介质层内形成伪栅开口;形成所述伪栅开口之后,沿鳍部宽度方向上去除部分初始第一隔离结构,形成第一隔离结构;形成所述第一隔离结构之后,在所述伪栅开口内形成栅极结构。所述方法形成的器件性能较好。
Description
技术领域
本发明涉及半导体制造领域,尤其是涉及一种半导体结构及其形成方法。
背景技术
随着半导体制造技术的飞速发展,半导体器件朝着更高的元件密度,以及更高的集成度的方向发展。器件作为最基本的半导体器件,目前正被广泛应用,传统的平面器件对沟道电流的控制能力变弱,产生短沟道效应而导致漏电流,最终影响半导体器件的电学性能。
为了克服器件的短沟道效应,抑制漏电流,现有技术提出了鳍式场效应晶体管(Fin FET),鳍式场效应晶体管是一种常见的多栅器件,鳍式场效应晶体管的结构包括:位于半导体衬底表面的鳍部和隔离层,所述隔离层覆盖部分所述鳍部的侧壁,且隔离层表面低于鳍部顶部;位于隔离层表面,以及鳍部的顶部和侧壁表面的栅极结构;位于所述栅极结构两侧的鳍部内的源区和漏区。
然而,现有技术形成的半导体器件的性能较差。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法,以提高半导体结构的性能。
为解决上述技术问题,本发明提供一种半导体结构的形成方法,包括:提供基底,所述基底表面具有相邻的鳍部;分别形成横跨鳍部的伪栅结构,所述伪栅结构之间具有初始第一隔离结构,所述初始第一隔离结构的两侧分别与伪栅结构相接触;在所述基底顶部、鳍部的侧壁和顶部表面、伪栅结构的侧壁、以及初始第一隔离结构的侧壁形成第一介质层;去除所述伪栅结构,在所述第一介质层内形成伪栅开口;形成所述伪栅开口之后,沿鳍部宽度方向上去除部分初始第一隔离结构,形成第一隔离结构;形成所述第一隔离结构之后,在所述伪栅开口内形成栅极结构。
可选的,所述伪栅结构和初始第一隔离结构的形成方法包括:在所述基底顶部、以及鳍部的侧壁和顶部表面形成伪栅结构膜;对所述伪栅结构膜进行第一次图形化工艺,在相邻鳍部之间形成开口;在所述开口内形成初始第一隔离结构;形成初始第一隔离结构之后,对所述伪栅结构膜进行第二次图形化工艺,形成所述伪栅结构。
可选的,形成所述伪栅结构膜之前,还包括:在所述基底表面形成第二隔离结构,所述第二隔离结构的顶部低于鳍部的顶部表面,且覆盖鳍部的部分侧壁。
可选的,所述伪栅结构包括伪栅介质层;所述伪栅介质层的材料包括氧化硅。
可选的,所述初始第一隔离结构的材料与伪栅介质层的材料不同。
可选的,所述初始第一隔离结构的材料包括碳化硅、氮氧化硅、氮化硅或者碳氧化硅。
可选的,所述第一隔离结构侧壁和底部的夹角为60度~90度;沿鳍部的宽度方向上,所述第一隔离结构顶部尺寸小于底部尺寸。
可选的,沿鳍部的宽度方向上,所述第一隔离结构顶部的尺寸为:30纳米~50纳米;沿鳍部的宽度方向上,所述第一隔离结构底部的尺寸为:70纳米~90纳米。
可选的,所述鳍部侧壁到第一隔离结构侧壁的最小距离为:20纳米~40纳米。
可选的,形成所述伪栅结构之后,形成第一介质层之前,还包括:在所述伪栅结构两侧的鳍部内分别形成源漏掺杂区。
可选的,形成所述栅极结构之后,还包括:在所述第一介质层、第一隔离结构顶部、以及栅极结构顶部形成第二介质层;去除所述源漏掺杂区顶部的第二介质层和第一介质层,直至暴露出源漏掺杂区的顶部表面,在所述第一介质层和第二介质层内形成第一接触孔;去除栅极结构顶部的第二介质层,在所述第二介质层内形成第二接触孔;在所述第一接触孔内形成第一插塞;在所述第二接触孔内形成第二插塞。
相应的,本发明还提供一种半导体结构,包括:基底,所述基底表面具有相邻的鳍部;位于基底顶部的第一介质层,所述第一介质层内具有第一隔离结构,所述第一隔离结构的顶部尺寸小于底部尺寸,所述第一隔离结构两侧的第一介质层内分别具有伪栅开口,且所述伪栅开口暴露出第一隔离结构的侧壁;位于所述伪栅开口内的栅极结构。
可选的,所述第一隔离结构侧壁和底部的夹角为60度~90度;沿鳍部的宽度方向上,所述第一隔离结构顶部尺寸小于底部尺寸。
可选的,所述第一隔离结构顶部的尺寸为:30纳米~50纳米;所述第一隔离结构底部的尺寸为:70纳米~90纳米。
可选的,所述第一隔离结构的材料包括碳化硅、氮氧化硅、氮化硅或者碳氧化硅。
可选的,所述鳍部侧壁到第一隔离结构侧壁的最小距离为:20纳米~40纳米。
可选的,所述半导体结构还包括:位于栅极结构两侧鳍部内的源漏掺杂区;位于第一介质层、第一隔离结构和栅极结构顶部的第二介质层;位于所述源漏掺杂区顶部第一介质层和第二介质层内的第一接触孔,所述第一接触孔底部暴露出源漏掺杂区的顶部表面;位于所述栅极结构顶部第二介质层内的第二接触孔,所述第二接触孔底部暴露出栅极结构的顶部表面;位于第一接触孔内的第一插塞;位于第二接触孔内的第二插塞。
与现有技术相比,本发明实施例的技术方案具有以下有益效果:
本发明技术方案提供的半导体结构的形成方法中,形成所述伪栅开口之后,沿鳍部宽度方向上去除部分初始第一隔离结构,形成第一隔离结构,使所述第一隔离结构沿鳍部宽度方向上的尺寸较小,即所述鳍部与第一隔离结构侧壁构成的沟槽沿鳍部宽度方向上尺寸增大,则后续在所述沟槽内填充栅极结构的难度较低,使得在所述沟槽内所形成的栅极结构内不易产生空洞,则栅极结构对鳍部的控制能力较强,有利于提高半导体器件的性能。
进一步,沿鳍部宽度方向上,所述第一隔离结构顶部尺寸小于底部尺寸,则后续栅极结构时,所述栅极结构的材料沿第一隔离结构的侧壁滑落至沟槽内,能够更好地填充所述沟槽的拐角处,有利于防止沟槽拐角处的栅极结构内产生空洞。
附图说明
图1至图4是一种半导体结构的形成方法各步骤的结构示意图;
图5至图15是本发明一实施例半导体结构的形成方法各步骤的结构示意图。
具体实施方式
正如背景技术所述,半导体器件的性能较差。
图1至图4是一种半导体结构的形成方法各步骤的结构示意图。
请参考图1和图2,图1是图2沿X方向上的俯视图,图2是图1沿A-A1线的剖面示意图,提供基底100,所述基底100表面具有相邻的鳍部101;分别形成横跨鳍部101的伪栅结构102,所述相邻鳍部101的伪栅结构102之间具有开口103。
请参考图3,在所述基底100顶部、鳍部101的侧壁和顶部表面、伪栅结构102的侧壁、以及开口103内形成第一介质层104。
请参考图4,形成所述第一介质层104之后,去除所述伪栅结构102(见图3),在所述第一介质层104内形成伪栅开口(图中未标出);在所述伪栅开口内形成栅极结构105。
上述方法中,随着半导体集成度的不断提高,要求所述伪栅结构102的尺寸越来越小,小尺寸的所述伪栅结构102的形成方法包括:在所述基底100表面、以及鳍部101的侧壁和顶部表面形成伪栅结构膜;图形化所述伪栅结构膜,形成横跨鳍部101的初始伪栅结构;去除相邻鳍部101之间的所述初始伪栅结构,形成所述伪栅结构102。在去除相邻鳍部101之间所述初始伪栅结构的过程中,还包括:在相邻鳍部101之间形成开口103。
然而,受实际图形化工艺的限制,使得开口103沿鳍部101宽度方向上的尺寸难以做小。而相邻鳍部101之间的距离随着集成度的提高不断减小,则鳍部101与位于开口103内第一介质层104构成的沟槽1沿鳍部101宽度方向上的尺寸较小,则在所述沟槽1内填充栅极结构105较困难,则在所述沟槽1内形成的栅极结构105内易产生空洞,使得栅极结构105对鳍部101的控制作用较差,不利于提高半导体器件的性能。
为解决所述技术问题,本发明提供了一种半导体结构的形成方法,形成伪栅开口之后,沿鳍部宽度方向上去除部分初始第一隔离结构,形成第一隔离结构,使得鳍部与第一隔离结构构成的沟槽沿鳍部宽度方向上的尺寸增大,因此,有利于降低后续在所述沟槽内形成栅极结构的难度,所形成的栅极结构内不易产生空洞,则所述栅极结构对鳍部的控制能力较强。
为使本发明的上述目的、特征和有益效果能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图5至图15是本发明一实施例半导体结构的形成方法各步骤的结构示意图。
提供基底,所述基底表面具有相邻的鳍部;分别形成横跨鳍部的伪栅结构,所述伪栅结构之间具有初始第一隔离结构,所述初始第一隔离结构的两侧分别与伪栅结构相接触。所述伪栅结构和初始第一隔离结构的形成步骤具体请参考图5至图9。
请参考图5,提供基底200,所述基底200表面具有相邻的鳍部201;在基底200顶部、以及鳍部201的侧壁和顶部表面形成伪栅结构膜202;对所述伪栅结构膜202进行第一次图形化工艺,直至暴露出基底200的顶部表面,在相邻鳍部201之间形成开口203。
在本实施例中,所述基底200和鳍部201的形成步骤包括:提供初始衬底,所述初始衬底上具有第一掩膜层(图中未示出),所述第一掩膜层暴露出部分初始衬底的顶部表面;以所述第一掩膜层为掩膜,刻蚀所述初始衬底,形成基底200和位于基底200上的鳍部201。
在本实施例中,所述初始衬底的材料为硅,相应的,所述基底200和鳍部201的材料为硅。
在其他实施例中,所述初始衬底的材料包括:锗、硅锗、绝缘体上硅或绝缘体上锗,相应的,所述基底和第一鳍部的材料包括:锗、硅锗、绝缘体上硅或绝缘体上锗。
所述第一掩膜层的材料包括:氮化硅或者氮氧化硅。所述第一掩膜层用于形成基底200和鳍部201的掩膜。
所述基底200表面还具有第二隔离结构(图中未标出),所述第二隔离结构覆盖鳍部201的部分侧壁,且所述第二隔离结构的顶部表面低于鳍部201的顶部表面。
所述第二隔离结构的材料包括氧化硅或者氮氧化硅。所述第二隔离结构用于实现半导体不同器件之间的电隔离。
所述伪栅结构膜202包括:伪栅介质层(图中未示出)和位于伪栅介质层顶部的伪栅极层。
所述伪栅介质层的材料包括氧化硅,所述伪栅极层的材料包括硅。
所述第一次图形化工艺包括:在所述伪栅结构膜202顶部形成第二掩膜层(图中未示出),所述第二掩膜层暴露出相邻鳍部201之间的伪栅结构膜202;以所述第二掩膜层为掩膜,刻蚀所述伪栅结构膜202,直至暴露出第二隔离结构的顶部表面,在相邻鳍部201之间形成开口203。
所述第二掩膜层的材料包括氮化硅或者氮化钛。所述第二掩膜层用于作为形成开口203的掩膜。
以所述第二掩膜层为掩膜,刻蚀所述伪栅结构膜202的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
所述开口203受实际工艺限制,使得所述开口203沿鳍部201的宽度方向上的尺寸难以做小,具体的,所述开口203沿鳍部201的宽度方向上的尺寸为:30纳米~60纳米。
所述开口203用于后续容纳初始第一隔离结构。
请参考图6,在所述开口203(见图5)内形成初始第一隔离结构204,所述初始第一隔离结构204充满开口203。
所述初始第一隔离结构204的形成方法包括:在所述开口203内和伪栅结构膜202顶部形成第一隔离材料膜;去除部分所述第一隔离材料膜,直至暴露出伪栅结构膜202的顶部表面,在所述开口203内形成所述初始第一隔离结构204。
所述第一隔离材料膜的材料包括:碳化硅、氮氧化硅、氮化硅或者碳氧化硅。所述第一隔离材料膜的材料与栅介质膜的材料不同,则后续去除所述栅介质膜时,所述第一隔离材料膜不被去除。
所述第一隔离材料膜的形成工艺包括化学气相沉积工艺或者物理气相沉积工艺。
去除部分所述第一隔离材料膜的工艺包括:化学气相沉积工艺、干法刻蚀工艺和湿法刻蚀工艺中的一种或者几种组合。
所述初始第一隔离结构204用于后续形成第一隔离结构。
请参考图7至图9,图8是图7沿A-A1线的剖面示意图,图9是图7沿B-B1线的剖面示意图,图7是图8和图9沿Y方向上的俯视图,形成所述初始第一隔离结构204之后,对所述伪栅结构膜202进行第二次图形化工艺,分别形成横跨鳍部201的伪栅结构205,且所述伪栅结构205与初始第一隔离结构204接触。
所述第二次图形化工艺包括:在所述伪栅结构膜202顶部形成第三掩膜层(图中未示出),所述第三掩膜层覆盖初始第一隔离结构204沿鳍部201宽度方向上两侧的部分伪栅结构膜202;以所述第三掩膜层为掩膜,刻蚀所述伪栅结构膜202,直至暴露出第二隔离结构的顶部表面,形成所述伪栅结构205。
所述第三掩膜层的材料包括氮化硅或者氮化钛,所述第三掩膜层用于形成伪栅结构205的掩膜。
以所述第三掩膜层为掩膜,刻蚀所述伪栅结构膜202的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
通过第一次图形化工艺和第二次图形化工艺,形成的所述伪栅结构205的尺寸较小,有利于提高半导体器件的集成度。
请参考图10,在所述伪栅结构205两侧的鳍部201内形成源漏掺杂区206。
需要说明的是,图10与图9的剖面方向一致。
形成所述源漏掺杂区206之前,所述形成方法还包括:在所述伪栅结构205侧壁形成侧墙(图中未示出)。所述侧墙用于定义源漏掺杂区206的位置。
所述侧墙的材料包括氮化硅。
所述源漏掺杂区206的形成方法包括:在所述伪栅结构205和侧墙两侧的鳍部201内形成源漏开口;在所述源漏开口内形成外延层;在所述外延层内掺入掺杂离子,形成所述源漏掺杂区206。
所述外延层的材料和掺杂离子的导电类型与待形成的晶体管的类型相关。具体的,当待形成的晶体管为NMOS晶体管时,所述外延层的材料包括碳化硅或者硅,所述掺杂离子为N型离子,如:磷离子或者砷离子;当待形成的晶体管为PMOS晶体管时,所述外延层的材料包括硅锗或者硅,所述掺杂离子为P型离子,如:硼离子。
形成所述源漏掺杂区206之后,所述形成方法还包括:在所述源漏掺杂区206顶部形成停止层(图中未标出)。所述停止层的材料包括氮化硅或者氮化钛,所述停止层用于后续在源漏掺杂区206顶部形成插塞时作为停止层,有利于保护源漏掺杂区206的顶部表面。
请参考图11和图12,在所述停止层顶部形成初始第一介质层207,所述第一介质层207暴露出伪栅结构205的顶部表面。
需要说明的是,图11与图10的剖面方向一致,图12与图8的剖面方向一致。
所述第一介质层207的形成方法包括:在所述停止层顶部形成介质材料膜;去除部分介质材料膜,直至暴露出伪栅结构205的顶部表面,形成所述第一介质层207。
在本实施例中,所述介质材料膜的材料包括氧化硅或者氮氧化硅。
所述第一介质层207材料的隔离性能较好,有利于提高半导体器件的性能。
请参考图13,去除所述伪栅极层,在所述第一介质层207内形成伪栅开口208;形成所述伪栅开口208之后,沿鳍部201的宽度方向上去除部分初始第一隔离结构204,形成第一隔离结构209。
需要说明的是,图13与图12的剖面方向一致。
去除所述伪栅极层的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
所述伪栅开口208用于后续容纳栅极结构。
沿鳍部201的宽度方向上去除部分初始第一隔离结构204的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
沿鳍部201的宽度方向上去除部分初始第一隔离结构204,使得所形成的第一隔离结构209沿鳍部201的宽度方向上的尺寸较小,则所述鳍部201与第一隔离结构209沟槽的沟槽沿鳍部201宽度方向上的尺寸较大,使得后续在沟槽内形成栅极结构的难度较低,则位于所述沟槽内的栅极结构内不易产生空洞,则所述栅极结构对鳍部201的控制能力较强,有利于提高半导体器件的性能。
本实施例中,所述第一隔离结构209侧壁和底部的夹角为60度~90度;沿鳍部201宽度方向上,所述第一隔离结构209的顶部尺寸小于底部尺寸。具体的,沿鳍部201宽度方向上,所述第一隔离结构209顶部的尺寸为:30纳米~50纳米;沿鳍部201宽度方向上,所述第一隔离结构209底部的尺寸为:70纳米~90纳米。
在其他实施例中,所述第一隔离结构的侧壁和底部垂直。
在本实施例中,沿鳍部201的宽度方向上,所述第一隔离结构209顶部尺寸小于底部尺寸,使得后续形成栅极结构时,所述栅极结构的材料沿第一隔离结构209侧壁滑落至沟槽内,能够更好地填充所述沟槽的拐角处,有利于防止沟槽拐角处的栅极结构内产生空洞,则所述栅极结构对鳍部201的控制能力更强,有利于进一步提高半导体器件的性能。
请参考图14和图15,形成所述第一隔离结构209之后,在所述伪栅开口208(见图13)内形成栅极结构210。
需要说明的是,图14与图13的剖面方向一致,图15与图11的剖面方向一致。
形成所述栅极结构210之前,所述形成方法还包括:去除伪栅开口208底部的伪栅介质层。
去除伪栅开口208底部的伪栅介质层的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
由于第一隔离结构209沿鳍部201宽度方向上的尺寸较小,使得鳍部201与第一隔离结构209构成的沟槽沿鳍部201的宽度方向上的尺寸较大,则在所述沟槽内形成栅极结构210的难度较低,使得所述沟槽内的栅极结构210内不易产生空洞,则所述栅极结构210对鳍部201的控制能力较强,有利于提高半导体器件的性能。
并且,所述第一隔离结构209顶部尺寸小于底部尺寸,则所述栅极结构210的材料沿第一隔离结构209侧壁滑落至沟槽内,能够更好地填充所述沟槽的拐角处,有利于防止沟槽拐角处的栅极结构210内产生空洞,则栅极结构210对鳍部201的控制作用更强,有利于进一步提高半导体器件的性能。
所述栅极结构210包括栅介质层(图中未示出)和位于栅介质层顶部的栅极层。
所述栅介质层的材料为高K介质材料,所述栅介质层的材料包括:HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3或HfSiO4。
所述栅极层的材料为金属,所述栅极层包括:Al、Cu、Ag、Au、Ni、Ti、W、WN或WSi。
形成所述栅极结构210之后,所述形成方法还包括:去除部分栅极层;在所述栅极层和第一介质层207顶部形成保护层(图中未标出)。
所述保护层用于后续在栅极结构210顶部的第二介质层内形成第二接触孔时作为停止层。
所述保护层的材料包括氮化硅。
尽管在形成第一隔离结构209的过程中,部分初始第一隔离结构204被去除,使得所形成的第一隔离结构209的高度可能被降低,但是,由于部分栅极结构210也被去除,使得栅极结构210和第一隔离结构209顶部的平坦度良好。后续在栅极结构210和第一介质层207顶部形成保护层,所述保护层顶部较平坦,有利于提高半导体器件的性能。
形成所述保护层之后,所述形成方法还包括:在所述第一介质层207、第一隔离结构209和保护层顶部形成第二介质层;去除所述源漏掺杂区206顶部的第一介质层207和第二介质层,直至暴露出源漏掺杂区206的顶部表面,在所述第一介质层207和第二介质层内形成第一接触孔;去除栅极结构210顶部的第二介质层和保护层,直至暴露出栅极结构210的顶部表面,在所述第二介质层和保护层内形成第二接触孔;在所述第一接触孔内形成第一插塞;在所述第二接触孔内形成第二插塞。
随着半导体集成度的提高,器件的尺寸不断减小。在形成第一接触孔的过程中,即使第一接触孔偏移到栅极结构210上,但是,由于栅极结构210顶部具有保护层,所述保护层能够对栅极结构210顶部进行保护,使得栅极结构210不被破坏,有利于提高半导体器件的性能。
相应的,本发明还提供一种半导体结构,请参考图14,包括:
基底200,所述基底200表面具有相邻的鳍部201;
位于基底200顶部的第一介质层207(见图11),所述第一介质层207具有第一隔离结构209,所述第一隔离结构209沿鳍部201宽度方向上顶部尺寸小于底部尺寸,所述第一隔离结构209两侧的第一介质层207内分别具有伪栅开口208(见图13),且所述伪栅开口208暴露出第一隔离结构209的侧壁;位于所述伪栅开口208内的栅极结构210。
所述第一隔离结构209侧壁和底部的夹角为60度~90度;沿鳍部201的宽度方向上,所述第一隔离结构209顶部尺寸小于底部尺寸。
沿鳍部201的宽度方向上,所述第一隔离结构209顶部的尺寸为:30纳米~50纳米;沿鳍部201的宽度方向上,所述第一隔离结构209底部的尺寸为:70纳米~90纳米。
所述第一隔离结构209的材料包括:碳化硅、氮氧化硅、氮化硅或者碳氧化硅。
所述鳍部201侧壁到第一隔离结构209侧壁的最小距离为:20纳米~40纳米。
所述半导体结构还包括:位于基底200表面的第二隔离结构(图中未标出),所述第二隔离结构顶部低于鳍部201的顶部表面,且所述第二隔离结构覆盖鳍部201的部分侧壁;位于栅极结构210两侧鳍部201内的源漏掺杂区206(见图8);位于第一介质层207、第一隔离结构209和栅极结构210顶部的第二介质层;位于所述源漏掺杂区206顶部第一介质层207和第二介质层内的第一接触孔,所述第一接触孔底部暴露出源漏掺杂区206的顶部表面;位于所述栅极结构210顶部第二介质层内的第二接触孔,所述第二接触孔底部暴露出栅极结构210的顶部表面;位于第一接触孔内的第一插塞;位于第二接触孔内的第二插塞。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (17)
1.一种半导体结构的形成方法,其特征在于,包括:
提供基底,所述基底表面具有相邻的鳍部;
分别形成横跨鳍部的伪栅结构,所述伪栅结构之间具有初始第一隔离结构,所述初始第一隔离结构的两侧分别与伪栅结构相接触;
在所述基底顶部、鳍部的侧壁和顶部表面、伪栅结构的侧壁、以及初始第一隔离结构的侧壁形成第一介质层;
去除所述伪栅结构,在所述第一介质层内形成伪栅开口;
形成所述伪栅开口之后,沿鳍部宽度方向上去除部分初始第一隔离结构,形成第一隔离结构;
形成所述第一隔离结构之后,在所述伪栅开口内形成栅极结构。
2.如权利要求1所述的半导体结构的形成方法,其特征在于,所述伪栅结构和初始第一隔离结构的形成方法包括:在所述基底顶部、以及鳍部的侧壁和顶部表面形成伪栅结构膜;对所述伪栅结构膜进行第一次图形化工艺,直至暴露出基底的顶部表面,在相邻鳍部之间形成开口;在所述开口内形成初始第一隔离结构;形成初始第一隔离结构之后,对所述伪栅结构膜进行第二次图形化工艺,形成所述伪栅结构。
3.如权利要求2所述的半导体结构的形成方法,其特征在于,形成所述伪栅结构膜之前,还包括:在所述基底表面形成第二隔离结构,所述第二隔离结构的顶部低于鳍部的顶部表面,且覆盖鳍部的部分侧壁。
4.如权利要求1所述的半导体结构的形成方法,其特征在于,所述伪栅结构包括伪栅介质层;所述伪栅介质层的材料包括氧化硅。
5.如权利要求4所述的半导体结构的形成方法,其特征在于,所述初始第一隔离结构的材料与伪栅介质层的材料不同。
6.如权利要求5所述的半导体结构的形成方法,其特征在于,所述初始第一隔离结构的材料包括碳化硅、氮氧化硅、氮化硅或者碳氧化硅。
7.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一隔离结构侧壁和底部的夹角为60度~90度;沿鳍部的宽度方向上,所述第一隔离结构顶部尺寸小于底部尺寸。
8.如权利要求7所述的半导体结构的形成方法,其特征在于,沿鳍部宽度方向上,所述第一隔离结构顶部的尺寸为:30纳米~50纳米;沿鳍部宽度方向上,所述第一隔离结构底部的尺寸为:70纳米~90纳米。
9.如权利要求1所述的半导体结构的形成方法,其特征在于,所述鳍部侧壁到第一隔离结构侧壁的最小距离为:20纳米~40纳米。
10.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述伪栅结构之后,形成第一介质层之前,还包括:在所述伪栅结构两侧的鳍部内分别形成源漏掺杂区。
11.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述栅极结构之后,还包括:在所述第一介质层、第一隔离结构顶部、以及栅极结构顶部形成第二介质层;去除所述源漏掺杂区顶部的第二介质层和第一介质层,直至暴露出源漏掺杂区的顶部表面,在所述第一介质层和第二介质层内形成第一接触孔;去除栅极结构顶部的第二介质层,在所述第二介质层内形成第二接触孔;在所述第一接触孔内形成第一插塞;在所述第二接触孔内形成第二插塞。
12.一种半导体结构,其特征在于,包括:
基底,所述基底表面具有相邻的鳍部;
位于基底顶部的第一介质层,所述第一介质层内具有第一隔离结构,所述第一隔离结构的顶部尺寸小于底部尺寸,所述第一隔离结构两侧的第一介质层内分别具有伪栅开口,且所述伪栅开口暴露出第一隔离结构的侧壁;
位于所述伪栅开口内的栅极结构。
13.如权利要求12所述的半导体结构,其特征在于,所述第一隔离结构侧壁和底部的夹角为60度~90度;沿鳍部的宽度方向上,所述第一隔离结构顶部尺寸小于底部尺寸。
14.如权利要求13所述的半导体结构,其特征在于,沿鳍部宽度方向上,所述第一隔离结构顶部的尺寸为:30纳米~50纳米;沿鳍部宽度方向上,所述第一隔离结构底部的尺寸为:70纳米~90纳米。
15.如权利要求12所述的半导体结构,其特征在于,所述第一隔离结构的材料包括碳化硅、氮氧化硅、氮化硅或者碳氧化硅。
16.如权利要求12所述的半导体结构,其特征在于,所述鳍部侧壁到第一隔离结构侧壁的最小距离为:20纳米~40纳米。
17.如权利要求12所述的半导体结构,其特征在于,所述半导体结构还包括:位于基底表面的第二隔离结构,所述第二隔离结构顶部低于鳍部的顶部表面,且所述第二隔离结构覆盖鳍部的部分侧壁;位于栅极结构两侧鳍部内的源漏掺杂区;位于第一介质层、第一隔离结构顶部、以及栅极结构顶部的第二介质层;位于所述源漏掺杂区顶部第一介质层和第二介质层内的第一接触孔,所述第一接触孔底部暴露出源漏掺杂区的顶部表面;位于所述栅极结构顶部第二介质层内的第二接触孔,所述第二接触孔底部暴露出栅极结构的顶部表面;位于第一接触孔内的第一插塞;位于第二接触孔内的第二插塞。
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