CN113823690A - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
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Abstract
一种半导体器件及其形成方法,其中半导体器件包括:基底;栅极结构,位于所述基底上,包括第一区和第二区,所述第一区的栅极结构的长度大于所述第二区的栅极结构长度;停止层,位于所述基底上且位于所述第一区的栅极结构内;在栅极结构的形成中,由于停止层的存在,停止层作为栅极结构形成过程中的停止标记,可以减少栅极结构损耗,保证了形成的栅极结构的质量得到提高,从而保证最终形成的半导体器件的质量得到提高。
Description
技术领域
本发明涉及半导体制造技术领域,尤其涉及一种半导体器件及其形成方法。
背景技术
电子工业不断地朝着更小和更快的电子器件需求发展,更小和更快的电子器件能够同时支持更多数量且越来越复杂的尖端功能。因此,半导体工业的持续趋势是制造低成本、高性能和低功率的集成电路(IC)。到目前为止,已经通过按比例缩小半导体IC尺寸(例如,最小特征尺寸(CD))从而提高生产效率以及降低相关成本,在很大程度上实现了这些目标。然而,这种按比例缩小也使半导体制造工艺的复杂度增加。因此,半导体IC和器件的持续进步需要半导体制造工艺和技术的同步进步。
栅极结构作为器件的一部分,其材料极大地影响了器件的性能。传统的多晶硅栅极工艺由于存在“多晶硅耗尽”效应,影响器件导通,所以引入了金属栅极,引入金属栅极之后,需要在金属栅极上形成互连金属层与外界形成电连接。
但是现有技术中形成栅极结构质量有待进一步提高。
发明内容
本发明解决的技术问题是提供一种半导体器件及其形成方法,使得栅极结构的形成质量得到提高,从而保证最终形成的半导体器件的质量得到提高。
为解决上述问题,本发明提供一种半导体器件,基底;栅极结构,位于所述基底上,包括第一区和第二区,所述第一区的栅极结构的长度大于所述第二区的栅极结构长度;停止层,位于所述基底上且位于所述第一区的栅极结构内。
可选的,所述停止层的数量为一个或者多个。
可选的,所述停止层的材料为氮化硅、氧化硅、氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅、碳氮硼化硅中的一种或多种组合。
相应的,本发明还提供一种半导体器件的形成方法:包括:提供基底,在所述基底上形成伪栅极结构,所述伪栅极结构包括第一区和第二区,所述第一区的伪栅极结构长度大于所述第二区的栅极结构长度;刻蚀所述第一区的部分伪栅极结构,在所述第一区的伪栅极结构内形成开口,所述开口的底部暴露出所述基底的表面;在所述开口内形成停止层,所述停止层填充满所述开口;去除所述伪栅极结构,在所述基底上形成栅极开口,在所述栅极开口内形成初始栅极结构;对所述初始栅极结构进行平坦化,至暴露出所述停止层的顶部表面,形成栅极结构。
可选的,所述开口的数量与所述停止层的数量相等。
可选的,所述开口的数量为一个,所述停止层的数量为一个或者所述开口的数量为多个,所述停止层的数量为多个。
可选的,所述停止层的材料为氮化硅、氧化硅、氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅、碳氮硼化硅中的一种或多种组合。
可选的,形成所述停止层的工艺为化学气相沉积工艺、原子层沉积工艺或者物理气相沉积工艺中的一种或者多种组合。
可选的,形成所述停止层的方法为:在所述伪栅极结构的顶部表面形成初始停止层;对所述初始停止层进行平坦化,至暴露出所述伪栅极结构的顶部表面。
可选的,所述栅极结构包括形成在所述基底上的栅介质层、形成所述栅介质层上的功函数层以及形成在所述功函数层上的金属层。
与现有技术相比,本发明的技术方案具有以下优点:
在本发明的结构中,由于停止层的存在,一方面停止层将第一区的栅极结构进行分割,实现第一区的栅极结构的切断(gate cut);另外一方面,在栅极结构的形成过程中,所述停止层作为所述栅极结构在形成过程中的停止标记,这样可以避免栅极结构在形成的过程中损失过多,从而提高栅极结构的形成质量。
在基底上形成伪栅极结构,伪栅极结构包括第一区和第二区,其中第一区的伪栅极结构长度大于第二区的栅极结构长度,通过刻蚀第一区的部分伪栅极结构,在第一区的伪栅极结构内形成开口,开口的底部暴露出基底的表面,在开口内形成停止层,停止层填充满开口,去除伪栅极结构,形成栅极开口,在栅极开口内形成初始栅极结构,平坦化初始栅极结构至暴露出停止层的顶部表面,从而形成栅极结构,这种方法形成的栅极结构质量好,能够保证最终形成的半导体器件的质量高,这是因为在平坦化初始栅极结构的过程中,由于停止层的存在,当平坦化的过程中暴露出停止层的顶部表面时,平坦化的过程就不能再继续进行,这就减少了栅极结构损耗,保证了形成的栅极结构的质量得到提高,从而保证最终形成的半导体器件的质量得到提高。
附图说明
图1至图12是一种半导体器件形成过程中各步骤的结构示意图;
图13至图27是本发明半导体器件及其形成方法一实施例各步骤结构示意图。
具体实施方式
现有技术中在栅极结构平坦化的过程中,损耗的较多,使得形成的栅极结构的质量差,阈值电压不稳定,影响半导体器件的使用性能。以下将结合附图进行具体说明。
图1至图12是一种半导体器件的形成过程中各步骤结构示意图。
请参考图1至图3,图1是图2和图3的俯视图,图2是图1在剖线A-A的剖面图;图3是图1在剖线B-B的剖面图。一种半导体器件的形成步骤包括:提供基底100,所述基底100包括衬底101、位于所述衬底101上的若干分立排布的鳍部110、所述鳍部110包括稀疏区111和密集区112,稀疏区111的相邻鳍部之间的距离大于密集区112的相邻鳍部之间的距离。
还包括,在所述衬底101上形成隔离层102,所述隔离层102覆盖所述鳍部110根部的部分侧壁。
请参考图4和图5,在所述衬底101上形成伪栅极结构,所述伪栅极结构横跨所述鳍部110。
图4是在图2基础上的示意图;图5是在图3基础上的示意图。
所述伪栅极结构包括伪栅极介质层103和位于伪栅极介质层103上的伪栅极电极层104。
所述伪栅极介质层103位于所述鳍部110的顶部和侧壁上,同时位于所述隔离层102的顶部表面。
所述伪栅极电极层104位于所述伪栅极介质层103上。
所述伪栅极结构的侧壁上还形成有侧墙107。
所述伪栅极结构包括第一区105和第二区106,所述第一区105的伪栅极结构长度大于所述第二区106的伪栅极结构长度。
所述伪栅极结构长度是指:垂直于鳍部的延伸方向,横跨相邻鳍部之间的伪栅极结构距离。
请参考图6,在所述伪栅极结构两侧的所述鳍部110内形成源漏掺杂层120。
图6的视图方向与图4的视图方向相同。
请参考图7,在所述源漏掺杂层120以及所述侧墙107的侧壁上形成层间介质层130,所述层间介质层130的顶部表面与所述伪栅极结构的顶部表面齐平。
图7是在图6基础上的示意图。
请参考图8至图10,图11和图12,去除所述伪栅极结构,形成栅极开口(图中未标出),在所述栅极开口内形成初始栅极结构,平坦化所述初始栅极结构在所述栅极开口内形成栅极结构140,所述栅极结构包括栅极介质层141、功函数层142和金属层143。
图10是图8和图9的俯视图;图8是图10在A-A的剖面图;图9是图10在B-B的剖面图;图11是图10在C-C的剖面图;图12是图10在D-D的剖面图。
发明人发现,对比图8和图11,对比图9和图12,这种方法形成的半导体器件,在初始栅极结构的平坦化形成栅极结构的过程中,初始栅极结构中间部分损耗较多,边缘部分损耗极少,对于栅极结构长度较长的第一区而言,在初始栅极结构平坦化的过程中,初始栅极结构中间会损耗的更多,在形成栅极结构时导致第一区的栅极结构中的功函数层容易暴露出来,甚至会暴露出第一区的鳍部,这就对功函数层和鳍部表面造成损伤,导致阈值电压不稳定,这就降低了最终形成的半导体器件的使用性能。
发明人研究发现:在去除伪栅极结构之前,在第一区的伪栅极结构内形成停止层,这样在去除伪栅极结构形成初始栅极结构,对初始栅极结构进行平坦化的过程中,停止层作为平坦化过程中的停止标记,当暴露出停止层的顶部表面时,就不再对初始栅极结构进行进一步平坦化,减少了第一区的栅极结构的损耗,从而避免损伤到最终在第一区形成的栅极结构的性能,使得最终形成的半导体器件的性能得到增强。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细地说明。
图13至图27是本发明实施例的一种半导体器件的形成过程的结构示意图。
请参考图13至图15,提供基底200。
其中图13是图14、图15的俯视图,图14是图13在A-A的剖面图,图15是图13在B-B的剖面图。
在本实施例中,所述基底200包括衬底210以及位于所述衬底210上的若干相互分立的鳍部220。
在本实施例中,所述衬底210的材料为单晶硅。在其他实施例中,所述衬底210还可以为多晶硅或非晶硅。所述衬底210的材料还可以为锗、锗化硅、砷化镓等半导体材料。
在本实施例中,所述衬底210与所述鳍部220的形成方法包括:提供初始衬底(未图示);在所述初始衬底上形成图形化层;以所述图形化层为掩膜刻蚀所述初始衬底,形成所述衬底210与所述鳍部220。
在本实施例中,所述鳍部220的材料为单晶硅。在其他实施例中,所述鳍部的材料还可以为单晶锗硅或者其它半导体材料。
在其他实施例中,所述基底200还可以是不具有所述鳍部的结构。
在本实施例中,所述鳍部220的数量为多个,相邻鳍部之间的距离大小不等,将相邻鳍部之间距离大的鳍部区域定义为稀疏区221,将相邻鳍部之间距离小的鳍部区域定义为密集区222。
在本实施例中,还包括:在所述衬底210上形成隔离层201,所述隔离层201覆盖部分所述鳍部220的侧壁。
所述隔离层201的形成方法包括:在所述衬底210上形成初始隔离层(未图示),所述初始隔离层覆盖所述鳍部220;对所述初始隔离层进行平坦化处理,直至暴露出所述鳍部220的顶部表面为止;在所述平坦化处理之后,去除部分所述初始隔离层,形成所述隔离层201,所述隔离层201的顶部表面低于所述鳍部220的顶部表面。
在本实施例中,所述隔离层201的材料包括氧化硅;在其他实施例中,所述隔离层201的材料还可以包括氮化硅或氮氧化硅。
请参考图16至图18,在所述基底200上形成伪栅极结构,所述伪栅极结构包括第一区202和第二区203,所述第一区202的伪栅极结构长度大于所述第二区203的伪栅极结构长度。
所述伪栅极结构长度是指:垂直于鳍部的延伸方向,横跨相邻鳍部之间的伪栅极结构距离。
从图16中可以看出,所述鳍部沿着X方向延伸,所述伪栅结构长度就是沿着X方向上,横跨相邻所述鳍部之间的所述伪栅结构长度。
图16是图17和图18的俯视图,图17是图16在A-A的剖面图,图18是图16在B-B的剖面图。
在本实施例中,所述伪栅极结构包括伪栅介质层204和伪栅电极层205。
所述伪栅极介质层204的材料为氧化硅。
在本实施例中,所述伪栅介质层204的形成工艺为原位蒸汽生成工艺(In-SituSteam Generation,简称ISSG)。所述原位蒸汽生成工艺形成的伪栅介质层204具有良好的阶梯覆盖能力,能够使所形成的伪栅介质层204紧密地覆盖于所述鳍部结构220的侧壁表面,且所形成的伪栅介质层204的厚度均匀。
所述伪栅电极层205的材料为多晶硅。
在另一实施例中,所述伪栅介质层204的形成工艺为化学氧化工艺;所述化学氧化工艺的方法包括:采用通入臭氧的水溶液对所述鳍部结构220暴露出的侧壁和顶部表面进行氧化,形成伪栅介质层204。
在本实施例中,在所述衬底210上形成伪栅极结构,所述伪栅极结构横跨所述鳍部220,所述第一区202的伪栅极结构位于所述稀疏区221的所述鳍部220之间,所述第二区203的伪栅极结构位于所述密集区222的所述鳍部220之间。
在本实施例中,还包括:在所述伪栅极结构的顶部上形成保护层206。
在本实施例中,所述保护层206的材料为氮化硅;在其他实施例中,所述保护层206的材料还可为氧化硅、碳化硅(SiC)、氮氧化硅(SiON)、碳氧化硅(SiOC)、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)、碳氮硼化硅(SiCBN)等材料中的一种或多种组合。
在本实施例中,所述保护层206的目的在于保护所述伪栅极结构的顶部表面在后续的工艺中不受到损伤。
在本实施例中,还包括:在所述伪栅极结构和所述保护层206的侧壁上形成侧墙207。
所述侧墙207的作用在于定义后续形成源漏掺杂层的位置,且所述侧墙207用作保护所述伪栅电极层205侧壁,避免后续形成的栅电极层出现形貌缺陷,影响半导体结构的电学性能。
在本实施例中,所述侧墙207的材料为氧化硅;在其他实施例中,所述侧墙206的材料还可为氮化硅、碳化硅、氮氧化硅等。
请参考图19,在所述伪栅极结构两侧的所述鳍部220内形成源漏掺杂层208,在所述源漏掺杂层208上形成层间介质层209,所述层间介质层209覆盖所述栅极结构的侧壁。
图19的视图方向与图17的视图方向相同。
在本实施例中,在所述侧墙207两侧的所述鳍部220内形成源漏掺杂层208,在所述源漏掺杂层208上形成层间介质层209,所述层间介质层209覆盖所述侧墙207的侧壁。
在本实施例中,所述层间介质层209的形成工艺为化学气相沉积工艺;在其他实施例中,所述层间介质层209的形成工艺还可为原子层沉积工艺或物理气相沉积工艺。
在本实施例中,所述层间介质层209的材料为氧化硅;在其他实施例中,所述层间介质层209的材料还可为氮化硅、碳化硅(SiC)、氮氧化硅(SiON)、碳氧化硅(SiOC)、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)、碳氮硼化硅(SiCBN)等材料中的一种或多种组合。
请参考图20,在所述保护层206的顶部表面形成图形化层300,以所述图形化层300为掩膜,刻蚀所述第一区202的部分伪栅极结构,在所述第一区202的伪栅极结构内形成开口230,所述开口230的底部暴露出所述基底200的表面。
图20的视图方向与图18的视图方向相同。
在本实施例中,刻蚀所述第一区202的部分所述伪栅电极层205,在所述第一区202的所述伪栅电极层205内形成开口230,所述开口230的底部暴露出所述伪栅介质层204的表面。
在本实施例中,所述开口230的数量为一个;在其他实施例中,所述开口230的数量还可以为多个。
在本实施例中,形成所述开口230的目的是为后续形成停止层提供空间。
在本实施例中,形成所述开口230的工艺为干法刻蚀工艺;在其他实施例中,形成所述开口230的工艺为湿法刻蚀工艺。
请参考图21至图22,在所述开口230内形成停止层231,所述停止层231填充满所述开口230。
图21的视图方向与图20的视图方向相同;图22的视图方向与图19的视图方向相同。
在本实施例中,所述停止层231的数量为一个,所述停止层231的数量与所述开口230的数量相同。
在其他实施例中,所述停止层231的数量还可为多个。
在本实施例中,在所述开口230内形成所述停止层231之前,去除所述图形化层300和所述保护层206,所述停止层231填充满所述开口230。
在本实施例中,去除所述图形化层300和所述保护层206的工艺为刻蚀工艺;在其他实施例中,去除所述图形化层300和所述保护层206的工艺还可为灰化工艺。
在本实施例中,形成所述停止层231的步骤包括:在所述伪栅极结构的顶部表面上以及所述开口230内形成初始停止层,平坦化所述初始停止层,至暴露出所述伪栅极结构的顶部表面,在所述开口230内形成所述停止层231。
在本实施例中,采用原子层沉积工艺形成所述停止层231,原因在于原子层沉积工艺能够形成覆盖梯度较好的所述停止层231,能够较高的填充在所述开口230内,提高形成的所述停止层231的质量。
在本实施例中,所述停止层231的材料为氮化硅;
在其他实施例中,所述停止层231的材料为氮化硅、氧化硅、氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅、碳氮硼化硅中的一种或多种组合。
请参考图23至图24,去除所述伪栅极结构,在所述基底200上形成栅极开口(图中未示出),在所述栅极开口内形成初始栅极结构。
图23的视图方向与图21的视图方向相同;图24的视图方向与图22的视图方向相同。
在本实施例中,去除所述伪栅介质层204、所述伪栅电极层205以及位于所述伪栅电极层205顶部的所述保护层206。
在本实施例中,所述初始栅极结构包括:栅介质层241、功函数层242和初始栅电极层240,所述栅介质层241形成与所述栅极开口的侧壁和顶部,所述功函数层242形成与所述栅介质层241上,所述栅电极层240形成在所述功函数层上242,且填充满所述栅极开口。
所述栅介质层241的材料为为高k介质材料(介电系数大于3.9);所述高k介质材料包括氧化铪、氧化锆、氧化铪硅、氧化镧、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛或氧化铝等材料中的一种或多种组合。
所述功函数层242的材料包括:TaN、TiSiN、TaSiN、TaAl、TiAlC、AlN、TiAlN或TaAlN等材料中的一种或多种组合。
所述初始栅电极层240的材料为金属,所述金属材料包括铜、钨、镍、铬、钛、钽和铝中的一种或多种组合。
请参考图25至图27,对所述初始栅极结构进行平坦化,至暴露出所述停止层231的顶部表面,形成栅极结构244。
在本实施例中,平坦化所述初始栅电极层240,至暴露出所述停止层231的顶部表面,形成栅电极层243。
图25是图26、图27的俯视图,图26是图25在剖线A-A的剖视图,图27是图25在剖线B-B的剖视图。
在本实施例中,请对比图26与图12,图27与图11,由于所述停止层231的存在,在平坦化初始栅电极层240的过程中,当暴露出所述停止层231的顶部表面时,平坦化的过程就不能再继续,从而使得平坦化的过程得到停止,这样减少初始栅电极层240的损耗,使得形成的栅电极层243避免损耗过多,从而保证底部的功函数层具有较好的质量,避免了对阈值电压影响,同时保护好底部的鳍部表面,从而保证形成的栅极结构的质量以及鳍部质量,保证半导体器件在使用的过程中具有稳定的阈值电压,提升半导体器件的使用性能。
在本实施例中,平坦化所述初始栅电极层240的工艺为化学机械研磨工艺。
相应的,本发明还提供一种半导体器件,包括:基底200;栅极结构244,位于所述基底200上,包括第一区202和第二区203,所述第一区202的栅极结构的长度大于所述第二区203的栅极结构长度;停止层231,位于所述基底200上且位于所述第一区202的栅极结构内。
在本实施例中,所述停止层231位于基底200上且位于所述第一区202的栅极结构244内,由于停止层231的存在,一方面停止层231将第一区202的栅极结构244进行分割,实现第一区202的栅极结构244的切断(gate cut);另外一方面,在栅极结构的形成过程中,所述停止层作为所述栅极结构在形成过程中的停止标记,这样可以避免栅极结构在形成的过程中损失过多,从而提高栅极结构的形成质量。。
所述停止层231的数量为一个或者多个,在本实施例中,所述停止层231的数量为一个;在其他实施例中,所述停止层231的数量还可为多个。
在本实施例中,所述停止层231的材料为氮化硅;
在其他实施例中,所述停止层231的材料为氮化硅、氧化硅、氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅、碳氮硼化硅中的一种或多种组合。
在本实施例中,所述基底200包括:衬底210和位于所述衬底210上的若干分立排布的鳍部220,所述鳍部220包括稀疏区221和密集区222。
所述密集区222的所述鳍部之间的距离小于所述稀疏区221的所述鳍部之间的距离。
在本实施例中,所述栅极结构244位于所述衬底210上且横跨所述鳍部220,所述第一区202的栅极结构244位于所述稀疏区221的鳍部220之间,所述第二区203的栅极结构244位于密集区222的鳍部220之间。
在本实施例中,所述栅极结构244包括栅介质层241、功函数层242和栅电极层243,所述栅介质层241位于所述鳍部220的顶部和侧壁上,所述功函数层242位于所述栅介质层241上,所述栅电极层243位于所述功函数层242上,所述栅电极层243的材料为金属。
在本实施例中,还包括:隔离层201,所述隔离层201位于所述衬底210上且覆盖所述鳍部220的部分侧壁,所述隔离层201用于相邻所述鳍部220之间的电学隔离。
在本实施例中,所述隔离层201的材料为氧化硅;在其他实施例中,所述隔离层201的材料还可为氮化硅、氮氧化硅等。
在本实施例中,还包括:源漏掺杂层208,位于所述栅极结构244两侧的所述鳍部220内。
所述源漏掺杂层208的形成工艺包括外延生长和原位掺杂工艺。
在本实施例中,还包括:层间介质层209,位于所述源漏掺杂层208上且覆盖所述栅极结构244的侧壁表面。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (10)
1.一种半导体器件,其特征在于,包括:
基底;
栅极结构,位于所述基底上包括第一区和第二区,所述第一区的栅极结构的长度大于所述第二区的栅极结构长度;
停止层,位于所述基底上且位于所述第一区的栅极结构内。
2.如权利要求1所述的半导体器件,其特征在于,所述停止层的数量为一个或者多个。
3.如权利要求1所述的半导体器件,其特征在于,所述停止层的材料为氮化硅、氧化硅、氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅、碳氮硼化硅中的一种或多种组合。
4.一种半导体器件的形成方法,其特征在于,包括:
提供基底,在所述基底上形成伪栅极结构,所述伪栅极结构包括第一区和第二区,所述第一区的伪栅极结构长度大于所述第二区的伪栅极结构长度;
刻蚀所述第一区的部分伪栅极结构,在所述第一区的伪栅极结构内形成开口,所述开口的底部暴露出所述基底的表面;
在所述开口内形成停止层,所述停止层填充满所述开口;
去除所述伪栅极结构,在所述基底上形成栅极开口,在所述栅极开口内形成初始栅极结构;
对所述初始栅极结构进行平坦化,至暴露出所述停止层的顶部表面,形成栅极结构。
5.如权利要求4所述的半导体器件的形成方法,其特征在于,所述开口的数量与所述停止层的数量相等。
6.如权利要求5所述的半导体器件的形成方法,其特征在于,所述开口的数量为一个,所述停止层的数量为一个或者所述开口的数量为多个,所述停止层的数量为多个。
7.如权利要求4所述的半导体器件的形成方法,其特征在于,所述停止层的材料为氮化硅、氧化硅、氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅、碳氮硼化硅中的一种或多种组合。
8.如权利要求4所述的半导体器件的形成方法,其特征在于,形成所述停止层的工艺为化学气相沉积工艺、原子层沉积工艺或者物理气相沉积工艺中的一种或者多种组合。
9.如权利要求4所述的半导体器件的形成方法,其特征在于,形成所述停止层的方法为:在所述伪栅极结构的顶部表面形成初始停止层;对所述初始停止层进行平坦化,至暴露出所述伪栅极结构的顶部表面。
10.如权利要求4所述的半导体器件的形成方法,其特征在于,所述栅极结构包括形成在所述基底上的栅介质层、形成所述栅介质层上的功函数层以及形成在所述功函数层上的金属层。
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