CN104160507B - 在三栅极(finfet)工艺上集成多个栅极电介质晶体管的方法 - Google Patents
在三栅极(finfet)工艺上集成多个栅极电介质晶体管的方法 Download PDFInfo
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Classifications
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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Abstract
描述了具有不同栅极结构并且形成于单个集成电路上的两种或更多类型的基于鳍状物的晶体管。至少通过(多个)栅极电介质层的厚度或成分或者栅极电极中的(多个)功函数金属层的成分来区分每种类型的晶体管的栅极结构。还提供了用于制造具有至少两种不同类型的基于鳍状物的晶体管的集成电路的方法,其中通过(多个)栅极电介质层的厚度和成分和/或栅极电极中的功函数金属的厚度和成分来区分所述晶体管类型。
Description
技术领域
本发明总体涉及半导体器件、半导体逻辑器件、和晶体管的制造。具体而言,本发明的实施例涉及用于在同一芯片上制造具有不同栅极结构的多个基于鳍状物的器件的工艺。
背景技术
对于不断缩小的集成电路(IC)的期望对用于构造器件的技术和材料提出了极大的要求。IC芯片的部件包括诸如CMOS(互补金属氧化物半导体)器件之类的固态逻辑器件(晶体管)。最近开发的基于鳍状物的晶体管使能对应较小器件占用空间的提高的性能。不同的晶体管应用具有不同的结构和性能要求,例如,高速逻辑操作、低功率使用、高电压输入输出(I/O)、以及超高电压。需要新工艺来使能单个芯片上的多种类型的新的基于鳍状物的晶体管的制造。
附图说明
图1A-1D示出双栅极晶体管的实施例,其中每个晶体管具有不同的栅极堆叠体构造。
图2A-2B示出三栅极晶体管的实施例,其中每个晶体管具有不同的栅极堆叠体构造。
图3A-3B示出四栅极晶体管的实施例,其中每个晶体管具有不同的栅极堆叠体构造。
图4A-4I示出用于形成具有包含不同栅极堆叠体构造的多个晶体管的单个IC的方法。
图5A-5I示出用于形成具有包含不同栅极堆叠体构造的多个晶体管的单个IC的附加的方法。
图6A-6G示出用于形成具有包含不同栅极堆叠体构造的多个晶体管的单个IC的附加的方法。
图7A-7E示出用于形成具有包含不同栅极堆叠体构造的多个晶体管的单个IC的附加的方法。
图8示出根据本发明的一个实施例的计算设备。
具体实施方式
描述了包括两个或更多具有不同类型的栅极结构的基于鳍状物的场效应晶体管的集成电路(IC)结构,并且还描述了用于在单个芯片上形成不同类型的晶体管的方法。为提供对本发明的深入理解,已经针对具体细节对本发明进行了描述。本领域内的技术人员将领会到,可以在没有这些具体细节的情况下实践本发明。在其它实例中,为了不非必要地使本发明难以理解,没有具体描述公知的半导体工艺和设备。另外,附图中所示的各种实施例是说明性的表示,并且不必按比例绘制。
本发明的实施例提供容纳具有不同类型的栅极结构的多个基于鳍状物的晶体管的集成电路,以及用于在单个电路上制造这些不同类型的器件的方法。形成具有多个晶体管类型的IC可以解决不同的电路要求,例如,诸如高速逻辑操作、低功率使用、高电压输入输出(I/O)、以及超高电压,其是对片上系统(SOC)集成电路的部件所期望的属性。片上系统器件将诸如处理器核、模拟功能、以及混合的信号模块之类的多种电路功能集成到单个集成电路芯片上。本发明的实施例提供具有包含不同类型的栅极结构的晶体管的IC,每个栅极结构包括一个或两个高k材料栅极电介质层、氧化物(SiO2)层、一个或两个功函数金属层、填充金属、以及它们的组合。具有不同栅极结构的晶体管能够提供跨越大范围的操作速度、泄漏特性、以及高电压容差的性能特性。还公开了形成包括具有不同栅极结构的晶体管的电路的方法。
图1A-1D示出位于集成电路中的基于鳍状物的晶体管的实施例。每个集成电路具有至少两种不同的晶体管类型,至少通过栅极电介质的厚度或成分、和/或栅极电极中所采用的功函数金属的成分来区分不同的晶体管类型。晶体管可以具有其它区分特征。通常,具有多个不同晶体管类型的集成电路将具有以各种格式(例如,阵列)布置的每种类型的晶体管的大量实例。为简单起见,在图1A-1D中,每种类型的晶体管中的一个实例被示出为隔离的晶体管,尽管所示出的晶体管通常出现在它们所处的集成电路芯片中的不同位置和布置中。
图1A示出形成于同一个IC上的两个晶体管101和102的三维透视图。图1B示出如图1A中所示的晶体管101和102的沿着线A-A’截取的穿过沟道区116以及栅极结构111A和111B的截面视图。在实施例中,鳍状物112 从半导体衬底110延伸出来,并且蔓延衬底110的整个长度。在实施例中,每个晶体管包括由隔离区114分开的一个或多个鳍状物112。在实施例中,每个晶体管包括限定了沟道区116的栅极结构111,栅极结构111环绕每个鳍状物112的一部分的侧面和顶表面。在实施例中,晶体管101包括栅极结构111A,并且晶体管102包括栅极结构111B,如图1A所示。每个鳍状物112具有设置于沟道区116的相对侧上的一对源极/漏极区118,如由图 1A所示出的实施例中所示。对于PMOS器件而言,源极/漏极区是p型掺杂的,并且沟道区是n型掺杂的。对于NMOS器件而言,源极/漏极区是n 型掺杂的,并且沟道区是p型掺杂的。隔离区114上方的鳍状物112的高度在20到的范围内,并且鳍状物112的宽度在5到的范围内。
每个晶体管栅极结构111A和111B包括栅极电介质113和栅极电极 115,如图1A中所示。每个栅极电介质113可以包括一个或多个电介质层,例如,二氧化硅层或高k电介质层。栅极电介质113使沟道区116与栅极电极115绝缘,以减小泄漏并且设置器件阈值电压。每个栅极电极115包括一个或多个功函数金属层,并且还可以包括导电性填充金属140。功函数金属层管理电介质材料与填充金属之间的势垒高度,使金属-半导体交界面处的电阻最小化,并且设置器件的功函数。填充金属承载控制晶体管状态的大部分电荷,并且通常是比起(多个)功函数金属的低电阻电阻材料。
图1A-D中所示的集成电路具有至少两个不同类型的晶体管101和 102,通过晶体管栅极结构中所采用的电介质层的成分来区分每个晶体管。在本发明的实施例中,晶体管101的栅极结构包括具有高k电介质层121 的栅极电介质、以及具有功函数金属层131和填充金属140的栅极电极,如图1B中所示。晶体管101中的栅极结构的类型使能晶体管在高性能核心中的使用。
在本发明的实施例中,高k电介质层121与包括晶体管101的鳍状物 112和隔离区114的侧面和顶表面相符合。通常,高k电介质层是介电常数大于二氧化硅的介电常数的电介质材料。二氧化硅的介电常数是3.9。可以用于高k电介质层121中的示例性高k电介质材料包括二氧化铪(HfO2)、硅氧化铪、氧化镧、氧化镧铝、二氧化锆(ZrO2)、硅氧化锆、二氧化钛(TiO2)、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化镱、氧化铝、铅钪钽氧化物、铌锌酸铅、以及半导体领域内已知的其它材料。高k电介质层121的厚度在10到的范围内。在实施例中,高k电介质层的厚度是
功函数金属层131与高k电介质层121的表面相符合。可以用于功函数金属层131中的示例性金属包括氮化钛、氮化钨、氮化钽、钛铝、钨、硅化物以及半导体领域内已知的其它材料。功函数金属层131的厚度在10 到的范围内。在实施例中,功函数金属层131的厚度是
填充金属140填充由功函数金属层131限定的栅极结构开口。填充金属140可以包括包含例如金属栅极材料的材料,所述金属栅极材料例如铪、锆、钛、氮化钛、钽、铝、以及它们的组合。另外的材料包括金属碳化物,例如,碳化钛、碳化锆、碳化钽、碳化铪和碳化铝。可以使用的其它材料包括钌、钯、铂、钴、镍、以及导电性金属氧化物,例如氧化钌。其它材料是可行的。
在实施例中,晶体管102的栅极结构具有包括二氧化硅层125和高k 电介质层121的栅极电介质、以及包括功函数金属层131和填充金属140 的栅极电极。在实施例中,从鳍状物112的表面生长二氧化硅层125。在另一个实施例中,二氧化硅层125共形地沉积在鳍状物112和隔离区114上。二氧化硅层125的厚度可以在5到的范围内。在实施例中,二氧化硅层125的厚度是在实施例中,高k电介质层121覆盖栅极结构内的二氧化硅层125,并且这两层一起形成了栅极电介质。在实施例中,功函数金属131覆盖高k电介质层121,并且填充金属140填充由功函数金属131 装衬的开口。与晶体管101中的栅极结构相比较,在栅极电介质中添加二氧化硅层125使能晶体管102在高电压、输入输出(I/O)电路应用中的使用。
通常,电介质材料150至少部分地包围晶体管结构101和102,如图1B中所示。在一些实施例中,电介质材料150是层间电介质(ILD)材料,例如二氧化硅或低k电介质材料。可以使用的另外的电介质材料包括碳掺杂的氧化物(CDO)、碳化硅、氮化硅、诸如八氟环丁烷或聚四氟乙烯之类的有机聚合物、氟硅酸盐玻璃(FSG)、以及诸如倍半硅氧烷、硅氧烷、或有机硅酸盐玻璃之类的有机硅酸盐。
在实施例中,间隔体135位于栅极结构111的侧壁上。如图1A中所示,间隔体135形成于邻接源极/漏极区118的栅极结构111侧壁上,从而将栅极结构111与鳍状物112上生长的外延材料隔离,并且还在源极/漏极区的重掺杂期间保护沟道区116。间隔体135可以另外形成于每个栅极结构111 的端部上,如图1B中所示。间隔体135可以由适合的电介质材料组成,例如,氮化硅、二氧化硅、氮氧化硅、或半导体领域内已知的其它材料。
本发明的另一个实施例包括至少两个不同类型的基于鳍状物的晶体管 101和103,其中通过栅极结构中所采用的电介质层的成分来区分每个晶体管,如图1C中所示。在本发明的实施例中,晶体管101的栅极结构包括具有高k电介质层121的栅极电介质、以及具有功函数金属层131和填充金属140的栅极电极。
晶体管103的栅极结构包括具有高k电介质层122和高k电介质层121 的栅极电介质、以及具有功函数金属层131和填充金属140的栅极电极。在实施例中,高k电介质层122形成于鳍状物表面上。在实施例中,高k 电介质层121覆盖高k电介质层122。在实施例中,功函数金属层131覆盖高k电介质层121。在实施例中,填充金属140通过填充在由功函数金属层131限定的栅极结构开口中来完成栅极结构。在实施例中,高k电介质层 122具有与高k电介质层121不同的成分或厚度。与晶体管101中的栅极结构相比较,添加高k电介质材料122在增大了阈值电压的同时减小了栅极泄漏,使能晶体管103用于低功率电路或应用。高k电介质层122可以是以上针对高k电介质层121所列出的材料中的任何材料。高k电介质层122 的厚度在10到的范围内。在实施例中,高k电介质层122的厚度是
本发明的另一个实施例包括位于单个集成电路上的至少两个不同类型的基于鳍状物的晶体管101和104,其中每个类型的晶体管具有不同的栅极结构,如图1D所示出的。在本发明的实施例中,通过每个栅极电极中所采用的(多个)功函数金属的成分来区分晶体管101和104。在特定实施例中,晶体管101的栅极结构包括具有高k电介质层121的栅极电介质、以及具有功函数金属层131和填充金属140的栅极电极。
在实施例中,晶体管104中的栅极结构包括具有高k电介质层121的栅极电介质以及具有功函数金属层132、功函数金属层131和填充金属140 的栅极电极。在实施例中,高k电介质层121覆盖鳍状物112。在实施例中,功函数金属层132覆盖高k电介质层121。在实施例中,功函数金属层131 覆盖功函数金属层132。在实施例中,填充金属140填充由功函数金属层 131限定的栅极结构开口。在实施例中,晶体管104中的功函数金属层132 具有与功函数金属层131不同的功函数。与晶体管101中的栅极结构相比较,添加功函数金属132增大了晶体管104的阈值电压,并且减小了栅极泄漏,使能晶体管104用于低功率电路或应用。功函数金属层132可以是以上针对功函数金属层131所列出的材料中的任何材料。功函数金属层132 的厚度可以在10到的范围内。在实施例中,功函数金属层132的厚度是
图2A-B所示出的实施例包括单个集成电路上的三个或更多类型的基于鳍状物的晶体管,其中每个类型的晶体管具有不同的栅极结构。通常,具有多个不同类型的晶体管的集成电路将具有以各种格式(例如,阵列) 设置的每种类型的晶体管的大量实例。为简单起见,在附图中,晶体管的每种类型的一个实例被示出为隔离的晶体管,尽管所示出的晶体管通常出现在它们所处的集成电路上的不同位置和布置中。
根据本发明的实施例,图2A中所示的集成电路具有至少三个不同类型的晶体管201、202和203,通过栅极结构中所采用的电介质层的厚度或成分来区分它们。在实施例中,晶体管201中的栅极结构包括具有高k电介质层221的栅极电介质、以及具有功函数金属层231和填充金属240的栅极电极。晶体管201可以用于高性能处理器核。在实施例中,晶体管202 中的栅极结构包括具有鳍状物表面上的二氧化硅层225以及二氧化硅层225 上面的高k电介质层221的栅极电介质。在实施例中,晶体管202还包括具有功函数金属层231和填充金属240的栅极电极。与晶体管201相比较,添加二氧化硅层225减小了泄漏,并且增大了阈值电压,使能晶体管202 用于高电压输入输出(I/O)电路或应用。在实施例中,晶体管203的栅极结构包括具有鳍状物212上的高k电介质层222、以及高k层222上面的高电介质层221的栅极电介质。在实施例中,晶体管203还包括具有功函数金属层231和填充金属240的栅极电极。在实施例中,高k电介质层222 具有与高k电介质层221不同的成分。在另一个实施例中,高k电介质层 222具有与高k电介质层221不同的厚度。与晶体管201相比较,在栅极结构中添加高k电介质层222减小了泄漏,使能晶体管203用于低功率电路。
图2B中所示出的集成电路具有至少三个不同类型的晶体管201、202 和204,通过晶体管栅极结构中所采用的电介质层的成分或厚度、和/或功函数金属的成分来区分每个晶体管。在实施例中,晶体管201中的栅极结构包括具有高k电介质层221的栅极电介质、以及具有功函数金属层231 和填充金属240的栅极电极。晶体管201被设计用于高性能处理器核。在实施例中,晶体管202中的栅极结构包括具有鳍状物212上的二氧化硅层 225和二氧化硅层225上的高k电介质层221的栅极电介质。在实施例中,晶体管202还包括具有功函数金属层231和填充金属240的栅极电极。与晶体管201相比较,添加二氧化硅层225减小了泄漏,并且增大了阈值电压,使能晶体管202用于高电压输入输出(I/O)电路或应用。在实施例中,晶体管204的栅极结构包括具有高k电介质层221的栅极电介质以及具有功函数金属层232、功函数金属层232上的功函数金属层231、和填充金属 240的栅极电极。在实施例中,功函数金属232具有与功函数金属层231不同的功函数。与晶体管201相比较,添加功函数金属层232减小了泄漏,使能晶体管204用于低功率电路或应用。
根据本发明的实施例,图3A-B中示出了包括至少四种类型的基于鳍状物的晶体管的电路,其中每种类型的晶体管具有不同的栅极结构。如图3A-B 中所示出的包括四种类型的晶体管栅极结构的实施例是图2A-B中所示出的三种类型的晶体管的实施例的延续,并且可以在不引起附加的加工步骤的情况下制造。
图3A中所示的集成电路具有至少四个不同类型的晶体管301、302、 303和305,通过栅极结构中所采用的电介质层的厚度或成分来区分每个晶体管。在实施例中,晶体管301中的栅极结构包括具有高k电介质层321 的栅极电介质、以及具有功函数金属层331和填充金属340的栅极电极。晶体管301被设计用于高性能处理器核。在实施例中,晶体管302中的栅极结构包括具有生长在鳍状物312上的二氧化硅层325以及二氧化硅层325 上面的高k电介质层321的栅极电介质。在实施例中,晶体管302还包括具有功函数金属层331和填充金属340的栅极电极。晶体管302被设计用于高电压输入输出(I/O)电路。在实施例中,晶体管303中的栅极结构包括具有鳍状物表面上的高k电介质层322和高k电介质层322上面的高k 电介质层321的栅极电介质、以及具有功函数金属层331和填充金属340 的栅极电极。在实施例中,高k电介质层322的成分与高k电介质层321 的成分不同。在另一个实施例中,高k电介质层322的厚度与高k电介质层321的厚度不同。晶体管303被设计用于低功率电路。
在实施例中,晶体管305的栅极结构包括具有鳍状物上的二氧化硅层 325、二氧化硅层325上面的高k电介质层322、以及高k电介质层322上面的高k电介质层321的栅极电介质。在实施例中,高k电介质层322的成分与高k电介质层321的成分不同。在另一个实施例中,高k电介质层 322的厚度与高k电介质层321的厚度不同。在实施例中,晶体管305还包括具有功函数金属层331和填充金属340的栅极电极。与晶体管301中的高性能栅极结构相比较,添加二氧化硅层325和高k电介质层322增大了晶体管305的阈值电压,从而晶体管305可以用于要求超高电压的电路。
图3B示出具有多种类型的晶体管的电路的另一个实施例。集成电路具有至少四个不同类型的晶体管301、302、304和306,至少通过栅极结构中所采用的电介质层的厚度或成分、和/或功函数金属的成分来区分每个晶体管。在实施例中,晶体管301中的栅极结构包括具有高k电介质层321的栅极电介质、以及具有功函数金属层331和填充金属340的栅极电极。晶体管301被设计用于高性能处理器核。在实施例中,晶体管302中的栅极结构包括具有生长在鳍状物312上的二氧化硅层325以及二氧化硅层325 上面的高k电介质层321的栅极电介质。在实施例中,晶体管302还包括具有功函数金属层331和填充金属340的栅极电极。晶体管302被设计用于高电压输入输出(I/O)电路。在实施例中,晶体管304中的栅极结构包括具有高k电介质层321的栅极电介质以及具有功函数金属层332层、功函数金属层332层上面的功函数金属层331层、和填充金属340的栅极电极。在实施例中,功函数金属层332具有与功函数金属331不同的功函数。晶体管304被设计用于低功率电路。
在实施例中,晶体管306中的栅极结构包括具有生长在鳍状物312上的二氧化硅层325以及二氧化硅层325上面的高k电介质层321的栅极电介质。在实施例中,晶体管306还包括具有功函数金属层332、功函数金属层332上面的功函数金属层331、以及填充金属340的栅极电极。在实施例中,功函数金属层332具有与功函数金属层331不同的功函数。与晶体管301中的高性能栅极结构相比较,添加二氧化硅层325和功函数金属层322 增大了晶体管306的阈值电压,从而晶体管306可以用于要求超高电压的电路。
针对前面所描述的实施例,应该注意的是,还可以改变诸如栅极的宽度、沟道区的宽度、以及源极和漏极的类型之类的用于实现特定晶体管属性的其它器件特性,如本领域技术人员所理解的那样。
在制造的器件中,材料的层可以在外表上与为清楚起见在本文中提供的简化说明背离,并且可以例如在某些区域中稍厚或稍薄一些。此外,此处所描述的材料的“层”可以由本质上用作一个层的多个材料层组成。
图4A-I描述了用于形成多种类型的基于鳍状物的晶体管栅极结构的方法的实施例。所述方法对于形成在同一芯片上包括不同类型的基于鳍状物的晶体管的集成电路是有用的,其中晶体管具有至少两种不同的栅极电介质结构。集成电路芯片通常在衬底上的不同位置中包含相同晶体管的多个副本,然而,为清楚起见,图4A-I中示出每种类型的晶体管中的一个。
提供了具有鳍状物412的衬底410。在本发明的实施例中,从体单晶衬底形成鳍状物412。衬底410和鳍状物412可以由任何公知的半导体材料形成,所述公知的半导体材料例如但不限于硅、锗、硅锗、以及包括GaAs、 InSb、GaP、和GaSb的Ⅲ-Ⅴ化合物。鳍状物412的下层部分被隔离区414 分开,以防止来自鳍状物的泄漏,如图4A中所示。在实施例中,隔离区414包括诸如二氧化硅之类的电介质材料。在另一个实施例中,从包括下层体衬底、中间的绝缘层、以及顶部单晶层的绝缘体上硅(SOI)衬底形成鳍状物412。从顶部单晶层形成鳍状物412,并且中间的绝缘层形成隔离区。延伸到隔离区414上方的鳍状物412的高度在20到的范围内。鳍状物412的宽度在5到的范围内。
接下来,将二氧化硅层425形成于延伸到隔离区414上方的鳍状物412 的表面上。在实施例中,二氧化硅层425将形成栅极电介质的一部分,用于形成于栅极区492上的晶体管。在实施例中,随后将在形成附加的栅极结构部件之前从栅极区491去除二氧化硅层425。在特定实施例中,从鳍状物412的表面生长二氧化硅层425。在另一个特定实施例中,通过能够实现栅极区中的鳍状物412上的共形沉积的任何方法(例如化学气相沉积(CVD) 或原子层沉积(ALD))来均厚沉积二氧化硅层425。二氧化硅层425可以生长或沉积为均匀的厚度。在实施例中,二氧化硅层425的厚度是
用于从栅极区491去除二氧化硅层425的随后的蚀刻工艺包含两个牺牲层,所述两个牺牲层保护了将形成栅极区492中形成的器件的有源部件的二氧化硅层425的部分。在本发明的实施例中,嵌入的蚀刻停止层442 均厚沉积在衬底的表面上,并且牺牲二氧化硅层443共形地形成于嵌入的蚀刻停止层442上。在本发明的实施例中,嵌入的蚀刻停止层442和牺牲二氧化硅层443不会形成晶体管的有源部件。可以都通过诸如CVD或ALD 之类的适合于形成共形层的任何方法来沉积嵌入的蚀刻停止层442和二氧化硅层443。在实施例中,当通过挑选的化学蚀刻对两者进行蚀刻时,与二氧化硅的蚀刻速率相比较,嵌入的蚀刻停止层442是在较低速率下蚀刻的材料。在实施例中,嵌入的蚀刻停止层442是氮化硅。
将嵌入的蚀刻停止层442和二氧化硅层443都形成为均匀的厚度。挑选每个嵌入的蚀刻停止层442和二氧化硅层443的厚度,从而定时的蚀刻将在大致相同的时间内去除每个层。在实施例中,使用HF蚀刻工艺。HF 采用比氮化硅快的速率蚀刻二氧化硅,并且因此,在实施例中,牺牲二氧化硅层443比嵌入的蚀刻停止层442厚。在实施例中,牺牲二氧化硅层443 与二氧化硅层425的厚度相同。在实施例中,嵌入的蚀刻停止层442的厚度是在实施例中,二氧化硅层443的厚度是
接下来,利用光刻蚀刻工艺从栅极区491的表面去除牺牲二氧化硅层 443。在实施例中,在结构表面上形成光致抗蚀剂。对光致抗蚀剂进行光刻图案化,以便光致抗蚀剂455覆盖随后将形成包括二氧化硅层425的栅极结构的栅极区492,如图4C中所示。然后从栅极结构491蚀刻二氧化硅层 443的暴露的部分。可以通过诸如湿法蚀刻之类的任何适合的蚀刻工艺来蚀刻二氧化硅层443。湿法蚀刻包括例如HF。HF蚀刻可以具有从50:1-200:1 的浓度。在实施例中,在50秒内,从栅极区491的表面完全或近似完全地蚀刻二氧化硅层443。
在蚀刻二氧化硅层443之后,从结构表面去除光致抗蚀剂455,如图 4D中所示。总的来说,通过半导体产业中公知的工艺来去除光致抗蚀剂。可以例如通过干法等离子体工艺来去除光致抗蚀剂。采用被设计为去除有机残留、通常被称为灰化(ashing)的氧气等离子体工艺来去除抗蚀剂。例如,通过微波、RF(射频)、或UV臭氧源来产生等离子体。替代地,可以利用溶剂或溶剂的混合物来去除光致抗蚀剂。
接下来,根据图4E中示出的实施例,将牺牲栅极材料454均厚沉积在结构表面上。将牺牲栅极材料454形成为对应栅极高度所期望的厚度。然后对牺牲栅极材料454进行图案化并且进行蚀刻,以在栅极区491和492 上形成牺牲栅极结构456,从而随后可以通过栅极替换工艺形成有源栅极结构。牺牲栅极材料的沉积、图案化、和蚀刻是半导体领域内所公知的。牺牲栅极结构456被图案化成相同的形状,并且在将要形成随后形成的栅极电极和栅极电介质的位置的同一位置处。在本发明的实施例中,从诸如氮化硅或多晶硅之类的材料形成牺牲栅极电极材料。形成牺牲栅极结构456 之后,可以例如通过如本领域中所公知的顶端注入或晕环注入来对鳍状物 412进行掺杂。
接下来,如果需要的话,可以在牺牲栅极结构456的侧壁上形成电介质侧壁间隔体435。侧壁间隔体用于隔离栅极结构与可能生长在鳍状物的源极/漏极区上的外延半导体材料,如图1A中所示,但是间隔体材料可以另外形成于栅极结构的其它侧壁上,如图4F中所示。可以通过任何公知的技术来形成侧壁间隔体435,例如,通过在衬底上均厚沉积共形的侧壁间隔体电介质,并且然后进行各向异性地蚀刻,以从水平表面去除电介质间隔体材料,而留下垂直表面上的间隔体材料。间隔体453可以是氮化硅、二氧化硅、氮氧化硅、碳化硅、CDO或它们的组合。在实施例中,将过蚀刻用于从鳍状物412的侧壁去除间隔体材料,以使能随后的鳍状物表面上的外延层的生长、源极/漏极区的掺杂、和/或源极/漏极接触部的形成。
接下来,将电介质材料450均厚沉积在衬底上。将电介质材料形成为足够厚度以完全覆盖包括牺牲栅极结构456的衬底。电介质450由能够针对牺牲栅极材料进行选择性蚀刻的材料形成。也就是,电介质由一材料形成,由此可以在不明显蚀刻掉电介质450的情况下去除牺牲栅极结构456。在均厚沉积之后,诸如通过化学机械平坦化(CMP)之类的方法使电介质材料450平坦化,直到顶表面与牺牲栅极结构456成为平面。
然后蚀刻掉牺牲栅极结构456,以使能栅极区491和492中的栅极结构的形成。可以利用湿法或干法蚀刻工艺来去除牺牲栅极结构456。蚀刻工艺暴露了栅极区491上的下层嵌入蚀刻停止层442表面以及栅极区492上的下层牺牲二氧化硅层443表面,如图4G中所示。
在实施例中,附加的蚀刻工艺从栅极区491去除了嵌入的蚀刻停止层 442和二氧化硅层425,并且还从栅极区492去除了牺牲二氧化硅层443和嵌入的蚀刻停止层442。在实施例中,使用了选择性蚀刻。在另一个实施例中,使用了定时湿法蚀刻。在实施例中,定时湿法蚀刻可以包括HF。在特定实施例中,HF在比牺牲二氧化硅443材料更快的速率蚀刻嵌入的蚀刻停止层442。在实施例中,蚀刻工艺具有3:1的选择率。HF蚀刻可以具有从 50:1-200:1的浓度。由于已经基于HF蚀刻材料的速率选择了每个牺牲层的厚度,所以采用与通过HF从栅极区492蚀刻牺牲二氧化硅层443和嵌入的蚀刻停止层442相同的时间,完全或近似完全地蚀刻栅极区491上的嵌入的蚀刻停止层442和二氧化硅层425。
在实施例中,二氧化硅层425保留在将形成部分栅极电介质的栅极区 492上。像这样,在没有可能污染有源器件层的被暴露的光致抗蚀剂的情况下,已经在栅极区492上形成了二氧化硅层425。相对于直接利用光刻工艺对有源层进行图案化的器件而言,未被污染的二氧化硅层的形成将改进器件的性能和可靠性。
接下来,根据本发明的实施例,在衬底表面上以均匀的厚度共形沉积高k电介质层421。在实施例中,高k电介质材料421覆盖栅极区491中的鳍状物412的顶表面和侧壁,并且与栅极区492上的二氧化硅层425表面相符合。在实施例中,高k电介质层421将形成栅极区491和492中形成的栅极结构中的部分栅极电介质。在实施例中,通过诸如CVD或ALD之类的共形工艺来形成高k电介质材料,以确保与栅极区491中的鳍状物表面和栅极区492中的下层二氧化硅层425接触。高k电介质层421可以是任何适合的高k电介质材料,例如以上针对图1A中的高k电介质层121所描述的。高k电介质层421的厚度可以是10到在实施例中,高k电介质材料421的厚度是
接下来,在每个栅极区中在栅极电介质上形成栅极电极。栅极电极可以包括一个或多个功函数金属层和填充金属。在实施例中,功函数金属431 以均匀的厚度共形沉积在衬底上。功函数金属431设置器件的功函数,并且使栅极电介质与栅极电极之间的金属-半导体界面处的电阻最小化。通过诸如CVD或ALD之类的共形工艺来形成功函数金属431,以确保与栅极区491和492两者中的下层高k电介质层421接触。功函数金属层431可以是任何适合的功函数金属,例如以上针对图1A中的功函数金属层131所描述的。功函数金属层431的厚度可以是10到在实施例中,功函数金属层431的厚度是
然后将填充金属440以足够填充栅极区491和492中的栅极结构开口的厚度均厚沉积在功函数金属431上。可以通过诸如CVD、ALD、或物理气相沉积(PVD)之类的任何适合的工艺来形成金属栅极440。金属栅极材料可以是任何适合的栅极电极材料,例如以上针对图1A所描述的。
然后将金属栅极440、功函数材料431、和高k电介质层421化学地机械地平坦化,直到露出电介质层450的顶表面,如图4I中所示。一旦将栅极电极材料和栅极电介质材料背面抛光并从顶部电介质材料450去除之后,就形成了栅极结构。
因此,形成了两个晶体管401和402,每个晶体管具有不同的栅极结构。在实施例中,晶体管401包括具有高k材料421的栅极电介质、以及具有功函数金属431和填充金属440的栅极电极。晶体管401可以用于高性能处理器核。在实施例中,晶体管402包括具有二氧化硅层425和高k电介质层421的栅极电介质、以及具有功函数金属431和填充金属440的栅极电极。与晶体管401的栅极电介质相比较,在栅极电介质中添加二氧化硅层425使能晶体管402用于高电压输入-输出(I/O)电路和应用。
图5A-I示出用于形成包括两种类型的晶体管的集成电路的另一种方法,其中两种类型的晶体管具有不同的栅极结构。集成电路芯片通常在不同位置中包含相同晶体管的多个副本,然而,为清楚起见,图5A-I中示出每种类型的晶体管中的一个晶体管。
提供了具有鳍状物512的衬底510,如图5A中所示。在实施例中,衬底510和鳍状物512是单晶硅。鳍状物512由隔离区514分开,隔离区514 可以包括诸如例如二氧化硅之类的电介质材料。用于形成图5A中所示的结构的方法是半导体制造的领域中所公知的。
接下来,在所述结构的表面上形成二氧化硅层525。在本发明的实施例中,二氧化硅层525将形成随后形成于栅极区592中的栅极结构的一部分。在特定实施例中,从鳍状物512的表面生长二氧化硅层525。在另一个特定实施例中,通过诸如CVD或ALD之类的使能栅极区的水平和垂直表面上的共形沉积的任何方法来沉积二氧化硅层525。在实施例中,二氧化硅层 525的厚度是
根据本发明的实施例,然后形成牺牲栅极结构,从而随后可以通过栅极替换工艺形成有源栅极结构。在实施例中,将牺牲栅极材料554均厚沉积在二氧化硅层525上,如图5B中所示。将牺牲栅极材料554形成为针对栅极高度所需要的厚度。然后对牺牲栅极材料554进行图案化并进行蚀刻,以在栅极区591和592上形成牺牲栅极结构556。牺牲栅极材料的沉积、图案化、和蚀刻是半导体领域中所公知的。将牺牲栅极结构556图案化成相同的形状,并且在将要形成随后形成的栅极电极和栅极电介质的同一位置处。在本发明的实施例中,从诸如氮化硅或多晶硅之类的材料形成牺牲栅极结构556。形成牺牲栅极结构556之后,可以例如通过如本领域中所公知的顶端注入或晕环注入来对鳍状物512进行掺杂。
接下来,如果需要的话,可以在牺牲栅极结构556的侧壁上形成电介质侧壁间隔体535。侧壁间隔体用于隔离栅极结构与可能生长在鳍状物的源极/漏极区上的外延半导体材料,如图1A中所示,但是间隔体材料可以另外形成于栅极结构的其它侧壁上,如图5C中所示。可以通过任何公知的技术来形成侧壁间隔体535,例如,通过在衬底上均厚沉积共形的侧壁间隔体电介质,并且然后各向异性地蚀刻,以从水平表面去除电介质间隔体材料,而留下垂直表面上的间隔体材料。间隔体553可以是氮化硅、二氧化硅、氮氧化硅、碳化硅、CDO或它们的组合。在实施例中,将过蚀刻用于从鳍状物512的侧壁去除间隔体材料,以使能随后的鳍状物表面上的外延层的生长、源极/漏极区的掺杂、和/或源极/漏极接触部的形成。
接下来,将电介质材料550均厚沉积在衬底上。将电介质材料形成为足够完全覆盖包括牺牲栅极结构556的衬底的厚度。电介质层550由能够针对牺牲栅极材料进行选择性蚀刻的材料形成。也就是,电介质材料由一材料形成,由此可以在不明显蚀刻掉电介质550的情况下去除牺牲栅极结构556。在对电介质进行均厚沉积之后,例如通过CMP将电介质层平坦化,直到电介质薄膜的顶表面与牺牲栅极结构556成为平面。
然后蚀刻掉牺牲栅极结构556,以使能栅极区591和592内的栅极结构的形成。可以利用湿法或干法蚀刻工艺来蚀刻牺牲栅极结构556。蚀刻牺牲栅极结构556暴露了栅极区591和592内的二氧化硅层525,如图5D中所示。在实施例中,栅极区592中形成的栅极电介质将包括二氧化硅层525,但是栅极区591中形成的栅极结构将不包括二氧化硅层525。因此,随后对二氧化硅层525进行图案化,从而在保护栅极区592内的部分的同时,去除栅极区591内的部分。在本发明的另一个特定实施例中,从表面蚀刻掉二氧化硅层525的所有暴露的部分,并且为了具有未被腐蚀的二氧化硅层而从鳍状物生长新的二氧化硅层,或者在衬底上沉积新的二氧化硅层,利用所述未被腐蚀的二氧化硅层来形成随后形成的栅极结构的有源部件。
然后在二氧化硅层525上均厚沉积硬掩模534,如图5E中所示出的。在实施例中,在二氧化硅层525在栅极区591内的部分的蚀刻期间,硬掩模534将保护二氧化硅层525在栅极区592内的部分不被暴露在光致抗蚀剂下。硬掩模534可以包括例如不被HF蚀刻的功函数金属,例如但不限于氮化钛、氮化钨、和氮化钽。在实施例中,通过ALD形成硬掩模534。将硬掩模534形成为从10到的均匀的厚度,该厚度足够在随后的蚀刻工艺中保护下层材料。在实施例中,硬掩模534的厚度是
接下来,对硬掩模534进行图案化,以去除覆盖栅极区591内的二氧化硅层525的部分,如图5F中所示。在实施例中,通过光刻工艺对硬掩模534进行图案化。在实施例中,沉积光致抗蚀剂层555并对其进行图案化,使得光致抗蚀剂覆盖栅极区592上的硬掩模534。在实施例中,然后从没有被光致抗蚀剂覆盖的区域蚀刻硬掩模534,暴露栅极区591上的下层二氧化硅层525。在实施例中,利用对下层氧化物有高度选择性的湿法蚀刻工艺(例如过氧化氢和硫酸)蚀刻硬掩模534。
接下来,去除光致抗蚀剂层555,留下栅极区592上的硬掩模534。在实施例中,然后从栅极区591蚀刻二氧化硅层525。通过在蚀刻二氧化硅层 525之前去除光致抗蚀剂层545,用于蚀刻二氧化硅层525的蚀刻容器没有被光致抗蚀剂材料污染。在实施例中,蚀刻栅极区591上的二氧化硅层525 暴露了栅极区591中的鳍状物512和隔离区514的表面。对二氧化硅上的硬掩模材料有选择性的任何蚀刻可以用于蚀刻二氧化硅层525。在实施例中,利用HF来蚀刻二氧化硅层525。在实施例中,然后从栅极区592去除硬掩模534,以暴露二氧化硅层525,如图5H中所示。在实施例中,通过诸如过氧化氢和硫酸之类的湿法蚀刻工艺来去除硬掩模534。
然后通过沉积附加的栅极电介质层和栅极电极材料来形成栅极结构。在实施例中,在衬底上共形沉积高k电介质层521,覆盖栅极区591中的鳍状物的顶表面和侧壁,并且与栅极区592上的二氧化硅层525表面相符合。通过诸如CVD或ALD之类的共形工艺来形成高k电介质材料,以确保与栅极区591中的鳍状物接触,或与栅极区592中的下层第一二氧化硅层525 接触。高k电介质层521可以是任何适合的高k电介质材料,例如以上针对图1A中的高k电介质层121所描述的。高k电介质层521的厚度可以是 10到在实施例中,高k电介质材料521的厚度是
接下来,形成栅极电极。每个栅极电极可以包括一个或多个功函数金属层和填充金属。在实施例中,功函数金属531共形沉积在衬底上。通过诸如CVD或ALD之类的共形工艺来形成功函数金属531,以确保与下层高k电介质层521接触。功函数金属层531可以是任何适合的功函数金属,例如以上针对图1A中的功函数金属层131所描述的。功函数金属层531的厚度可以是10到在实施例中,功函数金属层531的厚度是
接下来,将填充金属540材料以足够填充栅极区591和592中的栅极结构开口的厚度均厚沉积在功函数金属531上。可以通过诸如CVD、ALD、或PVD之类的任何适合的工艺来形成填充金属540。填充金属材料可以是任何适合的栅极电极材料,例如以上针对图1A中的填充金属140所描述的。
然后将填充金属540、功函数材料531、和高k电介质层521化学地机械地平坦化,直到露出电介质层550的顶表面,如图5I中所示。一旦将栅极电极材料和栅极电介质材料背面抛光或从顶部电介质材料550去除之后,就形成了栅极结构。
因此,形成了两个晶体管501和502,每个晶体管具有不同的栅极结构。在实施例中,晶体管501包括具有高k材料521的栅极电介质、以及具有功函数金属531和填充金属540的栅极电极。晶体管501的栅极结构可以用于高性能处理器核。在实施例中,晶体管502包括具有二氧化硅层525 和二氧化硅层525上面的高k电介质层521的栅极电介质、以及具有功函数金属531和填充金属540的栅极电极。与晶体管501相比较,在晶体管 502的栅极电介质中附加的二氧化硅材料使能在高电压输入-输出(I/O)电路中的使用。
图6A-G提供了用于形成包括两种类型的晶体管的集成电路的方法的附加的实施例,其中每个晶体管类型具有不同的栅极电介质结构。集成电路芯片通常在不同位置中包含相同晶体管的多个副本,然而,为清楚起见,图6A-G中示出每种类型的晶体管中的一个晶体管。
提供了包括具有被隔离区614分开的鳍状物612和鳍状物上方的由具有间隔体635的电介质650限定的栅极结构开口的衬底610的结构。用于形成所述结构的方法是半导体制造的领域中已知的。可以例如通过以下步骤来形成所述结构:首先遵循图5A-5D中所示的和以上所述的工艺,并且然后去除覆盖栅极区691和693的二氧化硅层625的部分,如图6A中所示。在实施例中,通过湿法或干法蚀刻从栅极区691和693去除二氧化硅层625。
接下来,在衬底上均厚沉积高k电介质层622。通过诸如CVD或ALD 之类的共形工艺来形成高k电介质材料622,以确保与每个栅极区中的鳍状物的接触。在实施例中,高k电介质层622将形成栅极电介质的一部分,用于栅极区693中形成的晶体管。在实施例中,将从栅极区691去除高k 电介质层622。高k电介质层622可以是任何适合的高k电介质材料,例如以上针对图1B中的高k电介质层122所描述的。高k电介质层622的厚度可以是10到在实施例中,高k电介质材料622的厚度是
然后在高k电介质层622上均厚沉积硬掩模634,如图6B中所示出的。在实施例中,在随后从栅极区691蚀刻高k电介质层622期间,硬掩模634 将保护栅极区693内的高k电介质层622的部分不被暴露在光致抗蚀剂下。硬掩模634可以包括例如不被HF蚀刻的功函数金属,例如但不限于氮化钛、氮化钨、和氮化钽。在实施例中,通过ALD形成硬掩模634。将硬掩模634 形成为10到的均匀的厚度,该厚度足够在随后的蚀刻工艺中保护下层材料。在实施例中,硬掩模634的厚度是
接下来,对硬掩模634进行图案化,以去除覆盖栅极区691内的高k 电介质层622的部分,如图6C中所示。在实施例中,通过光刻工艺对硬掩模634进行图案化。在实施例中,沉积光致抗蚀剂层655并对其进行图案化,从而使光致抗蚀剂覆盖栅极区693上的硬掩模634。在实施例中,然后蚀刻硬掩模634,以暴露栅极区691中的高k电介质层622。在实施例中,利用对下层氧化物有高度选择性的湿法蚀刻工艺(例如过氧化氢和硫酸) 蚀刻硬掩模634。
然后去除光致抗蚀剂层655,留下栅极区693上的硬掩模634。然后蚀刻栅极区691上的高k电介质层622的暴露的部分,以暴露栅极区691中的鳍状物612和隔离区614的表面,如图6D中所示。通过在蚀刻栅极区 691上的高k电介质层622之前去除光致抗蚀剂层655,用于蚀刻高k电介质层622的蚀刻容器没有被光致抗蚀剂材料污染。对高k电介质材料上的硬掩模材料有选择性的任何蚀刻可以用于蚀刻高k层622。在实施例中,利用HF来蚀刻高k电介质层622。在实施例中,然后从栅极区693去除硬掩模634,以暴露高k电介质层622的表面,如图6E中所示。在实施例中,通过诸如过氧化氢和硫酸之类的湿法蚀刻工艺来去除硬掩模634。
接下来,在所述结构上共形沉积高k电介质层621。在实施例中,高k 电介质层621将形成栅极电介质的一部分,用于栅极区691和693中形成的晶体管中的每一个晶体管。在栅极区691中,高k电介质材料621覆盖栅极结构开口内的鳍状物612和隔离区614,并且在栅极区693中,高k电介质层621与高k电介质层622相符合。通过诸如CVD或ALD之类的共形工艺来形成高k电介质材料621,以确保与栅极区中的下层材料接触。在实施例中,高k电介质层621具有与高k电介质层622不同的成分。在另一个实施例中,高k电介质层621具有与高k电介质层622不同的厚度。高k电介质层621包括诸如以上针对图1A中的高k电介质层121所描述的之类的高k电介质材料。高k电介质层621的厚度可以是10到在实施例中,高k电介质材料621的厚度是
接下来,形成栅极电极。栅极电极可以包括一个或多个功函数金属层和填充金属。在实施例中,功函数金属631以均匀的厚度沉积在衬底上。通过诸如CVD或ALD之类的共形工艺来形成功函数金属层631,以确保与下层高k电介质层621接触。功函数金属层631可以是任何适合的功函数金属,例如以上针对图1A中的功函数金属层131所描述的。功函数金属层631的厚度可以是10到在实施例中,功函数金属层631的厚度是
接下来,将填充金属640以足够填充栅极区691和693上的栅极结构开口的厚度均厚沉积在功函数金属631上。可以通过诸如CVD、ALD、或 PVD之类的任何适合的工艺来形成填充金属640。填充金属可以是任何适合的栅极电极材料,例如以上针对图1A中的填充金属140所描述的。
然后将填充金属640、功函数材料631、和高k电介质层621和高k电介质层622化学地机械地平坦化,直到露出电介质层650的顶表面,如图 6G中所示。一旦将栅极电极材料和栅极电介质材料背面抛光或从电介质材料650的顶部去除之后,就形成了栅极结构。
因此,形成了两个不同的晶体管601和603,每个晶体管具有不同的栅极结构。在实施例中,晶体管601包括具有高k材料621的栅极电介质、以及具有功函数金属631和填充金属640的栅极电极。晶体管601的栅极结构使得能够用于高性能处理器核。在实施例中,晶体管603包括具有高k 电介质层622和高k电介质层621的栅极电介质、以及具有功函数金属631 和填充金属640的栅极电极。所述两层高k材料使能晶体管603用于低功率电路或应用。
图7A-E提供了用于形成包括两种类型的晶体管的集成电路的方法的附加的实施例,其中每个晶体管类型具有不同的栅极电极结构。集成电路芯片通常在不同位置中包含相同晶体管的多个副本,然而,为清楚起见,图7A-E中示出每种类型的晶体管中的一个晶体管。
提供了包括具有被隔离区714分开的鳍状物712和鳍状物上方的由电介质材料750与间隔体735限定的栅极结构开口的衬底710的结构。用于形成所述结构的方法是半导体制造的领域中已知的。可以例如通过以下步骤来形成所述结构:首先遵循图5A-5D中所示的和以上所述的工艺,并且然后去除覆盖栅极区791和794的二氧化硅层725的部分,如图7A中所示。
接下来,通过在栅极区791和794中沉积栅极电介质层来形成栅极结构的部分。将高k电介质层721均厚沉积在结构表面上(如图7B中所示出的),覆盖栅极区791和794内的鳍状物712和隔离区714。通过诸如CVD 或ALD之类的共形工艺来形成高k电介质材料721,以确保鳍状物712的表面上的均匀形成。高k电介质层721包括诸如以上针对图1A中的高k电介质层121所描述的之类的高k电介质材料。高k电介质层721的厚度可以是10到在实施例中,高k电介质材料721的厚度是
接下来,在所述结构上均厚沉积功函数金属732,如图7B中所示。在实施例中,功函数金属层732将形成栅极电极的一部分,用于栅极区794 中形成的晶体管栅极结构。在实施例中,将随后从栅极区791去除功函数金属层732。在实施例中,功函数金属732与高k电介质材料721的表面相符合。可以通过诸如CVD或ALD之类的共形工艺来沉积功函数金属。功函数金属层732可以是任何适合的功函数金属,例如以上针对图1A所描述的。在实施例中,在实施例中,在沉积之后将功函数金属层732氮化,以改变材料的功函数。功函数金属层732的厚度可以是10到在实施例中,功函数金属层732的厚度是
然后对功函数金属层732进行图案化,以去除栅极区791内的部分。在实施例中,利用光刻对功函数层732进行图案化。在实施例中,沉积光致抗蚀剂层755并对其进行图案化,从而使光致抗蚀剂覆盖栅极区794中的功函数金属层732的部分。在实施例中,然后从栅极区791蚀刻掉功函数金属层732,以暴露下层高k电介质材料721,如图7C中所示。可以利用干法蚀刻或湿法蚀刻工艺来蚀刻功函数金属层732。
接下来,去除光致抗蚀剂755,并且在衬底上均厚沉积功函数金属层 731。通过诸如CVD或ALD之类的共形工艺来形成功函数金属层731,以确保与栅极区791上的下层高k电介质层721接触,并且与栅极区794上的功函数金属层732接触。功函数金属层731可以是任何适合的功函数金属,例如以上针对图1A所描述的。在实施例中,功函数金属731具有与功函数金属层732不同的功函数。功函数金属层731的厚度可以是10到在实施例中,功函数金属层731的厚度是
接下来,叫啊ing填充金属740以足够填充栅极区791和794上的栅极结构开口的厚度均厚沉积在功函数金属731上。可以通过诸如CVD、ALD、或PVD之类的任何适合的工艺来形成填充金属740。填充金属可以是任何适合的栅极电极材料,例如以上针对图1A所描述的。
然后将填充金属740、功函数金属731、功函数金属732、和高k电介质层721化学机械平坦化,直到露出电介质层750的顶表面,如图7E中所示。一旦将栅极电极材料和栅极电介质材料背面抛光或从顶部电介质材料 750去除之后,就形成了栅极结构。
因此,形成了两个不同的晶体管701和704,每个晶体管具有不同的栅极结构。在实施例中,晶体管701的栅极结构包括具有高k材料721的栅极电介质、以及具有功函数金属层731和填充金属740的栅极电极。晶体管701可以用于高性能处理器核。在实施例中,晶体管704的栅极结构包括具有高k材料721的栅极电介质、以及具有功函数金属732、功函数金属731、和填充金属740的栅极电极。晶体管704可以用于低功率电路或应用中。
以上如针对图4A-I、5A-I、6A-G、和7A-E所描述的工艺能够以组合的形式用于形成具有三种或更多类型的晶体管的集成电路,其中每种类型的晶体管具有不同的栅极结构。
图8示出根据本发明的一种实施方式的计算设备800。计算设备800容纳板802。板802可以包括一些部件,所述部件包括但不限于处理器804和至少一个通信芯片806。处理器804与板802物理地和电气地耦合。在一些实施方式中,至少一个通信芯片806也与板802物理地和电气地耦合。在其它实施方式中,通信芯片806是处理器804的一部分。
取决于其应用,计算设备800可以包括其它部件,所述其它部件可以或可以不与板802物理地和电气地耦合。这些其它部件包括,但不限于易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、闪存存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、以及大容量存储设备(例如硬盘驱动器、光盘(CD)、数字多功能盘(DVD),等等)。
通信芯片806使能用于到和来自设备800的数据的传送的无线通信。术语“无线”和其衍生物可以用于描述可以通过使用调制的电磁辐射经由非固态介质传递数据的电路、设备、系统、方法、技术、通信信道、等等。所述术语并不暗示相关联的设备不能包含任何电线,尽管在一些实施例中它们可能不包含。通信芯片806可以实施多种无线标准或协议中的任何一种,所述多种无线标准或协议包括但不限于Wi-Fi(IEEE 802.11族)、WiMAX (IEEE802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、 HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、及它们的衍生物,以及被指定为3G、4G、5G和之外的任何其它无线协议。计算设备800可以包括多个通信芯片806。例如,第一通信芯片806可以专用于诸如Wi-Fi和蓝牙的较短距的无线通信,并且第二通信芯片806可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其它的较远距的无线通信。
计算设备800的处理器804包括封装在处理器804内的集成电路管芯。在本发明的一些实施方式中,处理器的集成电路管芯包括根据本发明的实施方式的两个或更多基于鳍状物的晶体管。术语“处理器”可以指代处理来自寄存器和/存储器的电子数据以将该电子数据转换成可以在寄存器和/ 或存储器中存储的其它电子数据的任何器件或器件的部分。
通信芯片806还包括封装在通信芯片806内的集成电路管芯。根据本发明的另一种实施方式,通信芯片的集成电路管芯包括根据本发明的实施方式的两个或更多基于鳍状物的晶体管。
在其它实施方式中,计算设备800内容纳的另一个部件可以包含集成电路管芯,该集成电路管芯包括根据本发明的实施方式的两个或更多基于鳍状物的晶体管。
在各种实施方式中,计算设备800可以是膝上型电脑、上网本、笔记本、超极本、智能手机、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器、或数字录像机。在其它实施中,计算设备800可以是处理数据的任何其它电子设备。
Claims (19)
1.一种半导体器件,包括:
具有多个半导体鳍状物的衬底;
第一晶体管,其具有环绕一个或多个所述半导体鳍状物的第一栅极结构,其中所述第一栅极结构包括与所述第一栅极结构所环绕的所述半导体鳍状物接触的第一栅极电介质结构以及包括第一功函数金属层的第一栅极电极结构,所述第一功函数金属层与所述第一栅极电介质结构接触,所述第一晶体管具有位于所述第一栅极结构的相对侧上的第一对n型掺杂的源极/漏极区;以及
第二晶体管,其具有环绕一个或多个所述半导体鳍状物的第二栅极结构,其中所述第二栅极结构包括与所述第二栅极结构所环绕的所述半导体鳍状物接触的第二栅极电介质结构以及包括第二功函数金属层的第二栅极电极结构,所述第二功函数金属层与所述第二栅极电介质结构接触,所述第二晶体管具有位于所述第二栅极结构的相对侧上的第二对n型掺杂的源极/漏极区,其中所述第二栅极电介质结构在厚度或成分上与所述第一栅极电介质结构不同。
2.根据权利要求1所述的器件,其中所述第一栅极电介质结构包括第一高k电介质层,并且其中所述第一栅极电极结构包括所述第一功函数金属层和填充金属。
3.根据权利要求2所述的器件,其中所述第二栅极电极结构在成分上与所述第一栅极电极结构相同,并且其中所述第二栅极电介质结构包括二氧化硅层和所述第一高k电介质层。
4.根据权利要求2所述的器件,其中所述第二栅极电极结构在成分上与所述第一栅极电极结构相同,并且其中所述第二栅极电介质结构包括第二高k电介质层和所述第一高k电介质层。
5.根据权利要求2所述的器件,其中所述第二栅极电极结构包括所述第一功函数金属层和所述第二功函数金属层,其中所述第二功函数金属层在成分上与所述第一功函数金属层不同。
6.根据权利要求2所述的器件,还包括第三晶体管,其中所述第三晶体管具有第三栅极结构,所述第三栅极结构包括第三栅极电介质结构和所述第一栅极电极结构,其中所述第三栅极电介质结构在成分上与所述第一栅极电介质结构不同。
7.根据权利要求2所述的器件,还包括第三晶体管,其中所述第三晶体管具有第三栅极结构,所述第三栅极结构包括所述第一栅极电介质结构和所述第二栅极电极结构。
8.根据权利要求6所述的器件,还包括第四晶体管,其中所述第四晶体管具有第四栅极结构,所述第四栅极结构包括第四栅极电介质结构和所述第一栅极电极结构,其中所述第四栅极电介质结构包括二氧化硅层、所述第一高k电介质层、和第二高k电介质层。
9.根据权利要求7所述的器件,还包括第四晶体管,其中所述第四晶体管具有第四栅极结构,所述第四栅极结构包括所述第二栅极电介质结构和所述第二栅极电极结构。
10.一种用于形成半导体器件的方法,包括:
提供具有多个半导体鳍状物的衬底,每个所述半导体鳍状物具有设置于其中的沟道区,其中第一栅极区跨越一个或多个所述半导体鳍状物的所述沟道区,并且其中第二栅极区跨越一个或多个所述半导体鳍状物的所述沟道区;
在所述第一栅极区和所述第二栅极区内的所述半导体鳍状物上生长第一二氧化硅层;
在所述第一栅极区和所述第二栅极区内并且在所述第一二氧化硅层之上均厚沉积嵌入的蚀刻停止层;
在所述嵌入的蚀刻停止层之上均厚沉积第二二氧化硅层;
利用第一蚀刻工艺进行蚀刻,以从所述第一栅极区去除所述第二二氧化硅层;以及
利用第二蚀刻工艺进行蚀刻,以从所述第一栅极区去除所述嵌入的蚀刻停止层和所述第一二氧化硅层,并且从所述第二栅极区去除所述第二二氧化硅层和所述嵌入的蚀刻停止层。
11.根据权利要求10所述的方法,其中所述第二蚀刻工艺包括定时的湿法蚀刻。
12.根据权利要求11所述的方法,其中所述定时的湿法蚀刻包括HF。
13.根据权利要求10所述的方法,还包括:
在所述第一栅极区内形成与所述半导体鳍状物接触的第一虚设栅极结构;
在所述第二栅极区内形成与所述第一二氧化硅层接触的第二虚设栅极结构;
均厚沉积电介质层;以及
抛光所述电介质层,以暴露所述第一虚设栅极和第二虚设栅极。
14.根据权利要求10所述的方法,其中所述嵌入的蚀刻停止层是氮化硅。
15.一种用于形成半导体器件的方法,包括:
提供具有多个半导体鳍状物的衬底,每个所述半导体鳍状物具有设置于其中的沟道区,其中第一栅极区跨越一个或多个所述半导体鳍状物的所述沟道区,并且其中第二栅极区跨越一个或多个所述半导体鳍状物的所述沟道区;
在所述第一栅极区和所述第二栅极区内的所述鳍状物之上均厚沉积电介质层;
在所述电介质层之上均厚沉积硬掩模层;
对所述硬掩模层进行图案化,以从所述第一栅极区去除所述硬掩模层;
对所暴露的电介质层进行图案化,以从所述第一栅极区去除所述电介质层;
从所述第二栅极区去除所述硬掩模层;
在所述第一栅极区内形成与所述半导体鳍状物接触的第一虚设栅极结构;
在所述第二栅极区内形成与所述电介质层接触的第二虚设栅极结构;
均厚沉积电介质层;以及
抛光所述电介质层,以暴露所述第一虚设栅极和第二虚设栅极。
16.根据权利要求15所述的方法,其中对所述硬掩模进行图案化包括:
在所述第一栅极区和所述第二栅极区之上形成光致抗蚀剂层;
对所述光致抗蚀剂层进行图案化,以暴露所述第一栅极区上的所述硬掩模层;
从所述第一栅极区蚀刻所述硬掩模的所暴露的部分;以及
去除所述光致抗蚀剂层。
17.根据权利要求15所述的方法,其中所述电介质层是二氧化硅。
18.根据权利要求15所述的方法,其中已经利用替换栅极工艺形成了所述第一栅极区和第二栅极区。
19.根据权利要求18所述的方法,其中所述电介质层是高k电介质材料。
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TWI691048B (zh) | 2020-04-11 |
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TW201946111A (zh) | 2019-12-01 |
TWI605568B (zh) | 2017-11-11 |
US20140319623A1 (en) | 2014-10-30 |
WO2013101007A1 (en) | 2013-07-04 |
TW201721837A (zh) | 2017-06-16 |
CN104160507A (zh) | 2014-11-19 |
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