FR3011382B1 - Procede de realisation d'un circuit integre - Google Patents
Procede de realisation d'un circuit integre Download PDFInfo
- Publication number
- FR3011382B1 FR3011382B1 FR1359365A FR1359365A FR3011382B1 FR 3011382 B1 FR3011382 B1 FR 3011382B1 FR 1359365 A FR1359365 A FR 1359365A FR 1359365 A FR1359365 A FR 1359365A FR 3011382 B1 FR3011382 B1 FR 3011382B1
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- layer
- depositing
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- dielectric
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- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000151 deposition Methods 0.000 abstract 5
- 239000002184 metal Substances 0.000 abstract 5
- 238000005530 etching Methods 0.000 abstract 2
- 230000001681 protective effect Effects 0.000 abstract 2
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
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- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
L'invention concerne un procédé de réalisation d'un circuit intégré sur un substrat comportant les étapes suivantes : - réalisation d'un empilement de grille à la surface d'une zone active, comportant les sous-étapes suivantes : • dépôt d'une couche d'un premier diélectrique ; • dépôt d'une couche conductrice de grille ; • dépôt d'une couche d'un premier métal ; • dépôt d'une couche d'un deuxième métal ; • dépôt d'une couche d'un deuxième diélectrique ; - gravure partielle de l'empilement de grille pour la formation d'une zone de grille sur zone active ; - réalisation d'espaceurs isolants de part et d'autre de la zone de grille sur zone active ; - réalisation de zones de source et de drain ; - réalisation de zones de siliciuration à la surface des zones de source et de drain ; - gravure, sur la zone de grille sur zone active, de la deuxième couche de diélectrique et de la couche du deuxième métal avec arrêt sur la couche du premier métal, de manière à former une cavité entre les espaceurs isolants ; - réalisation d'un bouchon de protection à la surface de la couche du premier métal de la zone de grille sur zone active, le bouchon de protection venant combler la cavité.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1359365A FR3011382B1 (fr) | 2013-09-27 | 2013-09-27 | Procede de realisation d'un circuit integre |
US14/498,091 US9240325B2 (en) | 2013-09-27 | 2014-09-26 | Method for making an integrated circuit |
US14/965,519 US20160099326A1 (en) | 2013-09-27 | 2015-12-10 | Method for making an integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1359365 | 2013-09-27 | ||
FR1359365A FR3011382B1 (fr) | 2013-09-27 | 2013-09-27 | Procede de realisation d'un circuit integre |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3011382A1 FR3011382A1 (fr) | 2015-04-03 |
FR3011382B1 true FR3011382B1 (fr) | 2019-03-29 |
Family
ID=49753384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1359365A Active FR3011382B1 (fr) | 2013-09-27 | 2013-09-27 | Procede de realisation d'un circuit integre |
Country Status (2)
Country | Link |
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US (2) | US9240325B2 (fr) |
FR (1) | FR3011382B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11929314B2 (en) * | 2021-03-12 | 2024-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures including a fin structure and a metal cap |
Family Cites Families (23)
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US5686329A (en) * | 1995-12-29 | 1997-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a metal oxide semiconductor field effect transistor (MOSFET) having improved hot carrier immunity |
US6764911B2 (en) * | 2002-05-10 | 2004-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd | Multiple etch method for fabricating spacer layers |
US7019351B2 (en) * | 2003-03-12 | 2006-03-28 | Micron Technology, Inc. | Transistor devices, and methods of forming transistor devices and circuit devices |
KR100502426B1 (ko) * | 2003-09-18 | 2005-07-20 | 삼성전자주식회사 | 듀얼 게이트를 갖는 반도체 소자 및 그 형성 방법 |
WO2005036651A1 (fr) * | 2003-10-09 | 2005-04-21 | Nec Corporation | Dispositif a semi-conducteur et son procede de production |
KR100672762B1 (ko) * | 2003-10-29 | 2007-01-22 | 주식회사 하이닉스반도체 | 리버스 게이트 공정을 이용한 반도체소자의 제조 방법 |
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JP4940682B2 (ja) * | 2005-09-09 | 2012-05-30 | 富士通セミコンダクター株式会社 | 電界効果トランジスタおよびその製造方法 |
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KR20110137435A (ko) * | 2010-06-17 | 2011-12-23 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
WO2012107970A1 (fr) * | 2011-02-10 | 2012-08-16 | パナソニック株式会社 | Dispositif semi-conducteur |
US10658361B2 (en) * | 2011-12-28 | 2020-05-19 | Intel Corporation | Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process |
-
2013
- 2013-09-27 FR FR1359365A patent/FR3011382B1/fr active Active
-
2014
- 2014-09-26 US US14/498,091 patent/US9240325B2/en active Active
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2015
- 2015-12-10 US US14/965,519 patent/US20160099326A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20150091106A1 (en) | 2015-04-02 |
US9240325B2 (en) | 2016-01-19 |
US20160099326A1 (en) | 2016-04-07 |
FR3011382A1 (fr) | 2015-04-03 |
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