JP5554701B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5554701B2 JP5554701B2 JP2010506065A JP2010506065A JP5554701B2 JP 5554701 B2 JP5554701 B2 JP 5554701B2 JP 2010506065 A JP2010506065 A JP 2010506065A JP 2010506065 A JP2010506065 A JP 2010506065A JP 5554701 B2 JP5554701 B2 JP 5554701B2
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- 239000004065 semiconductor Substances 0.000 title claims description 470
- 239000012535 impurity Substances 0.000 claims description 360
- 230000000903 blocking effect Effects 0.000 claims description 56
- 239000000758 substrate Substances 0.000 claims description 32
- 125000006850 spacer group Chemical group 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 12
- 238000003892 spreading Methods 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 description 56
- 238000000034 method Methods 0.000 description 41
- 238000002513 implantation Methods 0.000 description 35
- 238000004519 manufacturing process Methods 0.000 description 31
- 238000009792 diffusion process Methods 0.000 description 29
- 239000007789 gas Substances 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 17
- 238000010586 diagram Methods 0.000 description 13
- 238000009826 distribution Methods 0.000 description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 11
- 229910052796 boron Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000006866 deterioration Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000003405 preventing effect Effects 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 5
- 239000012141 concentrate Substances 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 230000007935 neutral effect Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
以下、本発明の第1の実施形態に係る半導体装置及びその製造方法について図面を参照しながら説明する。
以下、本発明の不純物阻止部(第1の実施形態ではゲート電極15の突き出し部15a)によって前述の効果が得られるメカニズムについて、図面を参照しながら説明する。図6(a)及び(b)は、本実施形態の製造方法におけるエクステンション領域を形成するための不純物注入工程を示す概念図であり、図6(a)は図5(b)のA−A線の断面構成に対応し、図6(b)は図5(b)のB−B線の断面構成に対応する。
以下、本発明の第2の実施形態に係る半導体装置及びその製造方法について図面を参照しながら説明する。
12 絶縁層
13a〜13d フィン型半導体領域
14a〜14d ゲート絶縁膜
15 ゲート電極
15a 突き出し部
15A ポリシリコン膜
16 絶縁性サイドウォールスペーサ
17 エクステンション領域
17a エクステンション領域の高濃度部分(フィン型半導体領域上部中央)
17b エクステンション領域の他の部分(フィン型半導体領域左側部)
17c エクステンション領域の他の部分(フィン型半導体領域右側部)
17d エクステンション領域の他の部分(フィン型半導体領域上部左側コーナー)
17e エクステンション領域の他の部分(フィン型半導体領域上部右側コーナー)
17f エクステンション領域の他の部分(フィン型半導体領域中央部)
17g エクステンション領域の高濃度部分(フィン型半導体領域上部及び両側部)
17h エクステンション領域の他の部分(フィン型半導体領域中央部)
18a 注入イオン
18b 吸着種
18c 離脱不純物
27 ソース・ドレイン領域
30 不純物阻止部
41、42 レジストパターン
50a、50b 不純物領域
Claims (20)
- 基板上に形成されたフィン型半導体領域と、
前記フィン型半導体領域の所定部分の上面及び両側面を覆うように形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記フィン型半導体領域における前記ゲート電極の両側に形成された不純物領域とを備え、
前記フィン型半導体領域の上面上における前記ゲート電極の両側に隣接して、不純物の導入を阻止するための不純物阻止部が設けられ、
前記不純物阻止部は、前記ゲート電極の材料とは異なる材料から構成され、
前記不純物阻止部の側面上に絶縁性サイドウォールスペーサが形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記不純物阻止部のゲート幅方向の寸法は、前記フィン型半導体領域のゲート幅方向の寸法よりも小さいことを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置において、
前記ゲート電極のゲート長方向の寸法は45nm以下であることを特徴とする半導体装置。 - 請求項1〜3のいずれか1項に記載の半導体装置において、
前記フィン型半導体領域の側部に形成された前記不純物領域の比抵抗は、前記フィン型半導体領域の上部に形成された前記不純物領域の比抵抗の2倍以下であることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記フィン型半導体領域の側部に形成された前記不純物領域の比抵抗は、前記フィン型半導体領域の上部に形成された前記不純物領域の比抵抗の1.25倍以下であることを特徴とする半導体装置。 - 請求項1〜3のいずれか1項に記載の半導体装置において、
前記フィン型半導体領域の側部に形成された前記不純物領域のシート抵抗は、前記フィン型半導体領域の上部に形成された前記不純物領域のシート抵抗の2倍以下であることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記フィン型半導体領域の側部に形成された前記不純物領域のシート抵抗は、前記フィン型半導体領域の上部に形成された前記不純物領域のシート抵抗の1.25倍以下であることを特徴とする半導体装置。 - 請求項1〜3のいずれか1項に記載の半導体装置において、
前記フィン型半導体領域の側部に形成された前記不純物領域の拡がり抵抗は、前記フィン型半導体領域の上部に形成された前記不純物領域の拡がり抵抗の2倍以下であることを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記フィン型半導体領域の側部に形成された前記不純物領域の拡がり抵抗は、前記フィン型半導体領域の上部に形成された前記不純物領域の拡がり抵抗の1.25倍以下であることを特徴とする半導体装置。 - 請求項1〜9のいずれか1項に記載の半導体装置において、
前記基板と前記フィン型半導体領域との間に絶縁層が形成されていることを特徴とする半導体装置。 - 請求項1〜10のいずれか1項に記載の半導体装置において、
前記基板は、前記フィン型半導体領域となる凸部を有する半導体基板であることを特徴とする半導体装置。 - 請求項1〜11のいずれか1項に記載の半導体装置において、
前記不純物領域はエクステンション領域であることを特徴とする半導体装置。 - 請求項1〜12のいずれか1項に記載の半導体装置において、
前記フィン型半導体領域における前記ゲート電極から見て前記絶縁性サイドウォールスペーサの両側に他の不純物領域が形成されていることを特徴とする半導体装置。 - 請求項13に記載の半導体装置において、
前記他の不純物領域はソース・ドレイン領域であることを特徴とする半導体装置。 - 請求項1〜14のいずれか1項に記載の半導体装置において、
前記フィン型半導体領域の高さは前記フィン型半導体領域のゲート幅方向の寸法よりも大きいことを特徴とする半導体装置。 - 請求項1〜15のいずれか1項に記載の半導体装置において、
複数の前記フィン型半導体領域が前記基板上に所定のピッチで形成されており、
前記ゲート電極は前記各フィン型半導体領域を横断するように形成されており、
前記不純物阻止部は前記各フィン型半導体領域同士の間には形成されていないことを特徴とする半導体装置。 - 請求項1〜16のいずれか1項に記載の半導体装置において、
前記不純物阻止部は絶縁材料から構成されていることを特徴とする半導体装置。 - 請求項1〜17のいずれか1項に記載の半導体装置において、
前記ゲート電極は、ゲート幅方向において実質的に均一なゲート長を有していることを特徴とする半導体装置。 - 請求項1〜18のいずれか1項に記載の半導体装置において、
ゲート幅方向における前記フィン型半導体領域の長さは、前記フィン型半導体領域の高さの1/3程度であることを特徴とする半導体装置。 - 請求項1〜19のいずれか1項に記載の半導体装置において、
前記不純物領域は、ソース側のエクステンション領域及びドレイン側のエクステンション領域を含み、
前記ソース側のエクステンション領域と前記ドレイン側のエクステンション領域との間の距離は、前記フィン型半導体領域の上部中央においても、前記フィン型半導体領域の上部コーナー及び両側部においても、実質的に同じであることを特徴とする半導体装置。
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PCT/JP2009/001974 WO2009144874A1 (en) | 2008-05-29 | 2009-04-30 | Finfet with impurity blocking portion on an upper surface of fin |
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US8258585B2 (en) | 2012-09-04 |
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