JP4970185B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4970185B2 JP4970185B2 JP2007197398A JP2007197398A JP4970185B2 JP 4970185 B2 JP4970185 B2 JP 4970185B2 JP 2007197398 A JP2007197398 A JP 2007197398A JP 2007197398 A JP2007197398 A JP 2007197398A JP 4970185 B2 JP4970185 B2 JP 4970185B2
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- 239000004065 semiconductor Substances 0.000 title claims description 149
- 238000004519 manufacturing process Methods 0.000 title claims description 30
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- 238000000034 method Methods 0.000 claims description 44
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- 210000000746 body region Anatomy 0.000 claims description 20
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 229910052814 silicon oxide Inorganic materials 0.000 description 26
- 239000000758 substrate Substances 0.000 description 25
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- 229910052581 Si3N4 Inorganic materials 0.000 description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 17
- 238000010586 diagram Methods 0.000 description 14
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- 238000000206 photolithography Methods 0.000 description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
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- 238000001312 dry etching Methods 0.000 description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
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- 230000003068 static effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000779 depleting effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
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- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
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- 238000012545 processing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Description
図1は、本実施の形態に係る、CMOSトランジスタと低耐圧パワーMOSトランジスタとを同一基板上に混載して形成した半導体装置の構造断面図を略示したものである。
図5は、本実施の形態に係る、半導体装置の構造断面図を略示したものである。CMOSトランジスタ領域については、上記した第1の実施の形態と同様なので説明を省略する。本実施の形態に係る半導体装置のパワーMOSトランジスタ60は、P−型半導体層2にP型ボディ領域61を有する点で、上記した第1の実施の形態のパワーMOSトランジスタ20と異なる。P型ボディ領域61は、ソース側のコンタクト領域22、ソース領域24、LDD領域25を包囲し、一部がゲート酸化膜31の下方にまで延在するように形成されている。したがって、ゲート酸化膜31の下方での不純物濃度は、ドレイン側よりもソース側の方が高くなっている。P型ボディ領域61の不純物濃度のピークは、ソース領域24が形成されている半導体層の表面よりもさらに深い位置にある。
図8は、本実施の形態に係る、半導体装置の構造断面図を略示したものである。CMOSトランジスタ領域については、上記した第1の実施の形態と同様なので説明を省略する。本実施の形態に係るパワーMOSトランジスタ70は、ドリフト領域が2層構造を有する点で、上記した第1の実施の形態のパワーMOSトランジスタ20と異なる。チャネル領域7’の右側(ドレイン側)すなわちLDD領域25と共にゲート電極27を挟む位置には、深さ方向に異なる不純物分布を有する2層構造のドリフト領域が形成されている。
以上、発明の実施の形態を説明したが、本発明はこれらに限定されるものではなく、発明の趣旨を逸脱しない範囲内において、種々の変更、追加等が可能である。例えば、パワーMOSトランジスタのサイドウォールを形成する絶縁膜は3層に限定されず、それ以上の膜が積層されて形成されてもよい。
半導体層内に、CMOSトランジスタと、パワーMOSトランジスタとが形成され、
CMOSトランジスタは、
半導体層上に第1の絶縁膜を介して形成された第1ゲート電極と、
半導体層の内部に、第1ゲート電極に対応して設けられた第1ソース領域と、
半導体層の内部に、第1ソース領域と共に第1ゲート電極を挟むように設けられた第1ドレイン領域とを備え、
パワーMOSトランジスタは、
半導体層上に第2の絶縁膜を介して形成された第2ゲート電と、
半導体層の内部に、第2ゲート電極に対応して設けられた第2ソース領域と、
半導体層の内部に、第2ソース領域と共に第2ゲート電極を挟むように設けられたドリフト領域と、
半導体層の内部に、ドリフト領域に隣接し、第2ソース領域と共に第2ゲート電極を挟むように設けられた第2ドレイン領域とを備え、
第1ゲート電極の側面には第1サイドウォールが設けられ、第2ゲート電極の側面には第2サイドウォールが設けられ、第1サイドウォールの上記第1の絶縁膜に沿った幅と、第2サイドウォールの上記第2の絶縁膜に沿った幅とが異なることを特徴とする。
半導体層上に第1絶縁膜を介して第1ゲート電極と、第2絶縁膜を介して第2ゲート電極とを形成する工程と、
半導体層の内部に、第1ゲート電極に対応して設けられた第1LDD領域、半導体層の内部に、第1LDD領域と共に第1ゲート電極を挟むように設けられた第2LDD領域、及び半導体層の内部に、第2ゲート電極に対応して設けられた第3LDD領域を不純物イオン注入処理により同時に形成する工程と、
半導体層の内部に、第3LDD領域と共に第2ゲート電極を挟むように設けられたドリフト領域を不純物イオン注入処理により形成する工程と、
半導体層の表面全体に多層絶縁膜を堆積する工程と、
CMOSトランジスタ側の多層絶縁膜の少なくとも一層を等方性エッチングにより除去する工程と、
パワーMOSトランジスタ側の多層絶縁膜の少なくとも一層を第1の異方性エッチングによりエッチバックする工程と、
多層絶縁膜の残りを第2の異方性エッチングによりエッチバックして、第1ゲート電極の側面には第1サイドウォールを、第2ゲート電極の側面には第2サイドウォールをそれぞれ形成する工程と、
第1サイドウォールをマスクに使って半導体層の内部に第1LDD領域に対応して設けられた第1ソース領域及び半導体層の内部に第1ソース領域と共に第1ゲート電極を挟むように第2LDD領域に対応して設けられた第1ドレイン領域を、第2サイドウォールをマスクに使って半導体層の内部に第3LDD領域に対応して設けられた第2ソース領域及び半導体層の内部に第2ソース領域とともに第2ゲート電極を挟むように第3LDD領域に対応して設けられた第2ドレイン領域を、イオン注入により同時に形成する工程と、
を備えることを特徴とする。
半導体層上に第1絶縁膜を介して第1ゲート電極と、第2絶縁膜を介して第2ゲート電極とを形成する工程と、
半導体層の内部に、第1ゲート電極に対応して設けられた第1LDD領域、半導体層の内部に、第1LDD領域と共に第1ゲート電極を挟むように設けられた第2LDD領域、及び半導体層の内部に、第2ゲート電極に対応して設けられた第3LDD領域を不純物イオン注入処理により同時に形成する工程と、
半導体層の内部に、第3LDD領域と共に第2ゲート電極を挟むように設けられたドリフト領域を不純物イオン注入処理により形成する工程と、
半導体層の表面全体に多層絶縁膜を堆積する工程と、
パワーMOSトランジスタ側の多層絶縁膜の少なくとも一層を第1の異方性エッチングによりエッチバックする工程と、
CMOSトランジスタ側の多層絶縁膜の少なくとも一層を等方性エッチングにより除去する工程と、
多層絶縁膜の残りを第2の異方性エッチングによりエッチバックして、第1ゲート電極の側面には第1サイドウォールを、第2ゲート電極の側面には第2サイドウォールをそれぞれ形成する工程と、
第1サイドウォールをマスクに使って半導体層の内部に第1LDD領域に対応して設けられた第1ソース領域及び半導体層の内部に第1ソース領域と共に第1ゲート電極を挟むように第2LDD領域に対応して設けられた第1ドレイン領域を、第2サイドウォールをマスクに使って半導体層の内部に第3LDD領域に隣接して位置する第2ソース領域及び半導体層の内部に第2ソース領域とともに第2ゲート電極を挟むように第3LDD領域に対応して設けられた第2ドレイン領域を、イオン注入により同時に形成する工程と、
を備えることを特徴とする。
第1の異方性エッチング及び第2の異方性エッチングはRIEであることを特徴とする。
Claims (4)
- 半導体層内に、CMOSトランジスタと、パワーMOSトランジスタとが形成され、
前記CMOSトランジスタは、
前記半導体層上に第1の絶縁膜を介して形成された第1ゲート電極と、
前記半導体層の内部に、前記第1ゲート電極に対応して設けられた第1ソース領域と、
前記半導体層の内部に、前記第1ソース領域に隣接すると共に前記第1ソース領域よりも前記第1ゲート電極の近くに設けられ、且つ前記第1ソース領域よりも低い不純物濃度を有する第1LDD領域と、
前記半導体層の内部に、前記第1ソース領域と共に前記第1ゲート電極を挟むように設けられた第1ドレイン領域と、
前記半導体層の内部に、前記第1ドレイン領域に隣接して前記第1ドレイン領域よりも前記第1ゲート電極の近くに位置し、前記第1LDD領域と共に前記第1ゲート電極を挟むように設けられ、且つ前記第1ドレイン領域よりも低い不純物濃度を有する第2LDD領域とを備え、
前記パワーMOSトランジスタは、
前記半導体層上に第2の絶縁膜を介して形成された第2ゲート電極と、
前記半導体層の内部に、前記第2ゲート電極に対応して設けられた第2ソース領域と、
前記半導体層の内部に、前記第2ソース領域に隣接すると共に前記第2ソース領域よりも前記第2ゲート電極の近くに設けられ、且つ前記第2ソース領域よりも低い不純物濃度を有する第3LDD領域と、
前記半導体層の内部に、前記第2ソース領域と共に前記第2ゲート電極を挟むように設けられた第2ドレイン領域と、
前記半導体層の内部に、前記第2ドレイン領域に隣接して前記第2ドレイン領域よりも前記第2ゲート電極の近くに位置し、前記第3LDD領域と共に前記第2ゲート電極を挟むように設けられ、且つ前記第2ドレイン領域及び前記第3LDD領域よりも低い不純物濃度を有するドリフト領域とを備え、
前記第1ゲート電極の側面には第1サイドウォールが設けられ、前記第2ゲート電極の側面には第2サイドウォールが設けられ、
前記第1サイドウォールは、前記第1LDD領域の上方及び前記第2LDD領域の上方に設けられ、
前記第2サイドウォールは、前記第3LDD領域の上方及び前記ドリフト領域の上方に設けられ、
前記第2サイドウォールの前記第2の絶縁膜に沿った幅は、前記第1サイドウォールの前記第1の絶縁膜に沿った幅より大きく、
前記第1サイドウォールの前記第1の絶縁膜に沿った幅は、前記第1LDD領域と前記第2LDD領域との前記第1の絶縁膜に沿った幅と対応し、
前記第2サイドウォールの前記第2の絶縁膜に沿った幅は、前記第3LDD領域と前記ドリフト領域との前記第2の絶縁膜に沿った幅と対応する
ことを特徴とする半導体装置。 - 前記パワーMOSトランジスタは、さらに、前記第2ソース領域を包囲するように設けられ、前記半導体層よりも不純物濃度が高いボディ領域を有し、前記ボディ領域は前記パワーMOSトランジスタの前記第2ゲート電極の下方まで延在していることを特徴とする請求項1に記載の半導体装置。
- 前記第1サイドウォール及び第2サイドウォールが、それぞれ多層膜構造から成ることを特徴とする請求項1または2に記載の半導体装置。
- 半導体層内に、CMOSトランジスタと、パワーMOSトランジスタとを含む半導体装置の製造方法において、
前記CMOSトランジスタが形成されるCMOSトランジスタ領域における前記半導体層上に第1の絶縁膜を介して第1ゲート電極を形成する工程と、
前記パワーMOSトランジスタが形成されるパワーMOSトランジスタ領域における前記半導体層上に第2の絶縁膜を介して第2ゲート電極を形成する工程と、
前記CMOSトランジスタ領域の前記半導体層に対してイオン注入を行い、前記半導体層内であって前記第1ゲート電極の一方の側面側の下方に第1LDD領域を形成し、前記半導体層内であって前記第1ゲート電極の他方の側面側の下方に第2LDD領域を形成する工程と、
前記パワーMOSトランジスタ領域において、前記第2ゲート電極の一方の側面側の前記半導体層に対して第1の注入量でイオン注入を行って第3LDD領域を形成すると共に、前記第2ゲート電極の他方の側面側の前記半導体層に対して前記第1の注入量よりも小さい第2の注入量でイオン注入を行って前記第3LDD領域よりも低い不純物濃度を有するドリフト領域を形成する工程と、
前記CMOSトランジスタ領域及び前記パワーMOSトランジスタ領域において前記半導体層の表面全体に多層絶縁膜を堆積する工程と、
前記CMOSトランジスタ領域の前記多層絶縁膜の少なくとも一層を等方性エッチングにより除去する工程と、
前記パワーMOSトランジスタ領域の前記多層絶縁膜の少なくとも一層を第1の異方性エッチングによりエッチバックする工程と、
前記CMOSトランジスタ領域及び前記パワーMOSトランジスタ領域において前記多層絶縁膜の残りの膜を第2の異方性エッチングによりエッチバックして、前記第1ゲート電極の側面に第1サイドウォールを形成すると共に前記第2ゲート電極の側面に前記第1サイドウォールよりも厚い第2サイドウォールを形成する工程と、
前記CMOSトランジスタ領域において前記第1サイドウォールをマスクとして前記第1LDD領域及び前記第2LDD領域にイオン注入を行い、前記第1LDD領域の一部及び前記第2LDD領域の一部に、それぞれ第1ソース領域及び第1ドレイン領域を形成する工程と、
前記パワーMOSトランジスタ領域において前記第2サイドウォールをマスクとして前記第3LDD領域及び前記ドリフト領域にイオン注入を行い、前記第3LDD領域の一部及び前記ドリフト領域の一部に、それぞれ第2ソース領域及び第2ドレイン領域を形成する工程と
を含むことを特徴とする半導体装置の製造方法。
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US8084827B2 (en) * | 2009-03-27 | 2011-12-27 | National Semiconductor Corporation | Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses |
JP2011009695A (ja) * | 2009-05-29 | 2011-01-13 | Toshiba Corp | 不揮発性半導体記憶装置及びディプレッション型mosトランジスタ |
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US8525257B2 (en) | 2009-11-18 | 2013-09-03 | Micrel, Inc. | LDMOS transistor with asymmetric spacer as gate |
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US8476127B2 (en) * | 2010-10-28 | 2013-07-02 | Texas Instruments Incorporated | Integrated lateral high voltage MOSFET |
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