US20090020813A1 - Formation of lateral trench fets (field effect transistors) using steps of ldmos (lateral double-diffused metal oxide semiconductor) technology - Google Patents
Formation of lateral trench fets (field effect transistors) using steps of ldmos (lateral double-diffused metal oxide semiconductor) technology Download PDFInfo
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- US20090020813A1 US20090020813A1 US11/778,428 US77842807A US2009020813A1 US 20090020813 A1 US20090020813 A1 US 20090020813A1 US 77842807 A US77842807 A US 77842807A US 2009020813 A1 US2009020813 A1 US 2009020813A1
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- 230000015572 biosynthetic process Effects 0.000 title description 12
- 229910044991 metal oxide Inorganic materials 0.000 title description 4
- 150000004706 metal oxides Chemical class 0.000 title description 4
- 230000005669 field effect Effects 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000002019 doping agent Substances 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 15
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 22
- 238000007796 conventional method Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 9
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- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
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- 230000004048 modification Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Definitions
- the present invention relates generally to lateral trench FETs (Field Effect Transistors) and more particularly to formation of the lateral trench FETs using step of LDMOS (Lateral double-Diffused Metal Oxide Semiconductor) technology.
- LDMOS Longeral double-Diffused Metal Oxide Semiconductor
- LDMOS Longeral double-Diffused Metal Oxide Semiconductor
- high voltage power devices on the same wafer. Therefore, there is a need for a method for forming the LDMOS and the high voltage power devices on the same wafer that requires fewer steps than in the prior art.
- the present invention provides a semiconductor structure, comprising (a) a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface; (b) a first transistor on the semiconductor substrate; and (c) a second transistor on the semiconductor substrate, wherein a first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped Source/Drain portion of the second transistor in the reference direction are essentially the same, wherein the first doped transistor region is not a portion of a Source/Drain region of the first transistor, wherein a first gate electrode region of the first transistor is on a first side of the top substrate surface, wherein a second gate electrode region of the second transistor is on a second side of the top substrate surface, and wherein the first side and the second side are opposite sides of the top substrate surface.
- the present invention provides a method for forming the LDMOS and the high voltage power devices on the same wafer that requires fewer steps than in the prior art.
- FIGS. 1A-1H show cross-section views used to illustrate a fabrication process of a first semiconductor structure, in accordance with embodiments of the present invention.
- FIGS. 2A-2D show cross-section views used to illustrate a fabrication process of a second semiconductor structure, in accordance with embodiments of the present invention.
- FIGS. 3A-3B show cross-section views used to illustrate a fabrication process of a third semiconductor structure, in accordance with embodiments of the present invention.
- FIG. 4 shows a cross-section view of a fourth semiconductor structure, in accordance with embodiments of the present invention.
- FIG. 5 shows a cross-section view of a fifth semiconductor structure, in accordance with embodiments of the present invention.
- FIG. 6 shows a cross-section view of a sixth semiconductor structure, in accordance with embodiments of the present invention.
- FIGS. 1A-1H show cross-section views used to illustrate a fabrication process of a semiconductor structure 100 , in accordance with embodiments of the present invention. More specifically, with reference to FIG. 1A , the fabrication process of the semiconductor structure 100 starts with a P-substrate 110 .
- the P-substrate 110 comprises silicon doped with p-type dopants (e.g., boron atoms).
- p-type dopants e.g., boron atoms
- a deep trench 111 is formed in the P-substrate 110 .
- the deep trench 111 can be formed by a conventional method.
- a dielectric layer 112 and a poly-silicon region 114 are formed in the deep trench 111 .
- the dielectric layer 112 can comprise silicon dioxide.
- the dielectric layer 112 and the poly-silicon region 114 can be formed by (i) depositing a dielectric layer on top of the semiconductor structure 100 of FIG. 1A , (ii) depositing a poly-silicon layer on top of the dielectric layer such that the deep trench 111 is filled with poly-silicon, and then (iii) removing portions of the dielectric layer and the poly-silicon layer outside the deep trench 111 resulting in the dielectric layer 112 and the poly-silicon region 114 .
- the dielectric layer 112 and the poly-silicon region 114 can be collectively referred to as a deep trench isolation region 112 + 114 .
- N ⁇ regions 120 , 120 a , and 120 b are formed in the P-substrate 110 .
- the N ⁇ regions 120 , 120 a , and 120 b can comprise n-type dopants (e.g., arsenic atoms).
- the N ⁇ regions 120 , 120 a , and 120 b can be formed by (i) forming a photoresist layer (not shown) on top of the structure 100 of FIG.
- a depth 121 of the N ⁇ region 120 and a depth 121 ′ of the N ⁇ regions 120 a and 120 b are equal.
- the depth 121 of the N ⁇ region 120 is the vertical distance from the top surface 115 of the substrate 110 to the bottom surface 125 of the N ⁇ region 120 .
- the depth 121 ′ of the N ⁇ regions 120 a and 120 b is a vertical distance from the top surface 115 of the substrate 110 to the bottom surface 125 ′ of the N ⁇ region 120 b .
- a depth 112 ′ of the deep trench isolation region 112 + 114 is a vertical distance from the top surface 115 of the substrate 110 to the bottom surface 112 b of the dielectric layer 112 (the depth 112 ′ is also considered the depth 112 ′ of the dielectric layer 112 ). In one embodiment, the depth 112 ′ is greater than the depth 121 . In one embodiment, for illustration, the depth 112 ′ is also considered the depth of the poly-silicon region 114 .
- doping concentrations with respect to the depth (i.e., in the reference direction 127 which is perpendicular to the top surface 115 of the substrate 110 ) in the N ⁇ region 120 and the N ⁇ regions 120 a and 120 b have the same doping profile.
- the doping profile of the N ⁇ region 120 is the dopant concentration of the N ⁇ region 120 distributed along the depth 121 of the N ⁇ region 120 .
- the doping profiles of the N ⁇ regions 120 a and 120 b are the dopant concentrations of the N ⁇ regions 120 a and 120 b distributed along the depth 121 ′ of the N ⁇ regions 120 a and 120 b.
- N+ regions 116 , 116 a , and 116 b are formed in the P-substrate 110 .
- the N+ regions 116 , 116 a , and 116 b can comprise n-type dopants.
- the N+ regions 116 , 116 a , 116 b can be formed by (i) forming a photoresist layer (not shown) on top of the structure 100 of FIG.
- a P-body region 130 is formed in the N ⁇ region 120 .
- the P-body region 130 comprises p-type dopants.
- the P-body region 130 can be formed in a manner similar to the manner in which the N ⁇ region 120 of FIG. 1C is formed (i.e., selective ion implantation).
- STI (shallow trench isolation) regions 118 are formed in the P-substrate 110 .
- the STI regions 118 can comprise silicon dioxide.
- the STI regions 118 can be formed by (i) forming a photoresist layer (not shown) on top of the structure 100 of FIG. 1E , (ii) patterning the photoresist layer, (iii) anisotropically etching the semiconductor structure 100 using the patterned photoresist layer as a blocking mask resulting in shallow trenches 118 , and then (iv) filling back the shallow trenches with silicon dioxide resulting in the STI regions 118 .
- an N ⁇ region 132 is formed in the P-body region 130 .
- the N ⁇ region 132 comprises n-type dopants.
- the N ⁇ region 132 can be formed by a selective ion implantation process.
- the ion implantation process that forms the N ⁇ regions 132 also implants n-type dopants into the N+ regions 116 a and 116 b resulting in N+ regions 132 a and 132 b .
- the N+ regions 132 a and 132 b comprise n-type dopants from two separate ion implantation processes that form the N ⁇ region 132 and the N+ regions 116 a and 116 b.
- a gate dielectric region 140 and a gate electrode region 150 are formed on top of the P-body region 130 .
- the gate dielectric region 140 can comprise silicon dioxide.
- the gate electrode region 150 can comprise poly-silicon.
- the gate dielectric region 140 and the gate electrode region 150 can be formed by a conventional method.
- an extension region 131 is formed in the P-body region 130 .
- the extension region 131 comprises n-type dopants.
- the extension region 131 can be formed by a conventional method.
- spacer regions 160 are formed on side walls of the gate dielectric region 140 and the gate electrode region 150 .
- the spacer regions 160 can comprise silicon nitride.
- the spacer regions 160 can be formed by a conventional method.
- a P+ region 134 , N+ regions 136 , 136 ′, 136 a , and 136 b are formed in the semiconductor structure 100 .
- the P+ region 134 comprises p-type dopants.
- the N+ regions 136 , 136 ′, 136 a , and 136 b comprise n-type dopants.
- the P+ region 134 and the N+ regions 136 , 136 ′, 136 a , and 136 b can be formed by a conventional method. More specifically, in one embodiment, the N+ regions 136 , 136 ′, 136 a , and 136 b can be formed by an ion implantation process.
- silicide regions 170 are formed on the P+ region 134 and the N+ regions 136 , 136 ′, 136 a , and 136 b .
- the silicide regions 170 can be formed by a conventional method.
- a dielectric layer (not shown) is formed on top of the structure 100 of FIG. 1H .
- contact regions (not shown) are formed in the dielectric layer to provide electrical access to the silicide regions 170 .
- a structure 180 of the semiconductor structure 100 of FIG. 1H is an LDMOS (Lateral double-Diffused Metal Oxide Semiconductor) transistor 180
- a structure 190 of FIG. 1H serves as a lateral trench FET (Field Effect Transistor) 190 .
- the lateral trench FET 190 includes a channel region 119 , a first Source/Drain region 120 a + 116 a + 132 a + 136 a , a second Source/Drain region 120 b + 116 b + 132 b + 136 b , a gate dielectric layer 112 , and a gate electrode region 114 .
- the lateral trench FET 190 is on, there is an electric current flowing between the first and second Source/Drain regions through the channel region 119 .
- regions of the lateral trench FET 190 are formed using steps in the fabrication process of the LDMOS transistor 180 .
- the lateral trench FET 190 can serve as a high voltage power device that has a breakdown voltage in the range from 120V to 150V.
- FIGS. 2A-2D show cross-section views used to illustrate a fabrication process of a semiconductor structure 200 , in accordance with embodiments of the present invention. More specifically, with reference to FIG. 2A , the fabrication process of the semiconductor structure 200 starts with the semiconductor structure 200 of FIG. 2A .
- the semiconductor structure 200 of FIG. 2A is similar to the semiconductor structure 100 of FIG. 1F .
- the formation of the structure 200 of FIG. 2A is similar to the formation of the structure 100 of FIG. 1F .
- a poly-silicon region 214 is formed in the STI region 118 such that the poly-silicon region 214 and the poly-silicon region 114 constitute a poly-silicon region 214 + 114 .
- the poly-silicon region 214 can be formed by a conventional method.
- a silicon germanium region 280 is formed on top of and in direct physical contact with the poly-silicon region 214 + 114 .
- the silicon germanium region 280 can be formed by selective epitaxial growth.
- the gate dielectric region 140 , the gate electrode region 150 , and the extension region 131 are formed on the P-body region 130 .
- the gate dielectric region 140 , the gate electrode region 150 , and the extension region 131 can be formed in a manner similar to the manner in which the gate dielectric region 140 , the gate electrode region 150 , and the extension region 131 of FIG. 1G are formed.
- the spacer regions 160 , the P+ region 134 , and the N+ regions 136 , 136 ′, 136 a , and 136 b are formed on the structure 200 of FIG. 2C .
- the spacer regions 160 , the P+ region 134 , the N+ regions 136 , 136 ′, 136 a , and 136 b , and silicide regions 170 can be formed in a manner similar to the manner in which these regions are formed in FIG. 1H .
- silicide regions 170 are formed on the P+ region 134 , the N+ regions 136 , 136 ′, 136 a , and 136 b , and the silicon germanium region 280 .
- the silicide regions 170 can be formed by a conventional method.
- a structure 290 of the semiconductor structure 200 of FIG. 2D serve as a lateral trench FET 290 .
- the lateral trench FET 290 is similar to the lateral trench FET 190 of FIG. 1H except that the lateral trench 290 farther comprises the silicon germanium region 280 which is electrically coupled to the poly-silicon region 214 + 114 .
- the poly-silicon region 214 + 114 and the silicon germanium region 280 collectively serve as a gate electrode of the lateral trench FET 290 .
- FIGS. 3A-3B show cross-section views used to illustrate a fabrication process of a semiconductor structure 300 , in accordance with embodiments of the present invention. More specifically, with reference to FIG. 3A , the fabrication process of the semiconductor structure 300 starts with the semiconductor structure 300 of FIG. 3A .
- the structure 300 of FIG. 3A is similar to the structure 100 of FIG. 1H except that the structure 300 do not comprise the deep trench isolation region 112 + 114 .
- the formation of the structure 300 of FIG. 3A is similar to the formation of the structure 100 of FIG. 1H except that the formation of the structure 300 do not comprise the formation of the deep trench isolation region 112 + 114 .
- a trench isolation region 312 + 314 is formed in the P-substrate 110 .
- the trench isolation region 312 + 314 can be formed by a conventional method.
- a depth 312 ′ of the trench isolation region 312 + 314 is a vertical distance from the top surface 115 of the substrate 110 to the bottom surface 312 b of the dielectric layer 312 (the depth 312 ′ is also considered the depth 312 ′ of the dielectric layer 312 ).
- the depth 312 ′ is less than the depth 112 ′.
- the depth 312 ′ is also considered the depth of the poly-silicon region 114 .
- a structure 390 of the semiconductor structure 300 of FIG. 3B serve as a lateral trench FET 390 .
- the lateral trench FET 390 includes a channel region 319 , a first Source/Drain region 120 a + 116 a + 132 a + 136 a , a second Source/Drain region 120 b + 116 b + 132 b + 136 b , a gate dielectric layer 312 , and a gate electrode region 314 .
- the lateral trench FET 390 When the lateral trench FET 390 is on, there is an electric current flowing between the first and second Source/Drain regions through the channel region 319 .
- FIG. 4 shows a cross-section view of a semiconductor structure 400 , in accordance with embodiments of the present invention.
- the semiconductor structure 400 comprises an LDMOS transistor 480 and a lateral trench FET 490 .
- the lateral trench FET 490 includes a channel region 419 , a first Source/Drain region 420 a + 416 a + 424 a + 428 a , a second Source/Drain region 420 b + 416 b + 424 b + 428 b , a gate dielectric layer 412 , and a gate electrode region 414 .
- the lateral trench FET 490 When the lateral trench FET 490 is on, there is an electric current flowing between the first and second Source/Drain regions through the channel region 419 .
- the LDMOS transistor 480 is formed by a conventional method.
- the first and second Source/Drain regions 420 a + 416 a + 424 a + 428 a and 420 b + 416 b + 424 b + 428 b of the lateral trench FET 490 are formed using steps in the fabrication process of the LDMOS transistor 480 .
- the formation of a deep trench isolation region 412 + 414 is similar to the formation of the deep trench isolation region 112 + 114 of FIG. 1H .
- the deep trench isolation region 412 + 414 is formed before the LDMOS transistor 480 , the first and second Source/Drain regions 420 a + 416 a + 424 a + 428 a and 420 b + 416 b + 424 b + 428 b of the lateral trench FET 490 , and the STI regions 429 are formed.
- a poly-silicon region 514 , a silicon germanium region 580 , and a silicide region 560 are formed on the structure 400 of FIG. 4 resulting in the semiconductor structure 400 of FIG. 5 .
- the poly-silicon region 514 , the silicon germanium region 580 , and a silicide region 560 can be formed by a conventional method.
- a lateral trench FET 590 of FIG. 5 is similar to the lateral trench FET 490 of FIG. 4 except that the lateral trench FET 590 comprises the poly-silicon region 514 and the silicon germanium region 580 .
- the poly-silicon regions 514 and 414 and the silicon germanium region 580 collectively serve as a gate electrode region 514 + 414 + 580 .
- FIG. 6 shows a cross-section view of a semiconductor structure 600 , in accordance with embodiments of the present invention. More specifically, the semiconductor structure 600 comprises the LDMOS transistor 480 and a lateral trench FET 690 .
- the lateral trench FET 690 includes a channel region 619 , a first Source/Drain region 420 a + 416 a + 424 a + 428 a , a second Source/Drain region 420 b + 416 b + 424 b + 428 b , a gate dielectric layer 612 , and a gate electrode 614 .
- the first and second Source/Drain region 420 a + 416 a + 424 a + 428 a and 420 b + 416 b + 424 b + 428 b of the lateral trench FET 690 are formed using steps in the fabrication process of the LDMOS transistor 480 .
- the formation of a trench isolation region 612 + 614 which serves as the gate dielectric layer 612 and the gate electrode 614 is similar to the formation of the trench isolation region 312 + 314 of FIG. 3B .
- the trench isolation region 612 + 614 can be formed (i) after the first and second Source/Drain region 420 a + 416 a + 424 a + 428 a and 420 b + 416 b + 424 b + 428 b and the STI regions 429 are formed and (ii) before the gate dielectric 430 , the gate electrode 440 , the spacer regions 450 , and the silicide regions 460 are formed.
- the first and second Source/Drain regions of the lateral trench FETs 190 , 290 , and 390 of FIGS. 1H , 2 D, and 3 B are formed using steps in the fabrication processes for forming the LDMOS transistors 180 of FIGS. 1H , 2 D, and 3 B.
- the first and second Source/Drain regions of the lateral trench FETs 490 , 590 , and 690 of FIGS. 4-6 are formed using steps in the fabrication processes for forming the LDMOS transistors 480 of FIGS. 4-6 .
- the lateral trench FETs 190 , 290 , 390 , 490 , 590 , and 690 can serve as high voltage power devices that have breakdown voltages in the range from 120V to 150V.
Abstract
Description
- The present invention relates generally to lateral trench FETs (Field Effect Transistors) and more particularly to formation of the lateral trench FETs using step of LDMOS (Lateral double-Diffused Metal Oxide Semiconductor) technology.
- In semiconductor technology, there is a need for LDMOS (Lateral double-Diffused Metal Oxide Semiconductor) and high voltage power devices on the same wafer. Therefore, there is a need for a method for forming the LDMOS and the high voltage power devices on the same wafer that requires fewer steps than in the prior art.
- The present invention provides a semiconductor structure, comprising (a) a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface; (b) a first transistor on the semiconductor substrate; and (c) a second transistor on the semiconductor substrate, wherein a first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped Source/Drain portion of the second transistor in the reference direction are essentially the same, wherein the first doped transistor region is not a portion of a Source/Drain region of the first transistor, wherein a first gate electrode region of the first transistor is on a first side of the top substrate surface, wherein a second gate electrode region of the second transistor is on a second side of the top substrate surface, and wherein the first side and the second side are opposite sides of the top substrate surface.
- The present invention provides a method for forming the LDMOS and the high voltage power devices on the same wafer that requires fewer steps than in the prior art.
-
FIGS. 1A-1H show cross-section views used to illustrate a fabrication process of a first semiconductor structure, in accordance with embodiments of the present invention. -
FIGS. 2A-2D show cross-section views used to illustrate a fabrication process of a second semiconductor structure, in accordance with embodiments of the present invention. -
FIGS. 3A-3B show cross-section views used to illustrate a fabrication process of a third semiconductor structure, in accordance with embodiments of the present invention. -
FIG. 4 shows a cross-section view of a fourth semiconductor structure, in accordance with embodiments of the present invention. -
FIG. 5 shows a cross-section view of a fifth semiconductor structure, in accordance with embodiments of the present invention. -
FIG. 6 shows a cross-section view of a sixth semiconductor structure, in accordance with embodiments of the present invention. -
FIGS. 1A-1H show cross-section views used to illustrate a fabrication process of asemiconductor structure 100, in accordance with embodiments of the present invention. More specifically, with reference toFIG. 1A , the fabrication process of thesemiconductor structure 100 starts with a P-substrate 110. The P-substrate 110 comprises silicon doped with p-type dopants (e.g., boron atoms). Next, adeep trench 111 is formed in the P-substrate 110. Thedeep trench 111 can be formed by a conventional method. - Next, with reference to
FIG. 1B , in one embodiment, adielectric layer 112 and a poly-silicon region 114 are formed in thedeep trench 111. Thedielectric layer 112 can comprise silicon dioxide. Thedielectric layer 112 and the poly-silicon region 114 can be formed by (i) depositing a dielectric layer on top of thesemiconductor structure 100 ofFIG. 1A , (ii) depositing a poly-silicon layer on top of the dielectric layer such that thedeep trench 111 is filled with poly-silicon, and then (iii) removing portions of the dielectric layer and the poly-silicon layer outside thedeep trench 111 resulting in thedielectric layer 112 and the poly-silicon region 114. It should be noted that thedielectric layer 112 and the poly-silicon region 114 can be collectively referred to as a deep trench isolation region 112+114. - Next, with reference to
FIG. 1C , in one embodiment, N−regions substrate 110. The N−regions regions structure 100 ofFIG. 1B , (ii) patterning the photoresist layer, and (iii) ion implanting n-type dopants by an ion implantation process into thesemiconductor structure 100 with the patterned photoresist layer as a blocking mask resulting in the N−regions structure 100 ofFIG. 1C . - As a result of the N−
region 120 and the N−regions depth 121 of the N−region 120 and adepth 121′ of the N−regions depth 121 of the N−region 120 is the vertical distance from thetop surface 115 of thesubstrate 110 to thebottom surface 125 of the N−region 120. Thedepth 121′ of the N−regions top surface 115 of thesubstrate 110 to thebottom surface 125′ of the N−region 120 b. Similarly, adepth 112′ of the deep trench isolation region 112+114 is a vertical distance from thetop surface 115 of thesubstrate 110 to thebottom surface 112 b of the dielectric layer 112 (thedepth 112′ is also considered thedepth 112′ of the dielectric layer 112). In one embodiment, thedepth 112′ is greater than thedepth 121. In one embodiment, for illustration, thedepth 112′ is also considered the depth of the poly-silicon region 114. - Also as a result of the N−
region 120 and the N−regions reference direction 127 which is perpendicular to thetop surface 115 of the substrate 110) in the N−region 120 and the N−regions region 120 is the dopant concentration of the N−region 120 distributed along thedepth 121 of the N−region 120. The doping profiles of the N−regions regions depth 121′ of the N−regions - Next, with reference to
FIG. 1D , in one embodiment,N+ regions substrate 110. TheN+ regions N+ regions structure 100 ofFIG. 1B , (ii) patterning the photoresist layer, and (iii) ion implanting n-type dopants by an ion implantation process into thesemiconductor structure 100 with the patterned photoresist layer as a blocking mask resulting in theN+ regions structure 100 ofFIG. 1D . TheN+ regions N+ regions regions - Next, with reference to
FIG. 1E , in one embodiment, a P-body region 130 is formed in the N−region 120. The P-body region 130 comprises p-type dopants. The P-body region 130 can be formed in a manner similar to the manner in which the N−region 120 ofFIG. 1C is formed (i.e., selective ion implantation). - Next, with reference to
FIG. 1F , in one embodiment, STI (shallow trench isolation)regions 118 are formed in the P-substrate 110. TheSTI regions 118 can comprise silicon dioxide. TheSTI regions 118 can be formed by (i) forming a photoresist layer (not shown) on top of thestructure 100 ofFIG. 1E , (ii) patterning the photoresist layer, (iii) anisotropically etching thesemiconductor structure 100 using the patterned photoresist layer as a blocking mask resulting inshallow trenches 118, and then (iv) filling back the shallow trenches with silicon dioxide resulting in theSTI regions 118. - Next, an N−
region 132 is formed in the P-body region 130. The N−region 132 comprises n-type dopants. The N−region 132 can be formed by a selective ion implantation process. In one embodiment, the ion implantation process that forms the N−regions 132 also implants n-type dopants into theN+ regions N+ regions N+ regions region 132 and theN+ regions - Next, with reference to
FIG. 1G , in one embodiment, agate dielectric region 140 and agate electrode region 150 are formed on top of the P-body region 130. Thegate dielectric region 140 can comprise silicon dioxide. Thegate electrode region 150 can comprise poly-silicon. Thegate dielectric region 140 and thegate electrode region 150 can be formed by a conventional method. - Next, in one embodiment, an
extension region 131 is formed in the P-body region 130. Theextension region 131 comprises n-type dopants. Theextension region 131 can be formed by a conventional method. - Next, with reference to
FIG. 1H , in one embodiment,spacer regions 160 are formed on side walls of thegate dielectric region 140 and thegate electrode region 150. Thespacer regions 160 can comprise silicon nitride. Thespacer regions 160 can be formed by a conventional method. - Next, in one embodiment, a
P+ region 134,N+ regions semiconductor structure 100. TheP+ region 134 comprises p-type dopants. TheN+ regions P+ region 134 and theN+ regions N+ regions - Next, in one embodiment,
silicide regions 170 are formed on theP+ region 134 and theN+ regions silicide regions 170 can be formed by a conventional method. - Next, in one embodiment, a dielectric layer (not shown) is formed on top of the
structure 100 ofFIG. 1H . Then, contact regions (not shown) are formed in the dielectric layer to provide electrical access to thesilicide regions 170. - It should be noted that a
structure 180 of thesemiconductor structure 100 ofFIG. 1H is an LDMOS (Lateral double-Diffused Metal Oxide Semiconductor)transistor 180, whereas astructure 190 ofFIG. 1H serves as a lateral trench FET (Field Effect Transistor) 190. Thelateral trench FET 190 includes achannel region 119, a first Source/Drain region 120 a+116 a+132 a+136 a, a second Source/Drain region 120 b+116 b+132 b+136 b, agate dielectric layer 112, and agate electrode region 114. When thelateral trench FET 190 is on, there is an electric current flowing between the first and second Source/Drain regions through thechannel region 119. - It should be noted that regions of the lateral trench FET 190 (except the
gate dielectric layer 112 and the gate electrode region 114) are formed using steps in the fabrication process of theLDMOS transistor 180. Thelateral trench FET 190 can serve as a high voltage power device that has a breakdown voltage in the range from 120V to 150V. -
FIGS. 2A-2D show cross-section views used to illustrate a fabrication process of asemiconductor structure 200, in accordance with embodiments of the present invention. More specifically, with reference toFIG. 2A , the fabrication process of thesemiconductor structure 200 starts with thesemiconductor structure 200 ofFIG. 2A . Thesemiconductor structure 200 ofFIG. 2A is similar to thesemiconductor structure 100 ofFIG. 1F . The formation of thestructure 200 ofFIG. 2A is similar to the formation of thestructure 100 ofFIG. 1F . - Next, with reference to
FIG. 2B , in one embodiment, a poly-silicon region 214 is formed in theSTI region 118 such that the poly-silicon region 214 and the poly-silicon region 114 constitute a poly-silicon region 214+114. The poly-silicon region 214 can be formed by a conventional method. - Next, with reference to
FIG. 2C , in one embodiment, asilicon germanium region 280 is formed on top of and in direct physical contact with the poly-silicon region 214+114. Thesilicon germanium region 280 can be formed by selective epitaxial growth. - Next, in one embodiment, the
gate dielectric region 140, thegate electrode region 150, and theextension region 131 are formed on the P-body region 130. Thegate dielectric region 140, thegate electrode region 150, and theextension region 131 can be formed in a manner similar to the manner in which thegate dielectric region 140, thegate electrode region 150, and theextension region 131 ofFIG. 1G are formed. - Next, with reference to
FIG. 2D , in one embodiment, thespacer regions 160, theP+ region 134, and theN+ regions structure 200 ofFIG. 2C . Thespacer regions 160, theP+ region 134, theN+ regions silicide regions 170 can be formed in a manner similar to the manner in which these regions are formed inFIG. 1H . - Next, in one embodiment,
silicide regions 170 are formed on theP+ region 134, theN+ regions silicon germanium region 280. Thesilicide regions 170 can be formed by a conventional method. - It should be noted that a
structure 290 of thesemiconductor structure 200 ofFIG. 2D serve as alateral trench FET 290. With reference toFIGS. 1H and 2D , thelateral trench FET 290 is similar to thelateral trench FET 190 ofFIG. 1H except that thelateral trench 290 farther comprises thesilicon germanium region 280 which is electrically coupled to the poly-silicon region 214+114. The poly-silicon region 214+114 and thesilicon germanium region 280 collectively serve as a gate electrode of thelateral trench FET 290. -
FIGS. 3A-3B show cross-section views used to illustrate a fabrication process of asemiconductor structure 300, in accordance with embodiments of the present invention. More specifically, with reference toFIG. 3A , the fabrication process of thesemiconductor structure 300 starts with thesemiconductor structure 300 ofFIG. 3A . Thestructure 300 ofFIG. 3A is similar to thestructure 100 ofFIG. 1H except that thestructure 300 do not comprise the deep trench isolation region 112+114. The formation of thestructure 300 ofFIG. 3A is similar to the formation of thestructure 100 ofFIG. 1H except that the formation of thestructure 300 do not comprise the formation of the deep trench isolation region 112+114. - Next, with reference to
FIG. 3B , in one embodiment, a trench isolation region 312+314 is formed in the P-substrate 110. The trench isolation region 312+314 can be formed by a conventional method. Adepth 312′ of the trench isolation region 312+314 is a vertical distance from thetop surface 115 of thesubstrate 110 to thebottom surface 312 b of the dielectric layer 312 (thedepth 312′ is also considered thedepth 312′ of the dielectric layer 312). In one embodiment, thedepth 312′ is less than thedepth 112′. In one embodiment, for illustration, thedepth 312′ is also considered the depth of the poly-silicon region 114. - It should be noted that a
structure 390 of thesemiconductor structure 300 ofFIG. 3B serve as alateral trench FET 390. Thelateral trench FET 390 includes achannel region 319, a first Source/Drain region 120 a+116 a+132 a+136 a, a second Source/Drain region 120 b+116 b+132 b+136 b, agate dielectric layer 312, and agate electrode region 314. When thelateral trench FET 390 is on, there is an electric current flowing between the first and second Source/Drain regions through thechannel region 319. -
FIG. 4 shows a cross-section view of asemiconductor structure 400, in accordance with embodiments of the present invention. More specifically, thesemiconductor structure 400 comprises anLDMOS transistor 480 and alateral trench FET 490. Thelateral trench FET 490 includes achannel region 419, a first Source/Drain region 420 a+416 a+424 a+428 a, a second Source/Drain region 420 b+416 b+424 b+428 b, agate dielectric layer 412, and agate electrode region 414. When thelateral trench FET 490 is on, there is an electric current flowing between the first and second Source/Drain regions through thechannel region 419. - In one embodiment, the
LDMOS transistor 480 is formed by a conventional method. In one embodiment, the first and second Source/Drain regions 420 a+416 a+424 a+428 a and 420 b+416 b+424 b+428 b of thelateral trench FET 490 are formed using steps in the fabrication process of theLDMOS transistor 480. The formation of a deep trench isolation region 412+414 is similar to the formation of the deep trench isolation region 112+114 ofFIG. 1H . More specifically, the deep trench isolation region 412+414 is formed before theLDMOS transistor 480, the first and second Source/Drain regions 420 a+416 a+424 a+428 a and 420 b+416 b+424 b+428 b of thelateral trench FET 490, and theSTI regions 429 are formed. - With reference to
FIG. 5 , in one embodiment, a poly-silicon region 514, asilicon germanium region 580, and asilicide region 560 are formed on thestructure 400 ofFIG. 4 resulting in thesemiconductor structure 400 ofFIG. 5 . The poly-silicon region 514, thesilicon germanium region 580, and asilicide region 560 can be formed by a conventional method. Alateral trench FET 590 ofFIG. 5 is similar to thelateral trench FET 490 ofFIG. 4 except that thelateral trench FET 590 comprises the poly-silicon region 514 and thesilicon germanium region 580. The poly-silicon regions silicon germanium region 580 collectively serve as a gate electrode region 514+414+580. -
FIG. 6 shows a cross-section view of asemiconductor structure 600, in accordance with embodiments of the present invention. More specifically, thesemiconductor structure 600 comprises theLDMOS transistor 480 and alateral trench FET 690. Thelateral trench FET 690 includes achannel region 619, a first Source/Drain region 420 a+416 a+424 a+428 a, a second Source/Drain region 420 b+416 b+424 b+428 b, agate dielectric layer 612, and agate electrode 614. In one embodiment, the first and second Source/Drain region 420 a+416 a+424 a+428 a and 420 b+416 b+424 b+428 b of thelateral trench FET 690 are formed using steps in the fabrication process of theLDMOS transistor 480. The formation of a trench isolation region 612+614 which serves as thegate dielectric layer 612 and thegate electrode 614 is similar to the formation of the trench isolation region 312+314 ofFIG. 3B . More specifically, the trench isolation region 612+614 can be formed (i) after the first and second Source/Drain region 420 a+416 a+424 a+428 a and 420 b+416 b+424 b+428 b and theSTI regions 429 are formed and (ii) before thegate dielectric 430, thegate electrode 440, thespacer regions 450, and thesilicide regions 460 are formed. - In summary, the first and second Source/Drain regions of the
lateral trench FETs FIGS. 1H , 2D, and 3B are formed using steps in the fabrication processes for forming theLDMOS transistors 180 ofFIGS. 1H , 2D, and 3B. The first and second Source/Drain regions of thelateral trench FETs FIGS. 4-6 are formed using steps in the fabrication processes for forming theLDMOS transistors 480 ofFIGS. 4-6 . Thelateral trench FETs - While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims (20)
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US11/778,428 US20090020813A1 (en) | 2007-07-16 | 2007-07-16 | Formation of lateral trench fets (field effect transistors) using steps of ldmos (lateral double-diffused metal oxide semiconductor) technology |
US12/640,192 US8143671B2 (en) | 2007-07-16 | 2009-12-17 | Lateral trench FETs (field effect transistors) |
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US12/640,192 Expired - Fee Related US8143671B2 (en) | 2007-07-16 | 2009-12-17 | Lateral trench FETs (field effect transistors) |
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