KR20050101615A - Method for manufacturing high voltage transistor - Google Patents
Method for manufacturing high voltage transistor Download PDFInfo
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- KR20050101615A KR20050101615A KR1020040026545A KR20040026545A KR20050101615A KR 20050101615 A KR20050101615 A KR 20050101615A KR 1020040026545 A KR1020040026545 A KR 1020040026545A KR 20040026545 A KR20040026545 A KR 20040026545A KR 20050101615 A KR20050101615 A KR 20050101615A
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000004904 shortening Methods 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 동작 저항(On Resistance)을 감소시키고, 공정 수를 단축시키기 위한 고전압 트랜지스터 제조방법을 개시한다. 개시된 본 발명의 방법은, 반도체 기판의 소정부분을 선택적으로 식각하여 트렌치를 형성하는 단계; 상기 반도체 기판에 고전압 웰을 형성하는 단계; 상기 고전압 웰 내에 선택적인 저농도 불순물 도핑으로 드리프트 영역을 형성하는 단계; 상기 트렌치를 포함한 기판 전면에 게이트 산화막을 형성하는 단계; 상기 결과물에 문턱전압 이온주입 공정을 실시하는 단계; 상기 게이트 산화막 상에 폴리실리콘막을 형성하여 상기 트렌치를 매립시키는 단계; 상기 반도체 기판이 노출될 때까지 상기 결과물을 평탄화시켜 상기 트렌치 내에 게이트 전극을 형성하는 단계; 및 상기 게이트 전극 양측의 기판에 선택적인 고농도 불순물 도핑으로 소오스/드레인 영역을 형성하는 단계를 포함한다.The present invention discloses a method of manufacturing a high voltage transistor for reducing On Resistance and shortening the number of processes. The disclosed method includes selectively etching a portion of a semiconductor substrate to form a trench; Forming a high voltage well on the semiconductor substrate; Forming a drift region with selective low concentration impurity doping in the high voltage well; Forming a gate oxide film on an entire surface of the substrate including the trench; Performing a threshold voltage ion implantation process on the resultant product; Filling the trench by forming a polysilicon film on the gate oxide film; Planarizing the resultant until the semiconductor substrate is exposed to form a gate electrode in the trench; And forming a source / drain region by selective high concentration impurity doping in the substrate on both sides of the gate electrode.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 동작 저항(On Resistance)을 감소시킬 수 있고, 공정 수를 단축시킬 수 있는 고전압 트랜지스터(High Voltage Transistor) 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a high voltage transistor capable of reducing on resistance and shortening the number of processes.
일반적인 고전압 트랜지스터(High Voltage Transistor)는 애벌런치 접합 브레이크다운 전압(Avalanch Breakdown Voltage)을 향상시키기 위하여 고농도의 불순물로 도핑(Dopping)된 소오스/드레인(Source/Drain) 영역과 저농도의 불순물로 도핑된 드리프트(Drift) 영역을 형성하여 DDD(Double Diffused Drain) 접합 구조를 사용하고 있다. Typical high voltage transistors are source / drain regions doped with high concentrations of impurities and drift doped with low concentrations of impurities to improve the avalanche junction breakdown voltage. A (Drift) region is formed to use a double diffused drain (DDD) junction structure.
이러한 DDD(Double Diffused Drain) 접합 구조를 이용한 종래의 고전압 트랜지스터 제조방법에 대하여 도 1을 참조하여 간략하게 설명하면 다음과 같다. A conventional method of manufacturing a high voltage transistor using a double diffused drain (DDD) junction structure will be briefly described with reference to FIG. 1.
도 1은 종래의 기술에 따른 고전압 트랜지스터 제조방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a high voltage transistor according to the related art.
종래의 고전압 트랜지스터 제조방법은, 도 1에 도시된 바와 같이, 먼저 반도체 기판(11)에 고전압 웰(High Voltage Well)(12)을 형성한다. 그런다음, 상기 고전압 웰(12) 내에 선택적인 저농도 불순물 도핑으로 드리프트(Drift) 영역(13)을 형성한다. 여기서, 상기 드리프트 영역(13) 사이의 반도체 기판(11)은 채널(Channel) 영역으로 작용한다. In the conventional high voltage transistor manufacturing method, as shown in FIG. 1, first, a high voltage well 12 is formed on the semiconductor substrate 11. A drift region 13 is then formed in the high voltage well 12 with selective low concentration impurity doping. Here, the semiconductor substrate 11 between the drift region 13 serves as a channel region.
계속해서, 상기 고전압 웰(12) 및 드리프트 영역(13)이 형성된 기판(11) 전면에 게이트 산화막(미도시) 및 폴리실리콘막(미도시)을 차례로 형성한 후, 상기 폴리실리콘막 및 게이트 산화막을 선택적으로 식각하고, 이를 통해, 폴리실리콘막 재질의 고전압(High Voltage) 게이트 전극(15)을 형성한다. 이때, 도 1에서 미설명된 도면부호 14는 식각후 잔류된 게이트 산화막을 나타낸 것이다. 다음으로, 상기 결과물 상에 스페이서용 절연막(미도시)을 형성한 후, 이를 식각하여 상기 게이트 전극(15)의 양측벽에 접하는 스페이서(Spacer)(16)를 형성한다. 그런 후에, 상기 스페이서(16) 양측 기판(11)에 고농도 불순물 도핑으로 소오스/드레인(Source/Drain) 영역(17)을 형성한다. Subsequently, a gate oxide film (not shown) and a polysilicon film (not shown) are sequentially formed on the entire surface of the substrate 11 on which the high voltage well 12 and the drift region 13 are formed, and then the polysilicon film and the gate oxide film are formed. Is selectively etched, thereby forming a high voltage gate electrode 15 of polysilicon film. In this case, reference numeral 14, which is not described in FIG. 1, indicates the gate oxide layer remaining after etching. Next, after forming an insulating film (not shown) for the spacer on the resultant, it is etched to form a spacer (16) in contact with both side walls of the gate electrode (15). Thereafter, source / drain regions 17 are formed on the substrate 11 on both sides of the spacer 16 by high concentration impurity doping.
그러나, 종래의 고전압 트랜지스터에서는 전술한 바와 같이, 브레이트다운 전압(Breakdown Voltage)을 확보하기 위하여 드리프트 영역을 형성하였지만, 이 드리프트 영역으로 인해 동작 저항(On Resistance)이 커지는 문제점이 발생된다. 또한, 고전압(High Voltage) 게이트 전극 형성을 위한 별도의 식각 공정으로 인해 공정 수가 증가하는 문제점이 발생된다. However, in the conventional high voltage transistor, as described above, although the drift region is formed to secure the breakdown voltage, the drift region causes a problem in that the on-resistance is increased. In addition, a separate etching process for forming a high voltage gate electrode causes a problem in that the number of processes increases.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 드리프트 영역의 형성으로 인한 동작 저항(On Resistance)의 증가를 방지하고, 고전압(High Voltage) 게이트 전극 형성을 위한 별도의 식각 공정에 따른 공정 수의 증가를 막을 수 있는 고전압 트랜지스터 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, to prevent the increase of the operating resistance (On Resistance) due to the formation of the drift region, and to a separate etching process for forming a high voltage gate electrode It is an object of the present invention to provide a method for manufacturing a high voltage transistor that can prevent an increase in the number of processes.
상기와 같은 목적을 달성하기 위한 본 발명의 고전압 트랜지스터 제조방법은, 반도체 기판의 소정부분을 선택적으로 식각하여 트렌치를 형성하는 단계; 상기 반도체 기판에 고전압 웰을 형성하는 단계; 상기 고전압 웰 내에 선택적인 저농도 불순물 도핑으로 드리프트 영역을 형성하는 단계; 상기 트렌치를 포함한 기판 전면에 게이트 산화막을 형성하는 단계; 상기 결과물에 문턱전압 이온주입 공정을 실시하는 단계; 상기 게이트 산화막 상에 폴리실리콘막을 형성하여 상기 트렌치를 매립시키는 단계; 상기 반도체 기판이 노출될 때까지 상기 결과물을 평탄화시켜 상기 트렌치 내에 게이트 전극을 형성하는 단계; 및 상기 게이트 전극 양측의 기판에 선택적인 고농도 불순물 도핑으로 소오스/드레인 영역을 형성하는 단계를 포함한다.A high voltage transistor manufacturing method of the present invention for achieving the above object comprises the steps of selectively etching a predetermined portion of the semiconductor substrate to form a trench; Forming a high voltage well on the semiconductor substrate; Forming a drift region with selective low concentration impurity doping in the high voltage well; Forming a gate oxide film on an entire surface of the substrate including the trench; Performing a threshold voltage ion implantation process on the resultant product; Filling the trench by forming a polysilicon film on the gate oxide film; Planarizing the resultant until the semiconductor substrate is exposed to form a gate electrode in the trench; And forming a source / drain region by selective high concentration impurity doping in the substrate on both sides of the gate electrode.
여기서, 상기 평탄화는 에치백 공정을 이용하여 달성한다.Here, the planarization is achieved using an etch back process.
본 발명에 따르면, 반도체 기판의 소정부분을 식각하여 트렌치를 형성한 후, 상기 트렌치 내에 게이트 전극을 형성함으로써, 드리프트 영역 사이의 기판 부분인 채널 영역과 소오스/드레인 영역 사이의 기생 직렬(Series) 저항을 감소시켜 동작 저항(On Resistance)을 감소시킬 수 있다. 또한, 게이트 전극을 형성하기 위한 식각 공정이 생략되므로, 공정 수를 단축시킬 수 있다. According to the present invention, a parasitic series resistance between a channel region and a source / drain region, which is a substrate portion between drift regions, is formed by etching a predetermined portion of a semiconductor substrate to form a trench, and then forming a gate electrode in the trench. By reducing the On resistance can be reduced. In addition, since the etching process for forming the gate electrode is omitted, the number of processes can be shortened.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 고전압 트랜지스터 제조방법을 설명하기 위한 공정별 단면도이다. 2A through 2D are cross-sectional views illustrating processes of manufacturing a high voltage transistor according to an exemplary embodiment of the present invention.
본 발명의 실시예에 따른 고전압 트랜지스터 제조방법은, 도 2a에 도시된 바와 같이, 먼저, 반도체 기판(21)의 소정부분을 선택적으로 식각하여 트렌치(Trench)(22)를 형성한 다음, 상기 반도체 기판(21)에 고전압 웰(High Voltage Well)(23)을 형성한다.In the method of manufacturing a high voltage transistor according to an embodiment of the present invention, as shown in FIG. 2A, first, a predetermined portion of the semiconductor substrate 21 is selectively etched to form a trench 22, and then the semiconductor A high voltage well 23 is formed on the substrate 21.
그런다음, 도 2b에 도시된 바와 같이, 상기 고전압 웰(23) 내에 선택적인 저농도 불순물 도핑으로 드리프트(Drift) 영역(24)을 형성한다. 여기서, 상기 드리프트 영역(24) 사이의 반도체 기판(21)은 채널(Channel) 영역으로 작용한다. 계속해서, 상기 트렌치(22)를 포함한 기판 전면에 게이트 산화막(25)을 형성한다. 이후, 상기 결과물에 문턱전압(Vt) 이온주입 공정(26)을 실시한다. Then, as shown in FIG. 2B, a drift region 24 is formed by selective low concentration impurity doping in the high voltage well 23. Here, the semiconductor substrate 21 between the drift regions 24 serves as a channel region. Subsequently, a gate oxide film 25 is formed over the entire substrate including the trench 22. Thereafter, a threshold voltage (Vt) ion implantation process 26 is performed on the resultant.
다음으로, 도 2c에 도시된 바와 같이, 상기 게이트 산화막(25) 상에 폴리실리콘막(27)을 형성하여 상기 트렌치(22)를 매립시킨다. Next, as shown in FIG. 2C, the trench 22 is buried by forming a polysilicon film 27 on the gate oxide film 25.
이어서, 도 2d에 도시된 바와 같이, 상기 반도체 기판(21)이 노출될 때까지 상기 결과물을 평탄화시켜 상기 트렌치(22) 내에 게이트 전극(27a)을 형성한다. 여기서, 상기 평탄화는 에치백(Etch Back) 공정을 이용하여 달성한다. 한편, 도 2d에서 미설명된 도면부호 25a는 에치백후 잔류된 게이트 산화막을 나타낸 것이다. Subsequently, as shown in FIG. 2D, the resultant is planarized until the semiconductor substrate 21 is exposed to form a gate electrode 27a in the trench 22. Here, the planarization is achieved using an etch back process. Meanwhile, reference numeral 25a, which is not described in FIG. 2D, indicates the gate oxide film remaining after the etch back.
그런후에, 상기 게이트 전극(27a) 양측의 기판에 선택적인 고농도 불순물 도핑으로 소오스/드레인 영역(Source/Drain)(28)을 형성한다. Thereafter, source / drain regions 28 are formed on the substrate on both sides of the gate electrode 27a by selective high concentration impurity doping.
상기와 같은 공정을 통해 제조되는 본 발명에 따른 고전압 트랜지스터는 반도체 기판의 소정부분을 식각하여 트렌치를 형성한 후, 상기 트렌치 내에 게이트 전극을 형성함으로써, 드리프트 영역 사이의 기판 부분인 채널 영역과 소오스/드레인 영역 사이의 기생 직렬(Series) 저항을 감소시켜 동작 저항(On Resistance)을 감소시킬 수 있다. 또한, 본 발명에 따르면, 게이트 전극을 형성하기 위한 식각 공정이 생략되므로, 공정 수를 단축시킬 수 있다. The high voltage transistor according to the present invention manufactured through the above process forms a trench by etching a predetermined portion of the semiconductor substrate, and then forms a gate electrode in the trench, thereby forming a channel region and a source / source between the drift regions. On resistance can be reduced by reducing the parasitic series resistance between the drain regions. Further, according to the present invention, since the etching process for forming the gate electrode is omitted, the number of processes can be shortened.
이상에서와 같이, 본 발명은 반도체 기판의 소정부분을 식각하여 트렌치(Trench)를 형성한 후, 상기 트렌치 내에 게이트 전극을 형성함으로써, 드리프트 영역 사이의 기판 부분인 채널 영역과 소오스/드레인 영역 사이의 기생 직렬(Series) 저항을 감소시켜 동작 저항(On Resistance)을 감소시킬 수 있다. 또한, 본 발명은 게이트 전극을 형성하기 위한 식각 공정이 생략되므로, 공정 수를 단축시킬 수 있다. As described above, the present invention forms a trench by etching a predetermined portion of the semiconductor substrate, and then forms a gate electrode in the trench, thereby forming a region between the channel region and the source / drain region, which are substrate portions between the drift regions. On resistance can be reduced by reducing parasitic series resistance. Further, in the present invention, since the etching process for forming the gate electrode is omitted, the number of processes can be shortened.
도 1은 종래의 기술에 따른 고전압 트랜지스터 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a high voltage transistor manufacturing method according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 고전압 트랜지스터 제조방법을 설명하기 위한 공정별 단면도.2A through 2D are cross-sectional views of processes for describing a method of manufacturing a high voltage transistor according to an exemplary embodiment of the present invention.
-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing
21 : 반도체 기판 22 : 트렌치21 semiconductor substrate 22 trench
23 : 고전압 웰 24 : 드리프트 영역23 high voltage well 24 drift region
25 : 게이트 산화막 25a : 에치백후 잔류된 게이트 산화막25 gate oxide film 25a remaining gate oxide film after etch back
26 : 문턱전압 이온주입 공정 27 : 폴리실리콘막26 threshold voltage ion implantation process 27 polysilicon film
27a : 게이트 전극 28 : 소오스/드레인 영역27a: gate electrode 28: source / drain region
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