KR20080088095A - Method for forming gate of semiconductor device - Google Patents

Method for forming gate of semiconductor device Download PDF

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Publication number
KR20080088095A
KR20080088095A KR1020070030515A KR20070030515A KR20080088095A KR 20080088095 A KR20080088095 A KR 20080088095A KR 1020070030515 A KR1020070030515 A KR 1020070030515A KR 20070030515 A KR20070030515 A KR 20070030515A KR 20080088095 A KR20080088095 A KR 20080088095A
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South Korea
Prior art keywords
gate
polysilicon film
film
type polysilicon
forming
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KR1020070030515A
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Korean (ko)
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오태경
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주식회사 하이닉스반도체
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Priority to KR1020070030515A priority Critical patent/KR20080088095A/en
Publication of KR20080088095A publication Critical patent/KR20080088095A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066Gate region of field-effect devices with PN junction gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

A method of forming a gate of a semiconductor device includes: recessing a semiconductor substrate to form a gate groove; Forming a gate insulating film on an entire surface of the substrate including the gate groove; Forming a P-type polysilicon film on the gate insulating film; Etching the P-type polysilicon film and the gate insulating film so that the P-type polysilicon film and the gate insulating film remain only under the gate groove; Forming an oxide film on a sidewall of an upper portion of the gate groove in which the P-type polysilicon film and the gate insulating film remain; Forming an N-type polysilicon film on the entire surface of the substrate including the oxide film and the P-type polysilicon film; And sequentially forming a metal-based film and a hard mask film on the N-type polysilicon film.

Description

METHOOD FOR FORMING GATE OF SEMICONDUCTOR DEVICE
1A to 1H are cross-sectional views illustrating processes for forming a gate of a semiconductor device in accordance with an embodiment of the present invention.
Explanation of symbols on the main parts of the drawings
100 semiconductor substrate 102 device isolation film
H: Gate groove 104: Gate insulating film
106: p-type polysilicon film 108: oxide film
110: N-type polysilicon film 112: metal film
114: hard mask film 116: gate
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, and to forming a gate cell of a semiconductor device, which may improve device characteristics and reliability by improving a gate induced drain leakage (GIDL) phenomenon in manufacturing a DRAM cell transistor. It is about a method.
In recent years, as the design rules of highly integrated MOSFETs are rapidly reduced to 100 nm or less, the channel length and width of transistors are correspondingly reduced, and the doping concentration to the junction region is increased. Therefore, the junction leakage current increases with the increase of the electric field. As a result, it is difficult to obtain a threshold voltage value required by a high density device using a conventional planar channel structure transistor, and reaches a limit in improving refresh characteristics.
Accordingly, a method of implementing a semiconductor device having various types of recess channels capable of securing an effective channel length of the transistor, and a channel having a three-dimensional structure capable of extending a channel width. Research on the idea of how to implement the semiconductor device and the actual process development is being actively conducted.
When the semiconductor device having the recess channel is manufactured, the effective length of the channel is increased as compared with the conventional planar type device, so that short channel effect is suppressed, and even a small ion implantation dose is desired. Since the threshold voltage can be ensured, the junction leakage current is reduced to improve the refresh characteristics. In addition, cell characteristics are improved by improving drain-induced barrier lowering (DIBL) and breakdown voltage (BVds).
In addition, a fin transistor structure has been proposed as a transistor having a channel having a three-dimensional structure, and the protrusion transistor has an active region formed by etching a device isolation region to protrude an active region to form a fin pattern. A gate line is formed to expose both sides and the top surface of the substrate, and then surround the protruding active region (pin pattern). In this case, a short channel effect due to an increase in drain induced barrier low (DIBL) Effect) is suppressed, and the channel is formed on all three exposed surfaces of the active region, which greatly improves the current drive characteristics of the channel.
On the other hand, as the integration of the MOSFET device progresses, the gate line width is reduced due to the decrease in the cell size, and the decrease in the line width of the gate electrode causes the channel length to decrease.
As such, the decrease in the channel length due to the high integration of the MOSFET increases the doping concentration of the semiconductor substrate. As a result, the leakage current (LC) of the device increases and the threshold voltage (Vt). The so-called short channel effect phenomenon, which is drastically lowered, is further intensified.
Therefore, in the NMOS device, a P-type polysilicon film having a large work function of a gate is applied to adjust a threshold voltage Vt through channel doping of a boron system.
When the P-type polysilicon film is used instead of the N-type polysilicon film in the NMOS device, the work function of the gate end is increased, thereby bringing about a change in the surface potential in the channel, thereby lowering the channel Threshold voltage (Vt) can be secured even with a dose.
However, in the above-described prior art, the potential difference is increased by the work function in the overlap region between the N-type junction region and the gate to which the P-type polysilicon film is applied, and as a result, a GIDL phenomenon is obtained. This deepening degrades the refresh characteristics of the device.
In this case, the GIDL phenomenon is a phenomenon in which current leaks due to concentration of an electric field at both corners of the gate and the substrate in contact with each other, and is a major factor in reducing the refresh time of the device. It is a challenge that must be solved.
The present invention provides a method of forming a gate of a semiconductor device that can improve device characteristics and reliability by improving a gate induced drain leakage (GIDL) phenomenon in manufacturing a DRAM cell transistor.
A method of forming a gate of a semiconductor device according to the present invention comprises the steps of: recessing a semiconductor substrate to form a groove for the gate; Forming a gate insulating film on an entire surface of the substrate including the gate groove; Forming a P-type polysilicon film on the gate insulating film; Etching the P-type polysilicon film and the gate insulating film so that the P-type polysilicon film and the gate insulating film remain only under the gate groove; Forming an oxide film on a sidewall of an upper portion of the gate groove in which the P-type polysilicon film and the gate insulating film remain; Forming an N-type polysilicon film on the entire surface of the substrate including the oxide film and the P-type polysilicon film; And sequentially forming a metal-based film and a hard mask film on the N-type polysilicon film.
Here, the etching of the P-type polysilicon film and the gate insulating film is performed such that the P-type polysilicon film remains at a thickness of 700 to 900 만큼 under the gate groove.
The P-type polysilicon film is formed of a polysilicon film doped with a P-type impurity dose of 5 × 10 18 to 5 × 10 22 ions / cm 2 .
The N-type polysilicon film is formed to a thickness of 300 to 500 kPa.
The N-type polysilicon film is formed of a polysilicon film doped with a dose of 5 × 10 18 to 5 × 10 22 ions / cm 2 of N-type impurities.
In addition, the method for forming a gate of a semiconductor device according to the present invention comprises the steps of forming an isolation film defining an active region of the semiconductor substrate; Etching the device isolation layer to expose some side surfaces of the active region to form a fin pattern having a protruding shape of the active region; Recessing the protruding active region to form a groove for a gate; Forming a gate insulating film on an entire surface of the substrate including the gate groove; Forming a P-type polysilicon film on the gate insulating film; Etching the P-type polysilicon film and the gate insulating film so that the P-type polysilicon film and the gate insulating film remain only under the gate groove; Forming an oxide film on a sidewall of an upper portion of the gate groove in which the P-type polysilicon film and the gate insulating film remain; Forming an N-type polysilicon film on the entire surface of the substrate including the oxide film and the P-type polysilicon film; And sequentially forming a metal-based film and a hard mask film on the N-type polysilicon film.
The etching of the P-type polysilicon film and the gate insulating film may be performed such that the P-type polysilicon film remains in the lower portion of the gate groove by a thickness of 700 to 900 Å.
The P-type polysilicon film is formed of a polysilicon film doped with a P-type impurity dose of 5 × 10 18 to 5 × 10 22 ions / cm 2 .
The N-type polysilicon film is formed to a thickness of 300 to 500 kPa.
The N-type polysilicon film is formed of a polysilicon film doped with a dose of 5 × 10 18 to 5 × 10 22 ions / cm 2 of N-type impurities.
(Example)
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
According to the present invention, a high concentration P-type polysilicon film is formed in a lower portion of a gate groove in which a channel of a recess gate is formed when forming a gate of a semiconductor device in which a polysilicon film is applied as a gate conductive film, and the sidewall of the gate groove is formed. A high concentration N-type polysilicon film is formed on the top.
In this case, a P-type polysilicon film having a large work function is formed in a portion where the channel is formed, thereby securing a threshold voltage Vt even with a low channel dose, thereby increasing driving current of a semiconductor device. In addition, by forming an N-type polysilicon layer on the sidewall of the gate groove, a gate current drain (LCID) phenomenon may be improved to reduce leakage current (LC).
1A to 1H are cross-sectional views illustrating processes of forming a gate of a semiconductor device according to an exemplary embodiment of the present invention.
Referring to FIG. 1A, a trench is formed by etching the device isolation region of the semiconductor substrate 100 having the active region including the gate formation region and the device isolation region, and then depositing an insulating layer to fill the trench. An isolation layer 102 defining a region is formed.
Subsequently, a mask pattern (not shown) is formed on the resultant of the substrate 100 on which the device isolation layer 102 is formed to expose the gate forming region of the active region, and then the substrate exposed by the mask pattern ( After etching the portion 100 to form the gate groove H, the mask pattern is removed.
Referring to FIG. 1B, a gate insulating film 104 is formed along the profile of the gate groove H on the entire surface of the substrate 100 including the gate groove H. Referring to FIG.
Referring to FIG. 1C, a P-type polysilicon film 106 is preferably deposited to a thickness of about 1000 GPa so as to fill the gate groove H on the gate insulating film 104. The P-type polysilicon film 106 is formed of a polysilicon film doped with P-type impurities of about 5 × 10 18 to 5 × 10 22 ions / cm 2 .
Referring to FIG. 1D, the P-type polysilicon film 106 and the gate insulating film 104 are formed to have a thickness of about 700 to 900 kV in the lower portion of the gate groove H, preferably about 800 kPa. The P-type polysilicon film 106 and the gate insulating film 104 are etched so as to remain as much as possible.
Referring to FIG. 1E, an oxide film 108 is formed on the entire surface of the substrate 100 including the upper portion of the gate groove H, and then the oxide film 108 is etched to form the P-type polysilicon film 106. And the oxide film 108 remains only in the sidewall portion of the upper portion of the gate groove H in which the gate insulating film 104 does not remain.
Referring to FIG. 1F, the gate is formed on a resultant of the substrate 100 including the oxide film 108, the P-type polysilicon film 106, and the gate insulating film 104 remaining in the sidewall portion of the gate groove H. The N-type polysilicon film 110 is formed to a thickness of about 300 to 500 kPa, preferably about 400 kPa to fill the groove H.
The N-type polysilicon film 110 is formed of a polysilicon film doped with an N-type impurity dose of about 5 × 10 18 to 5 × 10 22 ions / cm 2 . Subsequently, it is preferable to planarize the surface of the N-type polysilicon film 110 through a chemical mechanical polishing (CMP) or an etch back process.
Referring to FIG. 1G, a metal layer 112 and a hard mask layer 114 are sequentially formed on the planarized N-type polysilicon layer 110. The metal layer 112 is formed of a WSi x film, and the hard mask layer 114 is formed of a SiN film.
Referring to FIG. 1H, a gate is formed on the gate groove H by etching the hard mask layer 114, the metal layer 112, and the N-type polysilicon layer 110.
Thereafter, although not shown, a series of subsequent known processes are sequentially performed to complete the gate of the semiconductor device according to the embodiment of the present invention.
Here, the present invention forms a high-concentration P-type polysilicon film having a large work function in the lower portion of the gate groove in which the channel of the gate is formed, thereby changing a low channel dose through a surface potential change in the channel. Also, the threshold voltage Vt may be secured to increase the driving current of the semiconductor device.
In addition, the present invention forms a high-concentration N-type polysilicon film in the upper portion of the gate groove in which the electric field is concentrated, thereby improving the GIDL phenomenon and causing the electric field to be concentrated at both edge portions of the gate and the substrate. The leakage current can be reduced, thereby improving the refresh characteristics of the semiconductor device.
Accordingly, the present invention forms a high concentration P-type polysilicon film under the gate groove and a high concentration N-type polysilicon film on the gate groove, thereby increasing the driving current of the semiconductor device and reducing the GIDL phenomenon. Since it can improve, a semiconductor element characteristic and reliability can be improved effectively.
Meanwhile, in the above-described embodiment of the present invention, a method of improving the GIDL phenomenon when the recess gate is formed to increase the effective channel length of the gate has been described, but as another embodiment of the present invention, the channel width of the gate is increased. The same effect can be obtained when the device isolation layer is etched to increase the ridge-type gate exposed by some side surfaces of the active region to increase.
As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
As described above, the present invention can increase the driving current of the semiconductor device by forming a high concentration P-type polysilicon film under the gate groove in which the channel of the gate is formed.
In addition, the present invention by forming a high concentration of the N-type polysilicon film in the upper portion of the gate groove in which the electric field is concentrated, it is possible to reduce the leakage current by improving the GIDL (Gate Induced Drain Leakage) phenomenon, In addition, the refresh characteristics of the semiconductor device can be improved.
Accordingly, the present invention forms a high concentration P-type polysilicon film under the gate groove and a high concentration N-type polysilicon film on the gate groove, thereby increasing the driving current of the semiconductor device and reducing the GIDL phenomenon. Since it can improve, a semiconductor element characteristic and reliability can be improved effectively.

Claims (10)

  1. Recessing the semiconductor substrate to form a groove for the gate;
    Forming a gate insulating film on an entire surface of the substrate including the gate groove;
    Forming a P-type polysilicon film on the gate insulating film;
    Etching the P-type polysilicon film and the gate insulating film so that the P-type polysilicon film and the gate insulating film remain only under the gate groove;
    Forming an oxide film on a sidewall of an upper portion of the gate groove in which the P-type polysilicon film and the gate insulating film remain;
    Forming an N-type polysilicon film on the entire surface of the substrate including the oxide film and the P-type polysilicon film; And
    Sequentially forming a metal-based film and a hard mask film on the N-type polysilicon film; And
    Gate forming method of a semiconductor device comprising a.
  2. The method of claim 1,
    Etching the P-type polysilicon film and the gate insulating film,
    And forming the P-type polysilicon film so as to remain in the lower portion of the gate groove by a thickness of 700 to 900 ∼.
  3. The method of claim 1,
    The P-type polysilicon film is a gate forming method of a semiconductor device, characterized in that the P-type impurities are formed of a polysilicon film doped with a dose of 5 × 10 18 ~ 5 × 10 22 ions / cm 2 .
  4. The method of claim 1,
    And the N-type polysilicon film is formed to a thickness of 300 to 500 GPa.
  5. The method of claim 1,
    The N-type polysilicon film is a gate forming method of a semiconductor device, characterized in that the N-type impurity is formed of a polysilicon film doped with a dose of 5 × 10 18 ~ 5 × 10 22 ions / cm 2 .
  6. Forming an isolation layer defining an active region of the semiconductor substrate;
    Etching the device isolation layer to expose some side surfaces of the active region to form a fin pattern having a protruding shape of the active region;
    Recessing the protruding active region to form a groove for a gate;
    Forming a gate insulating film on an entire surface of the substrate including the gate groove;
    Forming a P-type polysilicon film on the gate insulating film;
    Etching the P-type polysilicon film and the gate insulating film so that the P-type polysilicon film and the gate insulating film remain only under the gate groove;
    Forming an oxide film on a sidewall of an upper portion of the gate groove in which the P-type polysilicon film and the gate insulating film remain;
    Forming an N-type polysilicon film on the entire surface of the substrate including the oxide film and the P-type polysilicon film; And
    Sequentially forming a metal-based film and a hard mask film on the N-type polysilicon film;
    Gate forming method of a semiconductor device comprising a.
  7. The method of claim 6,
    Etching the P-type polysilicon film and the gate insulating film,
    And forming the P-type polysilicon film so as to remain in the lower portion of the gate groove by a thickness of 700 to 900 ∼.
  8. The method of claim 6,
    The P-type polysilicon film is a gate forming method of a semiconductor device, characterized in that the P-type impurities are formed of a polysilicon film doped with a dose of 5 × 10 18 ~ 5 × 10 22 ions / cm 2 .
  9. The method of claim 6,
    And the N-type polysilicon film is formed to a thickness of 300 to 500 GPa.
  10. The method of claim 6,
    The N-type polysilicon film is a gate forming method of a semiconductor device, characterized in that the N-type impurity is formed of a polysilicon film doped with a dose of 5 × 10 18 ~ 5 × 10 22 ions / cm 2 .
KR1020070030515A 2007-03-28 2007-03-28 Method for forming gate of semiconductor device KR20080088095A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101105433B1 (en) * 2009-07-03 2012-01-17 주식회사 하이닉스반도체 Semiconductor device with buried gate and method for manufacturing the same
CN105322021A (en) * 2014-08-04 2016-02-10 瑞萨电子株式会社 Semiconductor device and method for manufacturing same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101105433B1 (en) * 2009-07-03 2012-01-17 주식회사 하이닉스반도체 Semiconductor device with buried gate and method for manufacturing the same
US8120099B2 (en) 2009-07-03 2012-02-21 Hynix Semiconductor Inc. Semiconductor device with buried gate and method for fabricating the same
CN105322021A (en) * 2014-08-04 2016-02-10 瑞萨电子株式会社 Semiconductor device and method for manufacturing same
CN105322021B (en) * 2014-08-04 2020-11-24 瑞萨电子株式会社 Semiconductor device and method for manufacturing the same

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