JP2013251497A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can effectively inhibit unnecessary raise of on-resistance and field concentration on a gate end.SOLUTION: A semiconductor device comprises one and more types of high-voltage transistors each having a MOS transistor structure including a gate part formed by stacking on a semiconductor substrate 1, element isolation regions 2 formed by an STI method, an active region partitioned by the element isolation regions 2, a source region 16 and a drain region 17 which are formed in the active region at a distance from each other; and a gate insulation film 10 and a gate electrode 11 on a surface of the semiconductor substrate 1 between the source region 16 and the drain region 17. The high-voltage transistor includes below the semiconductor substrate surface at an end of the gate part, a gate end insulation part 3 formed by filling an insulator in a groove formed on the semiconductor substrate. A depth of the gate end insulation part 3 from the semiconductor substrate surface is made larger than a film thickness of the gate insulation film 10 of the high-voltage transistor and smaller than a depth of the element isolation region 2 from the semiconductor substrate surface.

Description

  The present invention relates to a semiconductor device, and more particularly to a high voltage MOS transistor.

  In a logic circuit transistor, miniaturization of the transistor is indispensable in order to improve the operation speed and reduce the cost, and the power supply voltage tends to decrease in order to reduce power consumption. On the other hand, a power input / output interface circuit, a data write / erase circuit in a flash memory, a liquid crystal panel drive circuit, etc. handle a higher input / output voltage than a general logic circuit, and therefore requires a transistor with a high breakdown voltage. And

  For a general high voltage transistor, it is necessary to make the gate oxide film thick and to secure a distance between the gate and the high concentration diffusion region in order to ensure a withstand voltage, and the dimensions of the transistor and the element isolation region are low voltage transistors. Tend to be bigger. For this reason, a trench offset type medium / high voltage MOS transistor that can reduce the size of the element by adopting STI (Shallow Trench Isolation) used in the element isolation region in the drift portion and securing a distance in the depth direction is provided. Proposed.

  Further, in a well-known LDMOS (Lateral Diffused MOS) transistor as a high breakdown voltage / low on-resistance element, the concentration of the channel portion is made higher than that of the drain side drift portion by using the gate oxide film of the low voltage transistor. Therefore, by suppressing the extension of the depletion layer to the channel side, the channel length is reduced, and high breakdown voltage and low on-resistance are realized. However, in a high breakdown voltage transistor using a thin gate oxide film, the factors that determine the breakdown voltage are firstly the breakdown voltage between the well of the channel part and the drain side drift part, and secondly, between the drain side drift part and the substrate. Third, there are three types of breakdown voltage, the breakdown voltage due to the electric field concentration at the drain side drift portion and the drain side gate end portion, and the electric field concentration at the gate end portion becomes dominant as the gate oxide film becomes thinner. End up. In order to improve this, a method of forming a thick oxide film by LOCOS (Local Oxidation of Silicon) method at the gate end on the drain side to alleviate electric field concentration at the gate end (for example, Patent Document 1 below) And a method of relaxing by STI instead of LOCOS has been proposed (see, for example, Patent Document 2 below).

  FIGS. 17 and 18 schematically show examples of cross-sectional structures of a general STI offset type n-type high breakdown voltage MOS transistor and an STI offset type n-type LDMOS transistor, respectively. In the STI offset type element structure, since the electric field concentration between the drain and the gate is relaxed by the thick oxide film at the gate end portion, the breakdown voltage can be improved. However, the current path in the drift portion is below the STI. There is a problem that it becomes longer by detouring to the side and accompanied by an increase in on-resistance.

  Further, in the general STI offset type medium / high breakdown voltage transistors shown in FIGS. 17 and 18, the drain side of the depletion layer that causes GIDL (Gate Induced Drain Leakage) by arranging the STI at the gate end. However, since the STI of the element isolation region is used as the STI disposed at the gate end, the STI is deepened and the on-resistance is increased.

JP-A-8-236757 JP 2011-187853 A

  As a method for suppressing the increase in the on-resistance, in Patent Document 2, an impurity implantation is added to the bottom of the STI after the trench etch during the STI formation in order to improve the trade-off relationship between the breakdown voltage and the on-resistance of the LDMOS transistor. Attempts have been made to increase the impurity concentration in the lower portion of the STI, reduce the drift resistance, and lower the on-resistance. However, in this method, the number of steps increases due to the additional impurity implantation step, which causes an increase in manufacturing cost.

  On the other hand, by making the depth of the STI disposed at the gate end portion shallower than the STI of the element isolation region, the detour distance of the STI of the current path in the drift portion can be shortened, and the increase in on-resistance can be suppressed. In order to reduce the depth of the STI disposed at the gate end, the STI trench disposed at the gate end and the STI trench of the element isolation region must be formed in separate processes. This increases the number of processes and increases manufacturing costs.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of effectively suppressing an unnecessary increase in on-resistance and electric field concentration at the gate end. .

  To achieve the above object, the present invention provides an element isolation region formed on a semiconductor substrate by an STI (Shallow Trench Isolation) method, an active region partitioned by the element isolation region, and spaced apart from each other in the active region. One type of MOS transistor structure comprising a formed source region and drain region, and a gate portion formed by laminating a gate insulating film and a gate electrode on the surface of the semiconductor substrate between the source region and the drain region. A gate end insulating portion comprising the above high breakdown voltage transistor, wherein an insulator is filled in a groove formed in the semiconductor substrate below the surface of the semiconductor substrate at the end of the gate portion of the high breakdown voltage transistor. The gate end insulating portion is narrower than the minimum width of the element isolation region, and the semiconductor of the gate end insulating portion There is provided a semiconductor device characterized in that a depth from a substrate surface is larger than a film thickness of the gate insulating film of the high breakdown voltage transistor and smaller than a depth from the semiconductor substrate surface of the element isolation region.

  Here, in the semiconductor device having the above characteristics, it is preferable that one of the high breakdown voltage transistors includes the gate end insulating portion only at the end of the gate portion on the drain region side.

  Furthermore, in the semiconductor device having the above characteristics, one of the high breakdown voltage transistors has the gate end insulating portion at each end of the gate portion on the drain region side and the source region side. Is preferred.

  Furthermore, in the semiconductor device having the above characteristics, one type of the high breakdown voltage transistors has the gate end insulating portion at each end of the gate portion on the drain region side and the source region side. The depth of the gate end insulating portion at the end on the drain region side from the surface of the semiconductor substrate is different from the depth of the gate end insulating portion at the end on the source region side from the surface of the semiconductor substrate. preferable.

  Furthermore, the semiconductor device having the above characteristics has at least one kind of low breakdown voltage transistor having the MOS type transistor structure having a lower breakdown voltage than the high breakdown voltage transistor, and the surface of the semiconductor substrate at the end of the gate portion of the low breakdown voltage transistor. It is preferable that the gate end insulating portion is not formed further below.

  Furthermore, in the semiconductor device having the above characteristics, it is preferable that the gate insulating film of the high breakdown voltage transistor and the gate insulating film of the low breakdown voltage transistor have the same film thickness.

  Furthermore, the semiconductor device having the above characteristics preferably includes two or more types of the high breakdown voltage transistors having different depths from the surface of the semiconductor substrate of the gate end insulating portion.

  Furthermore, in the semiconductor device having the above characteristics, it is preferable that one of the two or more types of the high breakdown voltage transistors is used as an ESD protection element.

  Furthermore, in order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device having the above characteristics, wherein the groove of the element isolation region and the groove of the gate end insulating portion are formed in the semiconductor substrate at 45 ° to 85 °. Provided is a method for manufacturing a semiconductor device, wherein the semiconductor devices are simultaneously formed by etching with an etching angle adjusted between.

  According to the semiconductor device having the above characteristics and the method of manufacturing the same, the high breakdown voltage transistor has a gate insulating film thickness below the surface of the semiconductor substrate on the drain region side, the source region side, or both ends of the gate portion. By providing the gate end insulating portion having a greater depth, a separation distance between the gate portion and the drain region or the source region can be secured, so that electric field concentration at the end portion can be effectively reduced. Furthermore, since the depth of the gate end insulating portion can be made smaller than the depth of the element isolation region from the surface of the semiconductor substrate, it is possible to suppress the on-resistance of the high voltage transistor from increasing unnecessarily.

  In particular, each of the element isolation region and the gate end insulating portion has a structure in which an insulator is filled in a groove formed in a semiconductor substrate, and each groove can be formed simultaneously in the same process. In addition, since the width of the groove in the gate end insulating portion is narrower than the minimum width of the groove in the element isolation region, the depth of the groove in the gate end insulating portion can be processed shallower than the depth of the groove in the element isolation region. More specifically, the element isolation regions having different groove widths and the grooves in the gate end insulating portion can be formed at different depths in the same etching step by adjusting the etching angle. That is, when both the element isolation region and the gate end insulating portion are formed by STI, STIs having different groove depths can be formed in the same process, so that conventional STI offset type high breakdown voltage MOS transistors and LDMOS transistors can be formed. As described above, since the gate end insulating portion does not need to be unnecessarily deeply formed without causing an increase in manufacturing cost due to the formation of the STI of the gate end insulating portion in a separate process, The depth can be freely adjusted according to the withstand voltage, and an increase in on-resistance can be suppressed.

  In addition, in the LDMOS transistor, by providing an overlap region between the gate electrode and the drift region, the drift carrier concentration under the gate end insulating portion (STI) of the drift portion can be increased by the voltage of the gate electrode. Can be reduced.

  Further, even in a semiconductor device in which two or more types of high breakdown voltage transistors having a gate end insulating portion at the end of the gate portion are mounted, each gate end is formed in the same process according to the breakdown voltage of each high breakdown voltage transistor. Since the depth of the insulating portion can be adjusted, a semiconductor device in which two or more types of high voltage transistors are mixedly mounted can be provided without increasing the number of processes.

Process sectional drawing which shows typically the manufacturing process (process 1) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 2) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 3) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 4) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 5) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 6) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 7) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 8 and 9) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 10) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. Process sectional drawing which shows typically the manufacturing process (process 11) of the high voltage | pressure-resistant and low voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention. The figure which shows the relationship between the gate edge insulating part width Wge and the trench depth D1 when the etching angles are 45 °, 60 °, 70 ° and 80 °. The figure which shows typically the relationship between the trench depth D1 of a gate end insulating part, element breakdown voltage Vtor, and ON resistance Ron of a LDMOS transistor. The figure which shows typically the relationship between the overlap length of the gate electrode of a LDMOS transistor, and a drift region, and the ON resistance of a LDMOS transistor Sectional drawing which shows typically the other element structure of the high voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention Sectional drawing which shows typically the other element structure of the high voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention Sectional drawing which shows typically the other element structure of the high voltage | pressure-resistant MOS transistor contained in the semiconductor device of this invention Sectional drawing which shows typically an example of the element structure of the conventional STI offset type high voltage MOS transistor Sectional drawing which shows typically the element structure of the conventional STI offset type high voltage | pressure-resistant LDMOS transistor

  Hereinafter, embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings. First, a method of manufacturing a high voltage MOS transistor and a low voltage MOS transistor included in the semiconductor device of the present invention will be described with reference to FIGS.

  1 to 10, it is assumed that the high breakdown voltage MOS transistor and the low breakdown voltage MOS transistor are both n-channel MOS transistors, and an LDMOS transistor is shown as an example of the high breakdown voltage MOS transistor. 1 to 10 are process cross-sectional views showing a manufacturing process of a high voltage MOS transistor (LDMOS transistor) on the right side and process cross-sectional views showing a manufacturing process of a low voltage MOS transistor on the left side. In FIGS. 1 to 10, the main parts are emphasized for easy understanding of the explanation, and therefore the dimensional ratios of the respective parts shown in the drawings do not necessarily match the dimensional ratios of the actual elements. do not do.

  As shown in FIG. 1, an element isolation region 2 is formed in a low breakdown voltage MOS transistor region and an element isolation region 2 and a gate are formed in a low breakdown voltage MOS transistor region on a silicon substrate 1 which is a p-type semiconductor substrate by using STI technology. The end insulating portions 3 are formed simultaneously (step 1). In step 1, trench etching for locally digging the silicon substrate 1 to form a trench is performed using anisotropic dry etching such as well-known RIE (Reactive Ion Etching). At the time of the trench etching, the width Wge of the gate end insulating portion 3 is adjusted to be smaller than the minimum width of the element isolation region 2, and further, the etching angle is adjusted to be within a range of 45 to 80 °. The trench depth D1 of the insulating portion 3 is formed shallower than the trench depth D2 of the element isolation region 2. The etching angle is defined as an angle from the surface of the silicon substrate 1. A predetermined insulating film (for example, silicon oxide film) is buried in each trench of the element isolation region 2 and the gate end insulating portion 3 by a CVD (Chemical Vapor Deposition) method or the like, and is flattened by a CMP (Chemical-Mechanical Polishing) method or the like. The element isolation region 2 and the gate end insulating portion 3 are formed by performing the process. In this embodiment, as an example, the trench depth D2 of the element isolation region 2 is set to 0.3 to 1.0 μm, and the trench depth D1 of the gate end insulating portion 3 is set to 0.05 to 0.5 μm.

FIG. 11 shows the relationship between the width Wge of the gate end insulating portion 3 and the trench depth D1 when the trench depth D2 of the element isolation region 2 is 1.0 μm. The etching angles are 45 °, 60 °, and 70 °. The case of 80 ° will be described. However, for the trench etch, a dry etching method was used, and the etching angle was adjusted by changing the RF power to 1000 W and the flow ratio of HBr to Cl ₂ gas between 1: 1 to 5: 1. Further, the relationship between the width Wge and the trench depth D1 when the etching angle is 85 ° is also shown in FIG. 11 as a comparative example. 11 that the trench depth D1 of the gate end insulating portion 3 can be made shallower than the trench depth D2 of the element isolation region 2 by individually adjusting the width Wge of the gate end insulating portion 3 and the etching angle. .

  Further, the trench etching may be performed using wet etching using chemicals having different etching rates with respect to the crystal orientation of the silicon substrate 1. For example, when a known KOH solution is used, it can be processed at an etching angle of about 55 ° with respect to a (100) Si wafer.

Subsequently, as shown in FIG. 2, after a sacrificial oxide film 4 is formed on the entire surface of the silicon substrate 1 to a thickness of 10 to 30 nm, a resist mask 5 having an opening in a partial region on the high voltage MOS transistor side is used to form n. A type impurity, for example, P (phosphorus) ions are implanted at a dose of 6.0 × 10 ¹² ions / cm ² and an implantation energy of 100 to 150 KeV, and a heat treatment at 900 ° C. to 1100 ° C. causes the drift region 6 of the LDMOS transistor. Is formed (step 2). Needless to say, the implantation of the P ions can be changed according to the breakdown voltage specification. The drift region 6 can be formed by multi-stage injection only by injection. Further, the drift region 6 may be formed on the entire surface of the high voltage MOS transistor region (see FIG. 14).

Subsequently, as shown in FIG. 3, by using well-known photolithography, the resist mask 7 is used to perform multi-stage implantation twice or more on the entire surface of the low breakdown voltage MOS transistor region and a partial region on the high breakdown voltage MOS transistor side. A p-type impurity, for example, B (boron) is ion-implanted to simultaneously form the p-type well 8 of the low breakdown voltage MOS transistor and the p-type body region 9 of the LDMOS transistor (step 3). In this embodiment, when the trench depth D1 of the gate end insulating portion 3 is 350 nm, B ions are implanted at a dose of 1.0 × 10 ¹³ ions / cm ² and an implantation energy of 200 KeV, and the dose is Ion implantation with an energy of 100 KeV at 7.0 × 10 ¹² ions / cm ² and an ion implantation with a dose of 5.0 × 10 ¹² ions / cm ² and an energy of 20 KeV for a total of three times. By doing so, the threshold voltage of the high voltage MOS transistor and the low voltage transistor can be controlled without affecting the junction breakdown voltage (for example, 30 V or more) of the high voltage MOS transistor (LDMOS transistor). Needless to say, in the ion implantation on the high energy side, the implantation energy and the dose amount are adjusted in accordance with the trench depth D1 of the gate end insulating portion 3 and the desired breakdown voltage of the high breakdown voltage MOS transistor.

  Subsequently, as shown in FIG. 4, the sacrificial oxide film 4 is removed, and the surface of the active region surrounded by the element isolation region 2 is thermally oxidized in an oxygen atmosphere at a temperature of 800 to 900 ° C. A gate oxide film 10 having a thickness of 3 to 15 nm for a breakdown voltage MOS transistor is formed (step 4). In the present embodiment, it is assumed that the gate oxide film 10 in step 4 is simultaneously formed on the active region on the high voltage MOS transistor side and used as the gate oxide film of the high voltage MOS transistor. The gate oxide film 10 may be a dielectric film deposited by a CVD method or the like instead of the thermal oxide film.

  Subsequently, as shown in FIG. 5, a first polysilicon layer serving as the gate electrodes of both the high voltage MOS transistor and the low voltage MOS transistor is deposited with a film thickness of 100 to 200 nm by a CVD method to obtain a predetermined plane. The gate electrode 11 of each MOS transistor is formed simultaneously by patterning with a visual pattern (step 5). Note that the overlap length Lx of the gate electrode 11 and the drift region 6 of the LDMOS transistor shown in FIG. 5 is referred to in the relationship between the on-resistance of the LDMOS transistor illustrated in FIG. 13 and the overlap length Lx.

Subsequently, as shown in FIG. 6, a resist mask 12 having the entire surface of the low breakdown voltage MOS transistor region is formed by using well-known photolithography, and the n-type impurity, the resist mask 12 and the gate electrode 11 are used as a mask. For example, LDD (Lightly Doped Drain) implantation of As (arsenic) ions is performed to form the LDD region 13 of the low breakdown voltage MOS transistor (Step 6). For example, the LDD implantation is performed with a dose amount of 2.0 × 10 ¹³ ions / cm ² and an implantation energy of 100 KeV. Here, Halo implantation using a p-type ion species may be simultaneously performed for short channel suppression. In the present embodiment, in addition to the low breakdown voltage MOS transistor region, a resist mask 12 in which a side portion on the source side of the gate electrode 11 of the high breakdown voltage MOS transistor and a part on the source side of the gate electrode 11 are used is used. Thus, the LDD region 13 similar to the low breakdown voltage MOS transistor is formed in the side portion on the source side of the gate electrode 11 of the high breakdown voltage MOS transistor, but the LDD region 13 on the high breakdown voltage MOS transistor side is necessary. It may be formed accordingly.

  Subsequently, as shown in FIG. 7, a silicon oxide film to be a sidewall insulating film 14 of the gate electrode 11 is deposited on the entire surface of the low breakdown voltage MOS transistor region and the high breakdown voltage MOS transistor region by a CDV method with a film thickness of 100 nm. Etch back is performed to form sidewall insulating films 14 on the sidewalls of the gate electrodes 11 of the low breakdown voltage MOS transistor and the high breakdown voltage MOS transistor (step 7). Note that another dielectric film may be deposited instead of the silicon oxide film.

Subsequently, as shown in FIG. 8, a resist mask that covers a region other than the n-type impurity implantation region having a predetermined plan view pattern (not shown) is formed, and the resist mask, the gate electrode 11 and the sidewall insulating film 14 are used as a mask. A type impurity, for example, As (arsenic) ions is implanted at a dose of 3.0 × 10 ¹⁵ ions / cm ² and an implantation energy of 40 KeV, and the source / drain region 15 of the low breakdown voltage MOS transistor and the high breakdown voltage MOS transistor The source region 16 and the drain region 17 are formed simultaneously (step 8). Subsequently, as shown in FIG. 8, a resist mask that covers a region other than the p-type impurity implantation region having a predetermined plan view pattern (not shown) is formed, and a p-type impurity such as boron (B) is formed using the resist mask as a mask. As an example, the ion implantation is performed at a dose of 3.0 × 10 ¹⁵ ions / cm ² and an implantation energy of 5 KeV to form the p-type high concentration diffusion region 18 and then at 700 to 850 ° C. in an inert gas atmosphere. Heat treatment is performed, or recovery of defects and activation of impurity ions by the high concentration ion implantation are performed by an RTA (Rapid Thermal Annealing) method or the like (step 9). In the high voltage MOS transistor, p type high concentration diffusion region 18 is electrically connected to p type body region 9. It is also possible to form silicide on the surfaces of the gate electrode 11, the source / drain region 15, the source region 16, and the drain region 17 by a known technique to reduce the resistance of each region.

  Subsequently, as shown in FIG. 9, an interlayer insulating film material (for example, P-SiO) is deposited to a thickness of 1000 nm by the CVD method, and planarized by the CMP method to form the interlayer insulating film 19 (step 10).

  Subsequently, as shown in FIG. 10, contact holes 20 reaching the respective surfaces of the source / drain region 15, the source region 16, the drain region 17, and the p-type high concentration diffusion region 18 are formed in the interlayer insulating film 19. Then, by a well-known technique, the contact hole 20 is filled with a conductive material, and the metal electrode 21 is formed on the contact hole 20 (step 11).

  As described above, the high voltage MOS transistor and the low voltage MOS transistor illustrated in FIG. 10 are formed through steps 1 to 11 shown in FIGS.

  FIG. 12 schematically shows the relationship between the trench depth D1 of the gate end insulating portion 3 formed in step 1 shown in FIG. 1, the element breakdown voltage Vtor and the on-resistance Ron of the LDMOS transistor. FIG. 13 shows the influence of the trench depth D1 of the gate end insulating portion 3 on the relationship between the overlap length Lx (see FIG. 5) of the gate electrode 11 and the drift region 6 of the LDMOS transistor and the on-resistance Ron of the LDMOS transistor. Is shown schematically.

  As shown in FIG. 12, the trench depth D1 of the gate end insulating portion 3 is increased within the shallow range as the trench depth D1 increases, but the device withstand voltage Vtor increases, but increases beyond the shallow range. However, the element withstand voltage Vtor does not increase any more. On the other hand, the on-resistance Ron tends to increase as the trench depth D1 increases. Therefore, in the present embodiment, as the trench withstand voltage Vtor, the trench depth D1 is a depth A slightly exceeding the shallow range described above and smaller than the trench depth D2 of the element isolation region 2. While maintaining the same level as before, the on-resistance Ron is greatly reduced.

  Further, as shown in FIG. 13, as the overlap length Lx between the gate electrode 11 of the LDMOS transistor and the drift region 6 becomes larger, the channel length becomes shorter, so the on-resistance Ron is lowered, but the gate end insulating portion is reduced. When the trench depth D1 of 3 is large, the current path from the drain region 17 to the source region 16 greatly detours below the gate end insulating portion 3, and the decrease in the on-resistance Ron is suppressed. As a result, a relationship between the on-resistance Ron and the trench depth D1 as shown in FIG. 12 is exhibited.

[Another embodiment]
Hereinafter, another embodiment of the semiconductor device of the above embodiment and a method for manufacturing the semiconductor device will be described.

  <1> In the above embodiment, the case where the high breakdown voltage MOS transistor and the low breakdown voltage MOS transistor are n-type channel MOS transistors has been described. However, an n-type semiconductor substrate is used or an n-type well is formed, By changing the n-type impurity species to p-type and the p-type impurity species to n-type in each of the n-type or p-type impurity implantation steps (steps 2, 3, 6, 8, and 9), The manufacturing process and transistor structure described in the above embodiment can also be applied to a p-channel MOS transistor.

  <2> Further, a semiconductor device in which an n-channel type high-voltage MOS transistor and a p-channel type high-voltage MOS transistor are mixedly mounted, or an n-channel type low-voltage MOS transistor and a p-channel type low-voltage MOS transistor are mixedly mounted. Alternatively, a semiconductor device may be formed.

  In this case, in each of the n-type or p-type impurity implantation steps (steps 2, 3, 6, 8, and 9), n-channel high breakdown voltage and low breakdown voltage MOS transistors are implanted and p-channel high breakdown voltage and low breakdown voltage. Implantation of MOS transistors may be performed alternately by masking areas other than the respective formation regions.

  <3> Furthermore, in the above embodiment, the LDMOS transistor as shown in FIG. 10 is assumed as the high voltage MOS transistor. However, even in the case of the same LDMOS transistor, the drift region 6 is formed as a p-type as shown in FIG. It may be formed on the entire surface of the high voltage MOS transistor region so as to include the body region 9. Further, as a high voltage MOS transistor, as shown in FIG. 15, a gate end insulating portion 3 is provided at both ends of the source side and the drain side of the gate electrode 11 as a symmetric structure between the drain and source. Anyway. In this case, it is preferable to form drift region 6 on the source side instead of p-type body region 9.

  Further, when the gate end insulating portion 3 is provided at both the source side and drain side ends of the gate electrode 11, when the required breakdown voltage differs between the gate and the source and between the gate and the drain, When the breakdown voltage between the drains is higher than the breakdown voltage between the gate and the source, the trench depth D1s of the gate end insulating part 3 on the source side is set to the trench of the gate end insulating part 3 on the drain side as shown in FIG. It may be formed shallower than the depth D1d. In this case, the trench depths D1s and D1d can be adjusted as described above by making the width Wges of the gate-side insulating part 3 on the source side narrower than the width Wged of the gate-side insulating part 3 on the drain side.

  <4> Further, in the above embodiment and another embodiment <3>, the gate end insulating portion 3 is provided only at the drain side end of the gate electrode 11 as shown in FIG. One of the high breakdown voltage MOS transistors having the structure and the high breakdown voltage MOS transistor having the structure in which the gate end insulating portion 3 is provided at both ends of the source side and the drain side of the gate electrode 11 as shown in FIG. 15 or FIG. Although semiconductor devices having different types are assumed, two or more types of high voltage MOS transistors may be mixedly mounted on the same silicon substrate. In this case, two or more types of high voltage MOS transistors having different trench depths D1 of the gate end insulating portion 3 may be provided for one of the transistor structures shown in FIGS. High voltage MOS transistors having two or more transistor structures out of the transistor structures shown in FIGS. 10 and 14 to 16 may be provided, or the former and the latter may be combined.

  When the trench depth D1 of the gate end insulating portion 3 of two or more types of high voltage MOS transistors is made different according to the voltage resistance required for each high voltage MOS transistor, the high voltage MOS having a large trench depth D1. The width of the gate end insulating portion 3 is increased as the transistor is used.

  Furthermore, when two or more types of high voltage MOS transistors are mixedly mounted on the same silicon substrate, it is preferable to use at least one type of high voltage MOS transistor as an ESD protection element.

  <5> Dimensions of each part, implantation conditions in each impurity implantation step (steps 2, 3, 6, 8, 9), and heat treatment exemplified in the manufacturing process of the high breakdown voltage and low breakdown voltage MOS transistors described in the above embodiment The temperature and the like are merely examples, and are not limited to the numerical values and numerical ranges exemplified in the above embodiment.

  <6> In the above embodiment, it is assumed that a high voltage MOS transistor and a low voltage MOS transistor are mounted on the same silicon substrate, but one or more types of high voltage MOS transistors are mounted on the same silicon substrate. Even when the low breakdown voltage MOS transistor is not mounted, the manufacturing process and transistor structure described in the above embodiment can be applied.

  Furthermore, even when a high voltage MOS transistor and a low voltage MOS transistor are mounted on the same silicon substrate, the film thicknesses of the gate oxide films of the high voltage MOS transistor and the low voltage MOS transistor are both MOS transistors. It doesn't have to be the same.

1: Semiconductor substrate (silicon substrate)
2: element isolation region 3: gate end insulating portion 4: sacrificial oxide film 5: resist mask 6: drift region 7: resist mask 8: p-type well 9: p-type body region 10: gate oxide film 11: gate electrode 12: Resist mask 13: LDD region 14: Side wall insulating film 15: Source / drain region of low breakdown voltage MOS transistor 16: Source region of high breakdown voltage MOS transistor 17: Drain region of high breakdown voltage MOS transistor 18: P-type high concentration diffusion region 19: Interlayer insulating film 20: Contact hole 21: Metal electrode

Claims (9)

An element isolation region formed on a semiconductor substrate by an STI (Shallow Trench Isolation) method, an active region partitioned by the element isolation region, a source region and a drain region formed separately from each other in the active region, and Having one or more types of high-breakdown-voltage transistors having a MOS transistor structure comprising a gate portion formed by laminating a gate insulating film and a gate electrode on the surface of the semiconductor substrate between the source region and the drain region;
A gate end insulating portion formed by filling an insulator in a groove formed in the semiconductor substrate below the surface of the semiconductor substrate at the end of the gate portion of the high breakdown voltage transistor;
A width of the gate end insulating portion is narrower than a minimum width of the element isolation region;
The depth of the gate end insulating portion from the surface of the semiconductor substrate is larger than the thickness of the gate insulating film of the high breakdown voltage transistor and smaller than the depth of the element isolation region from the surface of the semiconductor substrate. Semiconductor device.   2. The semiconductor device according to claim 1, wherein one type of the high-breakdown-voltage transistors has the gate end insulating portion only at the end of the gate portion on the drain region side.   3. The one or more types of the high breakdown voltage transistors each include the gate end insulating portion at each end of the gate portion on the drain region side and the source region side. A semiconductor device according to 1. One of the high breakdown voltage transistors has the gate end insulating portion at each end of the gate portion on the drain region side and the source region side,
The depth of the end of the drain region from the surface of the semiconductor substrate of the gate end insulating portion is different from the depth of the end of the source region of the gate end insulating portion from the surface of the semiconductor substrate. The semiconductor device according to claim 1. Having one or more low breakdown voltage transistors of the MOS type transistor structure having a lower breakdown voltage than the high breakdown voltage transistor;
5. The semiconductor device according to claim 1, wherein the gate end insulating portion is not formed below the surface of the semiconductor substrate at an end portion of the gate portion of the low breakdown voltage transistor. .   6. The semiconductor device according to claim 5, wherein the gate insulating film of the high breakdown voltage transistor and the gate insulating film of the low breakdown voltage transistor have the same film thickness.   The semiconductor device according to claim 1, further comprising two or more types of the high breakdown voltage transistors having different depths of the gate end insulating portion from the surface of the semiconductor substrate.   8. The semiconductor device according to claim 7, wherein one of the two or more types of high breakdown voltage transistors is used as an ESD protection element. A method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the groove of the element isolation region and the groove of the gate end insulating portion are simultaneously formed on the semiconductor substrate by etching with an etching angle adjusted between 45 ° and 80 °. .