US20070120182A1 - Transistor having recess gate structure and method for fabricating the same - Google Patents

Transistor having recess gate structure and method for fabricating the same Download PDF

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Publication number
US20070120182A1
US20070120182A1 US11/450,118 US45011806A US2007120182A1 US 20070120182 A1 US20070120182 A1 US 20070120182A1 US 45011806 A US45011806 A US 45011806A US 2007120182 A1 US2007120182 A1 US 2007120182A1
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Prior art keywords
trenches
gate
layer
semiconductor substrate
transistor
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US11/450,118
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Kyoung Rouh
Seung Jin
Min Lee
Yong Jung
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JIN, SEUNG WOO, JUNG, YONG SOO, LEE, MIN YONG, ROUH, KYOUNG BONG
Publication of US20070120182A1 publication Critical patent/US20070120182A1/en
Priority to US12/603,906 priority Critical patent/US7790551B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer

Definitions

  • the invention relates to a transistor and a method for fabricating the same, and more particularly to a transistor having a recess gate structure and a method for fabricating the same.
  • the width of gates of transistors forming the semiconductor device has gradually decreased.
  • the concentration of impurities at junction regions and channels has gradually increased and the intensity of the electric field between a source region and a drain region has gradually increased. Electrons accelerate between the source region and the drain region due to the increased intensity of the electric field, thus generating a large number of hot carriers attacking a gate insulating layer close to the drain region. The hot carriers deteriorate electrical characteristics of the semiconductor device.
  • a leakage current is generated due to the increase of the intensity of an electric field between a source region and a drain region, thus exerting a bad influence on the refresh characteristic, which is one of the more important characteristics of the DRAM.
  • methods for fabricating the semiconductor device have several problems, as follows. Since the distance between the source region and the drain region is reduced, a punch-through margin is gradually decreased, and thus, the method further requires ion implantation for stopping punch-through. Particularly, a method for fabricating the DRAM further requires planarization of a landing plug for improving the refresh characteristic. That is, additional steps, which do not directly relate to the operation of the semiconductor device, are required in the manufacturing process.
  • LDD lightly doped drain
  • the length of gates is increased.
  • the increase of the length of the gates exerts a bad influence on the integration of the semiconductor device.
  • the increase of the length of channels reduces the saturation current of a drain.
  • the invention provides a transistor having a recess gate structure and a method for fabricating the same.
  • the invention provides a transistor having a recess gate structure comprising a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate and separated from the upper portions of the first trenches by the channel regions.
  • the gate insulating layer may be an oxide layer
  • the gate conductive layer may be a polysilicon layer
  • the gate electrodes may be made of a metal layer.
  • the surfaces of the source/drain regions are preferably located at the same level as the surfaces of the gate conductive layer and the gate electrodes.
  • the transistor may further include a capping layer pattern formed on the gate conductive layer and the gate electrodes for selectively exposing the surfaces of the gate electrodes.
  • the capping layer pattern may include a nitride layer.
  • the invention provides a method for fabricating a transistor having a recess gate structure including the steps of forming first trenches having a designated depth in a semiconductor substrate; forming channel regions in the semiconductor substrate having the first trenches formed therein along the first trenches by ion implantation; forming a gate insulating layer on the semiconductor substrate having the channel regions formed therein; forming a gate conductive layer on the gate insulating layer, to form second trenches in the first trenches; forming gate electrodes filling the second trenches; partially removing the upper portions of the gate electrode, the gate conductive layer, and the semiconductor substrate by planarization; and implanting impurity ions into the semiconductor substrate exposed by the planarization, to form source/drain regions.
  • the depth of the first trenches is less than 2,000 ⁇ .
  • the method may further include the step of cleaning the semiconductor substrate using CFO 2 or CF 4 gas after the formation of the first trenches.
  • the method may further include the step of forming a liner oxide layer after the formation of the first trenches.
  • the method may further include the step of performing an annealing process after the formation of the first trenches.
  • FIG. 1 is a sectional view of a transistor having a recess gate structure in accordance with the invention.
  • FIGS. 2 to 5 are sectional views illustrating a method for fabricating a transistor having a recess gate structure in accordance with the invention.
  • FIG. 1 is a sectional view of a transistor having a recess gate structure in accordance with the invention.
  • a gate insulating layer 120 is disposed in first trenches 102 formed in a semiconductor substrate 100 .
  • the first trenches 102 have a depth of 2,000 ⁇ or less.
  • an oxide layer is illustratively used as the gate insulating layer 120
  • other insulating layers or a ferroelectric layer may be used as the gate insulating layer 120 .
  • the gate insulating layer 120 has a multi-layered structure having at least two layers.
  • a polysilicon layer 130 serving as a gate conductive layer is formed on the gate insulating layer 120 .
  • the polysilicon layer 130 has a thickness so as not to completely fill the first trench 102 .
  • second trenches 132 having a width smaller than that of the first trenches 102 are formed by the polysilicon layer 130 .
  • Gate electrodes 140 filling the second trenches 132 are formed on the polysilicon layer 130 .
  • the gate electrodes 140 are made of a metal layer or a metal silicide layer. The whole surfaces of the gate electrodes 140 are surrounded by the polysilicon layer 130 .
  • Channel regions 104 are disposed in the semiconductor substrate 100 along the first trenches 102 , and source/drain regions 106 are disposed at both sides of the first trenches 102 in a shallow portion of the semiconductor substrate 100 .
  • the surfaces of the source/drain regions 106 are located at the same level as the surfaces of the polysilicon layer 130 and the gate electrodes 140 .
  • the source/drain regions 106 are separated from the upper portions of the first trenches 102 by the channel regions 104 .
  • a capping layer pattern 150 is disposed on the upper surfaces of the gate insulating layer 120 , the polysilicon layer 130 and the gate electrodes 140 .
  • the capping layer pattern 150 serves to prevent breakdown or current leakage at recess gates, and is made of a nitride layer.
  • the capping layer pattern 150 has openings, each of which exposes a part of the surface of each of the gate electrodes 140 , in which a contact is formed.
  • An insulating layer 160 is disposed on the semiconductor substrate 100 .
  • a source/drain metal layer 170 is connected to the source/drain regions 106 via holes formed through the insulating layer 160
  • a gate metal layer 180 is connected to the gate electrodes 140 via other holes formed through the insulating layer 160 and the openings of the capping layer pattern 150 .
  • a transistor of the invention has recess gates disposed in the first trenches 102 of the semiconductor substrate 100 .
  • This recess gates do not require a gate spacer layer, which is necessary to insulate conventional planar gates from other parts.
  • the source/drain regions 106 are located on the gates, it is possible to increase a short channel margin and assure a punch-through margin. Accordingly, the transistor having the recess gates does not require an LDD structure, and obtains high-concentration source/drain regions, thus ensuring a sufficient amount of current and performing a high-speed switching operation.
  • the surfaces of the source/drain regions 106 are located at the same level as the surfaces of the polysilicon layer 130 and the gate electrodes 140 , thus preventing the generation of a difference of heights between the semiconductor substrate 100 and the gates when the insulating layer 160 is formed on the semiconductor substrate 100 . Further, when the transistor having the above recess gates is applied to a semiconductor memory, such as a DRAM, it is possible to omit additional steps, such as planarization of a landing plug.
  • FIGS. 2 to 5 are sectional views illustrating a method for fabricating a transistor having a recess gate structure in accordance with the invention.
  • a mask layer pattern 110 is formed on the semiconductor substrate 100 , such as a silicon substrate.
  • the mask layer pattern 110 is made of a photoresist layer.
  • the mask layer pattern 110 has openings for exposing the surfaces of regions of the semiconductor substrate 100 , i.e., regions on which recess gates will be formed. Thereafter, the exposed regions of the semiconductor substrate 100 are etched to a designated depth, for example, less than 2,000 ⁇ , using the mask layer pattern 110 as an etching mask, thus forming the first trenches 102 .
  • the surface of the semiconductor substrate 100 may be cleaned using CFO 4 gas or CF 4 gas. Further, a liner oxide layer may be formed on the inner walls of the first trenches 102 , or annealing may be performed. After the first trenches 102 are formed, the mask layer pattern 110 is removed from the surface of the semiconductor substrate 100 .
  • the gate insulating layer 120 is formed on the whole surface of the semiconductor substrate 100 having the first trenches 102 formed therein.
  • an oxide layer formed by thermal oxidation is illustratively used as the gate insulating layer 120
  • other insulating layers or a ferroelectric layer, if necessary, may be used as the gate insulating layer 120 .
  • the gate insulating layer 120 has a multi-layered structure having at least two layers.
  • the channel regions 104 are formed along the circumferences of the first trenches 102 by channel ion implantation. During the channel ion implantation, ions are implanted into the first trenches 102 at a tilt, as shown by arrows of FIG. 3 .
  • ion implantation for adjusting a threshold voltage may be performed.
  • the polysilicon layer 130 serving as a gate conductive layer is formed on the gate insulating layer 120 .
  • the polysilicon layer 130 has a thickness so as not to completely fill the first trenches 102 .
  • the second trenches 132 having a width smaller than that of the first trenches 102 are formed by the polysilicon layer 130 .
  • the gate electrodes 140 completely filling the second trenches 132 are formed on the polysilicon layer 130 .
  • the gate electrodes 140 are made of a metal layer or a metal silicide layer.
  • planarization of the structure of FIG. 4 is performed.
  • the planarization uses chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the upper portion of the semiconductor substrate 100 having a designated thickness is eliminated by the planarization.
  • Impurities are implanted into the semiconductor substrate 100 , which is exposed to the outside by the planarization, using ion implantation, thus forming the source/drain regions 106 .
  • a capping layer 152 is formed on the upper surfaces of the gate insulating layer 120 , the polysilicon layer 130 and the gate electrodes 140 .
  • a nitride layer may be used as the capping layer 152 .
  • the capping layer 152 is patterned, thus forming the capping layer pattern 150 for selectively exposing the surfaces of the gate electrodes 140 , the insulating layer 160 is formed on the whole surface of the semiconductor substrate 100 , and the source/drain metal layer 170 and the gate metal layer 180 , which are respectively connected to the source/drain regions 106 and the gate electrodes 140 via the holes formed through the insulating layer 160 , are formed.
  • another method which differs from the above method as shown in FIGS. 2 to 5 , may be used to fabricate a transistor having a recess gate structure of the invention.
  • gates are formed in a semiconductor substrate using a mask, an epitaxial layer is grown at both sides of the gates, and source/drain regions are formed in the epitaxial layer, thereby forming recess gates.
  • the epitaxial layer may be formed at the source/drain regions by doping, or the epitaxial layer may be formed at one region of the source/drain regions by doping and ions may be implanted into the other region of the source/drain regions.
  • the invention provides a transistor having a recess gate structure and a method for fabricating the same.
  • the transistor of the invention does not require a gate spacer layer, which is necessary to insulate conventional planar gates from other parts, and has source/drain regions located on the gates, thus increasing a short channel margin and assuring a punch through margin. Accordingly, the transistor of the invention does not require an LDD structure, and obtains high-concentration source/drain regions, thus ensuring a sufficient amount of current and performing a high-speed switching operation.
  • the surfaces of the source/drain regions are located at the same level as the surfaces of a polysilicon layer and gate electrodes, thus preventing the generation of a difference of heights between the semiconductor substrate and gates when the insulating layer is formed on the semiconductor substrate.
  • a semiconductor memory such as a DRAM

Abstract

A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to a transistor and a method for fabricating the same, and more particularly to a transistor having a recess gate structure and a method for fabricating the same.
  • 2. Description of the Related Art
  • As the degree of integration of semiconductor devices has rapidly increased, the width of gates of transistors forming the semiconductor device has gradually decreased. In order to facilitate this trend, the concentration of impurities at junction regions and channels has gradually increased and the intensity of the electric field between a source region and a drain region has gradually increased. Electrons accelerate between the source region and the drain region due to the increased intensity of the electric field, thus generating a large number of hot carriers attacking a gate insulating layer close to the drain region. The hot carriers deteriorate electrical characteristics of the semiconductor device. Particularly, in a semiconductor memory, such as a DRAM, a leakage current is generated due to the increase of the intensity of an electric field between a source region and a drain region, thus exerting a bad influence on the refresh characteristic, which is one of the more important characteristics of the DRAM.
  • In addition to the foregoing structural problems, methods for fabricating the semiconductor device have several problems, as follows. Since the distance between the source region and the drain region is reduced, a punch-through margin is gradually decreased, and thus, the method further requires ion implantation for stopping punch-through. Particularly, a method for fabricating the DRAM further requires planarization of a landing plug for improving the refresh characteristic. That is, additional steps, which do not directly relate to the operation of the semiconductor device, are required in the manufacturing process.
  • In order to suppress the generation of hot carriers, a method for forming source and drain regions having a lightly doped drain (LDD) structure is most widely used. When the semiconductor device employs the LDD structure, the intensity of an electrical field between the source region and the drain region is decreased, but the concentration of impurities at both ends of a channel region is relatively decreased and thereby the amount of current is simultaneously decreased, thus obstructing high-speed switching operation of the semiconductor device.
  • Accordingly, in order to assist the high-speed switching operation of the semiconductor device and prevent the degradation of the semiconductor device due to the hot carriers, the length of gates is increased. However, the increase of the length of the gates exerts a bad influence on the integration of the semiconductor device. Further, the increase of the length of channels reduces the saturation current of a drain.
    • SUMMARY OF THE INVENTION
  • The invention provides a transistor having a recess gate structure and a method for fabricating the same.
  • In accordance with one aspect, the invention provides a transistor having a recess gate structure comprising a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate and separated from the upper portions of the first trenches by the channel regions.
  • In preferred forms, the gate insulating layer may be an oxide layer, the gate conductive layer may be a polysilicon layer, and the gate electrodes may be made of a metal layer.
  • The surfaces of the source/drain regions are preferably located at the same level as the surfaces of the gate conductive layer and the gate electrodes.
  • The transistor may further include a capping layer pattern formed on the gate conductive layer and the gate electrodes for selectively exposing the surfaces of the gate electrodes.
  • The capping layer pattern may include a nitride layer.
  • In accordance with another aspect, the invention provides a method for fabricating a transistor having a recess gate structure including the steps of forming first trenches having a designated depth in a semiconductor substrate; forming channel regions in the semiconductor substrate having the first trenches formed therein along the first trenches by ion implantation; forming a gate insulating layer on the semiconductor substrate having the channel regions formed therein; forming a gate conductive layer on the gate insulating layer, to form second trenches in the first trenches; forming gate electrodes filling the second trenches; partially removing the upper portions of the gate electrode, the gate conductive layer, and the semiconductor substrate by planarization; and implanting impurity ions into the semiconductor substrate exposed by the planarization, to form source/drain regions.
  • Preferably, the depth of the first trenches is less than 2,000 Å.
  • The method may further include the step of cleaning the semiconductor substrate using CFO2 or CF4 gas after the formation of the first trenches.
  • The method may further include the step of forming a liner oxide layer after the formation of the first trenches.
  • The method may further include the step of performing an annealing process after the formation of the first trenches.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The features and advantages of the invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a sectional view of a transistor having a recess gate structure in accordance with the invention; and
  • FIGS. 2 to 5 are sectional views illustrating a method for fabricating a transistor having a recess gate structure in accordance with the invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Preferred embodiments of the invention are described in detail below with reference to the drawings.
  • FIG. 1 is a sectional view of a transistor having a recess gate structure in accordance with the invention.
  • With reference to FIG. 1, a gate insulating layer 120 is disposed in first trenches 102 formed in a semiconductor substrate 100. The first trenches 102 have a depth of 2,000 Å or less. Although an oxide layer is illustratively used as the gate insulating layer 120, other insulating layers or a ferroelectric layer may be used as the gate insulating layer 120. Further, the gate insulating layer 120 has a multi-layered structure having at least two layers. A polysilicon layer 130 serving as a gate conductive layer is formed on the gate insulating layer 120. The polysilicon layer 130 has a thickness so as not to completely fill the first trench 102. Thus, second trenches 132 having a width smaller than that of the first trenches 102 are formed by the polysilicon layer 130. Gate electrodes 140 filling the second trenches 132 are formed on the polysilicon layer 130. The gate electrodes 140 are made of a metal layer or a metal silicide layer. The whole surfaces of the gate electrodes 140 are surrounded by the polysilicon layer 130.
  • Channel regions 104 are disposed in the semiconductor substrate 100 along the first trenches 102, and source/drain regions 106 are disposed at both sides of the first trenches 102 in a shallow portion of the semiconductor substrate 100. The surfaces of the source/drain regions 106 are located at the same level as the surfaces of the polysilicon layer 130 and the gate electrodes 140. The source/drain regions 106 are separated from the upper portions of the first trenches 102 by the channel regions 104. A capping layer pattern 150 is disposed on the upper surfaces of the gate insulating layer 120, the polysilicon layer 130 and the gate electrodes 140. The capping layer pattern 150 serves to prevent breakdown or current leakage at recess gates, and is made of a nitride layer. The capping layer pattern 150 has openings, each of which exposes a part of the surface of each of the gate electrodes 140, in which a contact is formed. An insulating layer 160 is disposed on the semiconductor substrate 100. A source/drain metal layer 170 is connected to the source/drain regions 106 via holes formed through the insulating layer 160, and a gate metal layer 180 is connected to the gate electrodes 140 via other holes formed through the insulating layer 160 and the openings of the capping layer pattern 150.
  • Depending on the above structure, a transistor of the invention has recess gates disposed in the first trenches 102 of the semiconductor substrate 100. This recess gates do not require a gate spacer layer, which is necessary to insulate conventional planar gates from other parts. Further, since the source/drain regions 106 are located on the gates, it is possible to increase a short channel margin and assure a punch-through margin. Accordingly, the transistor having the recess gates does not require an LDD structure, and obtains high-concentration source/drain regions, thus ensuring a sufficient amount of current and performing a high-speed switching operation. Particularly, the surfaces of the source/drain regions 106 are located at the same level as the surfaces of the polysilicon layer 130 and the gate electrodes 140, thus preventing the generation of a difference of heights between the semiconductor substrate 100 and the gates when the insulating layer 160 is formed on the semiconductor substrate 100. Further, when the transistor having the above recess gates is applied to a semiconductor memory, such as a DRAM, it is possible to omit additional steps, such as planarization of a landing plug.
  • FIGS. 2 to 5 are sectional views illustrating a method for fabricating a transistor having a recess gate structure in accordance with the invention.
  • First, with reference to FIG. 2, a mask layer pattern 110 is formed on the semiconductor substrate 100, such as a silicon substrate. The mask layer pattern 110 is made of a photoresist layer. The mask layer pattern 110 has openings for exposing the surfaces of regions of the semiconductor substrate 100, i.e., regions on which recess gates will be formed. Thereafter, the exposed regions of the semiconductor substrate 100 are etched to a designated depth, for example, less than 2,000 Å, using the mask layer pattern 110 as an etching mask, thus forming the first trenches 102. After the first trenches 102 are formed, in order to recover damage to the surface of the semiconductor substrate 100 by etching, the surface of the semiconductor substrate 100 may be cleaned using CFO4 gas or CF4 gas. Further, a liner oxide layer may be formed on the inner walls of the first trenches 102, or annealing may be performed. After the first trenches 102 are formed, the mask layer pattern 110 is removed from the surface of the semiconductor substrate 100.
  • Thereafter, with reference to FIG. 3, the gate insulating layer 120 is formed on the whole surface of the semiconductor substrate 100 having the first trenches 102 formed therein. Although an oxide layer formed by thermal oxidation is illustratively used as the gate insulating layer 120, other insulating layers or a ferroelectric layer, if necessary, may be used as the gate insulating layer 120. Further, the gate insulating layer 120 has a multi-layered structure having at least two layers. Then, the channel regions 104 are formed along the circumferences of the first trenches 102 by channel ion implantation. During the channel ion implantation, ions are implanted into the first trenches 102 at a tilt, as shown by arrows of FIG. 3. Although not shown in drawings, ion implantation for adjusting a threshold voltage may be performed.
  • Then, with reference to FIG. 4, the polysilicon layer 130 serving as a gate conductive layer is formed on the gate insulating layer 120. The polysilicon layer 130 has a thickness so as not to completely fill the first trenches 102. Thus, the second trenches 132 having a width smaller than that of the first trenches 102 are formed by the polysilicon layer 130. Then, the gate electrodes 140 completely filling the second trenches 132 are formed on the polysilicon layer 130. The gate electrodes 140 are made of a metal layer or a metal silicide layer.
  • With reference to FIG. 5, planarization of the structure of FIG. 4 is performed. The planarization uses chemical mechanical polishing (CMP). As shown by a dotted line (A), the upper portion of the semiconductor substrate 100 having a designated thickness is eliminated by the planarization. Impurities are implanted into the semiconductor substrate 100, which is exposed to the outside by the planarization, using ion implantation, thus forming the source/drain regions 106. Then, a capping layer 152 is formed on the upper surfaces of the gate insulating layer 120, the polysilicon layer 130 and the gate electrodes 140. A nitride layer may be used as the capping layer 152.
  • Then, as shown in FIG. 1, the capping layer 152 is patterned, thus forming the capping layer pattern 150 for selectively exposing the surfaces of the gate electrodes 140, the insulating layer 160 is formed on the whole surface of the semiconductor substrate 100, and the source/drain metal layer 170 and the gate metal layer 180, which are respectively connected to the source/drain regions 106 and the gate electrodes 140 via the holes formed through the insulating layer 160, are formed.
  • On the other hand, another method, which differs from the above method as shown in FIGS. 2 to 5, may be used to fabricate a transistor having a recess gate structure of the invention. For example, gates are formed in a semiconductor substrate using a mask, an epitaxial layer is grown at both sides of the gates, and source/drain regions are formed in the epitaxial layer, thereby forming recess gates. In this case, the epitaxial layer may be formed at the source/drain regions by doping, or the epitaxial layer may be formed at one region of the source/drain regions by doping and ions may be implanted into the other region of the source/drain regions.
  • As apparent from the foregoing description, the invention provides a transistor having a recess gate structure and a method for fabricating the same. The transistor of the invention does not require a gate spacer layer, which is necessary to insulate conventional planar gates from other parts, and has source/drain regions located on the gates, thus increasing a short channel margin and assuring a punch through margin. Accordingly, the transistor of the invention does not require an LDD structure, and obtains high-concentration source/drain regions, thus ensuring a sufficient amount of current and performing a high-speed switching operation. Particularly, the surfaces of the source/drain regions are located at the same level as the surfaces of a polysilicon layer and gate electrodes, thus preventing the generation of a difference of heights between the semiconductor substrate and gates when the insulating layer is formed on the semiconductor substrate. Further, when the transistor of the invention is applied to a semiconductor memory, such as a DRAM, it is possible to omit additional steps, such as planarization of a landing plug.
  • Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.

Claims (10)

1. A transistor having a recess gate structure comprising:
a gate insulating layer formed on inner walls of first trenches formed in a semiconductor substrate;
a gate conductive layer formed on the gate insulating layer for partially filling the first trenches;
gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer;
channel regions formed in the semiconductor substrate along the first trenches; and
source/drain regions formed in a shallow portion of the semiconductor substrate and separated from the upper portions of the first trenches by the channel regions.
2. The transistor of claim 1, wherein the gate insulating layer is an oxide layer, the gate conductive layer is a polysilicon layer, and the gate electrodes are made of a metal layer.
3. The transistor of claim 1, wherein the surfaces of the source/drain regions are located at the same level as the surfaces of the gate conductive layer and the gate electrodes.
4. The transistor of claim 1, further comprising a capping layer pattern formed on the gate conductive layer and the gate electrodes for selectively exposing the surfaces of the gate electrodes.
5. The transistor of claim 4, wherein the capping layer pattern includes a nitride layer.
6. A method for fabricating a transistor having a recess gate structure comprising:
forming first trenches having a designated depth in a semiconductor substrate;
forming channel regions in the semiconductor substrate having the first trenches formed therein along the first trenches by ion implantation;
forming a gate insulating layer on the semiconductor substrate having the channel regions formed therein;
forming a gate conductive layer on the gate insulating layer, to form second trenches in the first trenches;
forming gate electrodes filling the second trenches;
partially removing the upper portions of the gate electrode, the gate conductive layer, and the semiconductor substrate by planarization; and
implanting impurity ions into the semiconductor substrate exposed by the planarization, to form source/drain regions.
7. The method of claim 6, wherein the depth of the first trenches 2,000 Å or less.
8. The method of claim 6, further comprising cleaning the semiconductor substrate using CFO2 or CF4 gas after forming the first trenches.
9. The method of claim 6, further comprising forming a liner oxide layer after forming the first trenches.
10. The method of claim 6, further comprising performing an annealing process after forming the first trenches.
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