KR20080081550A - Mosfet device and method of mamufacturing the same - Google Patents

Mosfet device and method of mamufacturing the same Download PDF

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Publication number
KR20080081550A
KR20080081550A KR1020070021690A KR20070021690A KR20080081550A KR 20080081550 A KR20080081550 A KR 20080081550A KR 1020070021690 A KR1020070021690 A KR 1020070021690A KR 20070021690 A KR20070021690 A KR 20070021690A KR 20080081550 A KR20080081550 A KR 20080081550A
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South Korea
Prior art keywords
gate
silicon
layer
oxide film
groove
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KR1020070021690A
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Korean (ko)
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이상호
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주식회사 하이닉스반도체
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Priority to KR1020070021690A priority Critical patent/KR20080081550A/en
Publication of KR20080081550A publication Critical patent/KR20080081550A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The MOSFET device includes a silicon substrate; An oxide film formed on the silicon substrate; A silicon layer formed on the oxide film; A gate formed on the silicon layer; And a source / drain region formed in the silicon layers on both sides of the gate, wherein the thickness of the silicon layer, the oxide layer, and the silicon substrate is recessed so that a gate groove is provided, and the gay groove is formed. A silicon epitaxial layer is formed on the silicon layer including a silicon epitaxial layer along a profile of the gate groove, the gate is formed on the silicon epitaxial layer of the gate groove, and the source / drain region includes the silicon epitaxial layer. It is formed into an elevated structure within.

Description

MOSFET device and its manufacturing method {MOSFET DEVICE AND METHOD OF MAMUFACTURING THE SAME}

1 is a cross-sectional view for explaining a MOSFET device according to an embodiment of the present invention.

Figure 2a to 2g is a cross-sectional view for each process for explaining the manufacturing method of the MOSFET device according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a MOSFET device according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100,200,300: silicon substrate 110,210,310: oxide film

120,220,320: Silicon layer H: Gate groove

130,230,330: Silicon epitaxial layer 132,232,332: Gate insulating film

134,234,334: Gate conductive film 136,236,336: Hard mask film

140,240,340: Gate 150,250,350: Spacer film

160,260,360: source / drain regions

The present invention relates to a MOSFET device and a method of manufacturing the same, and more particularly, to a MOSFET device and a method of manufacturing the same that can improve the characteristics of the semiconductor device by improving the short channel effect (Short Channel Effect).

As the design rules of MOSFETs, which are being developed recently, have decreased, the dose of the cell's threshold voltage ion implantation has been increasing to meet the cell's threshold voltage (Vt) target.

However, this phenomenon causes a so-called short channel effect in which the leakage current of the cell and the threshold voltage are drastically lowered as the device becomes more integrated, and also, the electric field (Electron Field) This increases the junction leakage current with the increase of) and deteriorates the refresh characteristics of the device.

Recently, various techniques for preventing a problem of deterioration of electrical characteristics of a device due to high integration of semiconductor devices have been proposed. For example, as one of methods for improving the short channel effect, a silicon on insulator (SOI) transistor is proposed. Is applied.

The SOI transistor has a structure in which an oxide film is formed on a silicon substrate, a silicon layer is deposited on the oxide film, and a transistor is formed on the silicon layer, and the effective channel length of the transistor is increased to increase the effective channel length. The short channel effect can be improved, and also minimizes the drain-induced barrier lowering (DIBL) phenomenon in which interference between source / drain regions occurs.

However, in the SOI transistor, since the silicon layer formed on the oxide film is in a floating state, it is difficult to control the silicon layer. That is, the potential of the silicon layer changes due to hot carriers generated during operation of the transistor, and thus, the characteristics of the semiconductor device are degraded, such as a threshold voltage (Vt).

Accordingly, the present invention provides a MOSFET device and a method of manufacturing the same which can improve the characteristics of semiconductor devices by effectively improving the short channel effect when applying a silicon on insulator (SOI) transistor.

In one embodiment, the MOSFET device comprises a silicon substrate; An oxide film formed on the silicon substrate; A silicon layer formed on the oxide film; A gate formed on the silicon layer; And a source / drain region formed in the silicon layers on both sides of the gate, wherein the thickness of the silicon layer, the oxide layer, and the silicon substrate is recessed so that a gate groove is provided, and the gay groove is formed. A silicon epitaxial layer is formed on the silicon layer including a silicon epitaxial layer along a profile of the gate groove, the gate is formed on the silicon epitaxial layer of the gate groove, and the source / drain region includes the silicon epitaxial layer. It is formed into an elevated structure within.

Here, the gate groove is formed such that a channel portion below the gate is disposed above the oxide film.

The gate groove is formed such that a channel portion below the gate is disposed below the oxide film.

The source / drain region having the raised structure is formed to a depth not in contact with the oxide film.

In another embodiment, a method of manufacturing a MOSFET device may include forming an oxide film on a silicon substrate having a gate formation region; Forming a silicon layer on the oxide film; Recessing a portion of the silicon layer, the oxide film, and a portion of the silicon substrate corresponding to the gate formation region to form a groove for the gate; Growing a silicon epitaxial layer connecting the silicon substrate and the silicon layer along the profile of the gate groove from the substrate resultant in which the gate groove is formed; Forming a gate on a silicon epi layer of the gate groove; Forming a spacer layer on both sidewalls of the gate; And forming a source / drain region having an elevated structure in the silicon layer including the silicon epitaxial layers on both sides of the gate.

Here, the oxide film is formed to a thickness of 50 to 500 kPa.

The gate groove is formed by recessing the silicon substrate by a thickness of 50 to 300 Å.

The silicon epitaxial layer is grown by a thickness of 200 to 1000 GPa.

The gate groove and the silicon epitaxial layer are formed such that a channel portion below the gate is disposed above the oxide film.

The gate groove and the silicon epitaxial layer are formed such that a channel portion under the gate is disposed below the oxide layer.

The source / drain regions having the raised structure are formed to a depth not in contact with the oxide film.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, when manufacturing a MOSFET device applying a silicon on insulator (SOI) transistor, after removing the oxide layer of the channel region, a silicon epitaxial layer is grown to connect the silicon substrate under the oxide layer and the silicon layer above the oxide layer, A source / drain region having an elevated structure is formed in the silicon layers on both sides of the gate.

In this case, by applying a bias power to the silicon layer on the oxide layer to easily control the silicon layer from the outside, it is possible to improve the short channel effect, thereby improving the characteristics of the semiconductor device. have. In addition, the present invention can more effectively improve the short channel effect by forming a source / drain region having an elevated structure in both silicon layers of the gate.

1 is a cross-sectional view illustrating a MOSFET device according to an embodiment of the present invention.

Referring to FIG. 1, a MOSFET device includes a silicon substrate 100, an oxide film 110 formed on the silicon substrate 100, a silicon layer 120 formed on the oxide film 110, and an upper portion of the silicon layer 120. And a source / drain region 160 formed in the silicon layer 120 at both sides of the gate 140.

In the MOSFET device, a thickness of the silicon layer 120, the oxide layer 110, and a portion of the silicon substrate 100 is recessed to provide the gate groove H, and the gay groove H. The silicon epitaxial layer 130 is formed on the silicon layer 120 including the silicon substrate 100 and the silicon layer 120 along the profile of the gate groove H.

The gate 140 is formed on the silicon epitaxial layer 130 of the gate groove H, and has a stacked structure of a gate insulating layer 132, a gate conductive layer 134, and a hard mask layer 136. The spacer layer 150 is formed on both sidewalls of the gate 140. In this case, the gate groove H is preferably formed such that a channel portion under the gate 140 is disposed above the oxide film 110.

In addition, the source / drain region 160 may be formed to have an elevated structure in the silicon layer 120 including the silicon epitaxial layer 130. The source / drain region 160 having the raised structure may be formed. Is preferably formed to a depth not in contact with the oxide film 110.

2A to 2G are cross-sectional views illustrating processes for manufacturing a MOSFET device according to an embodiment of the present invention.

Referring to FIG. 2A, an oxide film 210 is formed on a silicon substrate 200 having a gate formation region. The oxide film 210 is formed to a thickness of about 50 ~ 500Å.

Referring to FIG. 2B, a silicon layer 220 is formed on the oxide layer 210 to form a silicon on insulator (SOI) structure in which an oxide layer 210 is interposed between the silicon substrate 200 and the silicon layer 220. Form. Next, an isolation layer (not shown) defining an active region including a gate formation region is formed in the substrate 200 on which the silicon layer 220 is formed, and then an impurity ion implantation is performed to form a well (not shown). do.

Referring to FIG. 2C, a portion of the silicon layer 220, the oxide film 210, and the portion of the silicon substrate 200 corresponding to the gate formation region is recessed to form the groove H for the gate. In this case, the gate groove H is formed to recess the silicon substrate 200 by a thickness of about 50 to 300 Å so that the channel predetermined region of the gate is disposed above the oxide film 210.

Referring to FIG. 2D, a silicon epitaxial layer connecting the silicon substrate 200 and the silicon layer 220 along the profile of the gate groove H from a result of the substrate 200 on which the gate groove H is formed. Grow 230. In this case, the silicon epitaxial layer 230 is grown to a thickness that can cover the oxide film 210 from the recessed silicon substrate 200, preferably, about 200 to 1000 Å.

Referring to FIG. 2E, the gate insulating film 232 is formed on the silicon epitaxial layer 230 of the gate groove H to have a uniform thickness, for example, about 20 to about 300 GHz. ), The gate conductive film 234 and the hard mask film 236 are sequentially formed. The gate conductive layer 234 is formed of a polysilicon layer and a tungsten silicide layer, and the hard mask layer 236 is formed of a nitride layer.

Thereafter, the hard mask layer 236, the gate conductive layer 234, and the gate insulating layer 232 are etched to form a gate 240 on the gate groove H. Subsequently, a chemical mechanical polishing (CMP) process is performed on the hard mask layer 236 on the gate 240 to planarize the upper portion of the gate 240.

Referring to FIG. 2F, LDD (Light Doped Drain) ion implantation is performed on the resultant of the substrate 200 on which the gate 240 is formed. In this case, the LDD ion implantation is performed in a dose of about 1 × 10 13 to 1 × 10 15 ions / cm 2 using Ph + , or As ions in the case of NMOS, and PMOS (PMOS) ), B + , or BF 2 ions using a dose of about 1 × 10 13 ~ 1 × 10 15 ions / cm 2 It is preferable.

Next, after depositing an insulating film for a spacer on the entire surface of the substrate 200 on which the LDD ion implantation is performed, the spacer insulating film is etched to form a spacer film 250 on both sidewalls of the gate 240. The spacer film 250 is formed of an oxide film or a nitride film, and is formed to a thickness of about 100 to 500 Å.

Referring to FIG. 2G, an ion implantation process is performed on the resultant of the substrate 200 on which the spacer layer 250 is formed to be raised in the silicon layer 220 including the silicon epitaxial layer 230 on both sides of the gate 240. A source / drain region 260 having an (Elevated) structure is formed. The source / drain regions 260 having the raised structure are preferably formed to have a depth not in contact with the oxide film 210.

Thereafter, although not shown, a series of subsequent known processes are sequentially performed to complete a MOSFET device according to an embodiment of the present invention.

Here, the present invention can improve the short channel effect by increasing the effective channel length of the transistor by applying the SOI transistor in the manufacture of the MOSFET device, and the DIBL (Drain-) where interference between source / drain regions occurs. Induced Barrier Lowering can be minimized.

In addition, the present invention can be easily controlled from the outside by applying a bias power (Bias Power) to the silicon layer on the oxide layer, through which, as a hot carrier (Hot Carrier) generated during the operation of the transistor It is possible to prevent the potential and threshold voltage (Vt) of the silicon layer from changing, thereby improving the characteristics of the semiconductor device.

In addition, the present invention can more effectively improve the short channel effect by forming a source / drain region having a raised structure in the substrate surface on both sides of the gate.

Meanwhile, in the above-described embodiment of the present invention, the gate groove may be formed such that the channel portion under the gate is disposed above the oxide layer, thereby improving the characteristics of the semiconductor device. In another embodiment, the characteristics of the semiconductor device may be improved by forming the gate groove so that the channel portion under the gate is disposed under the oxide layer.

3 is a cross-sectional view illustrating a MOSFET device according to another exemplary embodiment of the present invention.

As shown in FIG. 3, the gate groove H and the silicon epitaxial layer 330 include an oxide layer having a channel portion under the gate 340 interposed between the silicon substrate 300 and the silicon layer 320. It is formed to be disposed below the 310.

In FIG. 3, reference numeral 332 of FIG. 3 denotes a gate insulating layer, 334 denotes a gate conductive layer, 336 denotes a hard mask layer, 350 denotes a spacer layer, and 360 denotes a source / drain region.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention can effectively improve the short channel effect by applying a silicon on insulator (SOI) transistor, thereby improving the characteristics of the semiconductor device.

In addition, according to the present invention, the silicon layer may be easily controlled by connecting the silicon substrate under the oxide layer and the silicon layer over the oxide layer when the SOI transistor is applied.

Claims (11)

Silicon substrates; An oxide film formed on the silicon substrate; A silicon layer formed on the oxide film; A gate formed on the silicon layer; And In the MOSFET device comprising a source / drain region formed in the silicon layer on both sides of the gate, A thickness of the silicon layer and the oxide layer and the silicon substrate is recessed to provide a groove for a gate, A silicon epitaxial layer is formed on the silicon layer including the gay groove along the profile of the gate groove. The gate is formed on the silicon epi layer of the gate groove, And the source / drain region is formed to have an elevated structure in the silicon layer including the silicon epitaxial layer. The method of claim 1, And the gate groove is formed such that a channel portion under the gate is disposed above the oxide film. The method of claim 1, And the gate groove is formed such that a channel portion under the gate is disposed under the oxide film. The method of claim 1, And the source / drain region having the raised structure is formed to a depth not in contact with the oxide film. Forming an oxide film on the silicon substrate having the gate formation region; Forming a silicon layer on the oxide film; Recessing a portion of the silicon layer, the oxide film, and a portion of the silicon substrate corresponding to the gate formation region to form a groove for the gate; Growing a silicon epitaxial layer connecting the silicon substrate and the silicon layer along the profile of the gate groove from the substrate resultant in which the gate groove is formed; Forming a gate on a silicon epi layer of the gate groove; Forming a spacer layer on both sidewalls of the gate; And Forming a source / drain region having an elevated structure in the silicon layer including the silicon epitaxial layers on both sides of the gate; Method for producing a MOSFET device comprising a. The method of claim 5, wherein And the oxide film is formed to a thickness of 50 to 500 GPa. The method of claim 5, wherein And the gate groove is formed by recessing the silicon substrate by a thickness of 50 to 300 GPa. The method of claim 5, wherein The silicon epitaxial layer is grown by a thickness of 200 to 1000 kHz. The method of claim 5, wherein And the gate groove and the silicon epitaxial layer are formed such that a channel portion under the gate is disposed above the oxide layer. The method of claim 5, wherein And the gate groove and the silicon epitaxial layer are formed such that a channel portion under the gate is disposed under the oxide film. The method of claim 5, wherein The source / drain region having the raised structure is formed to a depth not in contact with the oxide film.
KR1020070021690A 2007-03-05 2007-03-05 Mosfet device and method of mamufacturing the same KR20080081550A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101043367B1 (en) * 2009-01-05 2011-06-21 주식회사 하이닉스반도체 Semiconductor Device and Method for Manufacturing the same
CN102184926A (en) * 2010-01-14 2011-09-14 硅绝缘体技术有限公司 Memory cell in which the channel passes through a buried dielectric layer
US10361205B2 (en) 2017-04-12 2019-07-23 Samsung Electronics Co., Ltd. Semiconductor devices including structures for reduced leakage current and method of fabricating the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101043367B1 (en) * 2009-01-05 2011-06-21 주식회사 하이닉스반도체 Semiconductor Device and Method for Manufacturing the same
CN102184926A (en) * 2010-01-14 2011-09-14 硅绝缘体技术有限公司 Memory cell in which the channel passes through a buried dielectric layer
US8304833B2 (en) 2010-01-14 2012-11-06 Soitec Memory cell with a channel buried beneath a dielectric layer
KR101222023B1 (en) * 2010-01-14 2013-01-15 소이텍 Memory cell in which the channel passes through a buried dielectric layer
CN102184926B (en) * 2010-01-14 2014-10-08 硅绝缘体技术有限公司 Memory cell in which the channel passes through a buried dielectric layer
US10361205B2 (en) 2017-04-12 2019-07-23 Samsung Electronics Co., Ltd. Semiconductor devices including structures for reduced leakage current and method of fabricating the same
US10770463B2 (en) 2017-04-12 2020-09-08 Samsung Electronics Co., Ltd. Semiconductor devices including structures for reduced leakage current and method of fabricating the same

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