JP4440188B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 220
- 238000004519 manufacturing process Methods 0.000 title claims description 44
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- 239000012535 impurity Substances 0.000 claims description 107
- 238000005468 ion implantation Methods 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 37
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
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- 230000003647 oxidation Effects 0.000 description 17
- 238000007254 oxidation reaction Methods 0.000 description 17
- 239000005380 borophosphosilicate glass Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
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- 230000003213 activating effect Effects 0.000 description 1
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- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
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Description
−半導体装置の構造−
図1(a)は、本発明の第1の実施形態に係るトレンチゲート構造を有する半導体装置の構造を示す斜視図であり、図1(b)は、図1(a)に示す半導体装置における垂直方向に沿った第2導電型不純物濃度プロファイルを示す図である。尚、図1(a)においては、構造を見やすくするために、コンタクト電極10の下側に設けられるバリアメタル層の図示を省略している。
図3(a)〜(f)、図4(a)〜(f)、図5(a)〜(f)及び図6(a)〜(d)は、本発明の第1の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。特に、図3(a)、(c)、(e)、図4(a)、(c)、(e)、図5(a)、(c)、(e)及び図6(a)、(c)は、図1(a)に示す構造を正面側から見た断面構成を示しており、図3(b)、(d)、(f)、図4(b)、(d)、(f)、図5(b)、(d)、(f)及び図6(b)、(d)は、図1(a)に示す構造を右側面側から見た断面構成を示している。
−半導体装置の構造−
本発明の第2の実施形態に係るトレンチゲート構造を有する半導体装置は、第1の実施形態と同様に、図1(a)に示す構造を持つ。
本発明の第2の実施形態に係る半導体装置の製造方法は、基本的には、図3(a)〜(f)、図4(a)〜(f)、図5(a)〜(f)及び図6(a)〜(d)に示す第1の実施形態と同様である。
−半導体装置の構造−
本発明の第3の実施形態に係るトレンチゲート構造を有する半導体装置は、第1の実施形態と同様に、図1(a)に示す構造を持つ。
本発明の第3の実施形態に係る半導体装置の製造方法は、基本的には、図3(a)〜(f)、図4(a)〜(f)、図5(a)〜(f)及び図6(a)〜(d)に示す第1の実施形態と同様である。
2 低濃度N型ドレイン領域
3 P型基板領域
4 ゲート絶縁膜
5 ゲート電極
5A ポリシリコン膜
6 埋め込み絶縁膜
6A BPSG膜
7 高濃度P型基板領域
8 高濃度N型ソース領域
9 シリサイド層
10 コンタクト電極
11 保護絶縁膜
12 犠牲酸化膜
51、52、53、54、55 フォトレジストマスク
T トレンチ
S 半導体基板
Claims (10)
- 半導体基板に、第1導電型の第1の半導体領域を形成する工程(a)と、
前記半導体基板に、前記第1の半導体領域の所定の部位に達するトレンチを形成する工程(b)と、
前記トレンチの壁面に沿ってゲート絶縁膜を形成する工程(c)と、
前記工程(c)よりも後に、前記半導体基板内における前記第1の半導体領域の上に、第2導電型の第2の半導体領域を形成する工程(d)と、
前記トレンチ内に前記ゲート絶縁膜を介して第1導電型のゲート電極を形成する工程(e)と、
前記半導体基板内における前記第2の半導体領域の上に、第1導電型の第3の半導体領域を形成する工程(f)とを備え、
前記工程(e)において、前記ゲート電極は、前記第2の半導体領域と、前記第1の半導体領域における前記第2の半導体領域の下側に位置する部分と、前記第3の半導体領域における前記第2の半導体領域の上側に位置する部分とにそれぞれ跨るように、前記トレンチ内に前記ゲート絶縁膜を介して形成されており、
前記工程(e)は、前記トレンチ内に導体膜を埋め込む工程(e1)と、前記導体膜にエッチング処理を行なって前記ゲート電極を形成する工程(e2)とを含み、
前記工程(d)は前記工程(e1)と前記工程(e2)との間に実施され、
前記第2の半導体領域は、イオン注入により第2導電型不純物を前記導体膜を介して前記半導体基板に導入することによって形成されることを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記工程(e)において、前記ゲート電極は、当該ゲート電極の上面が前記第3の半導体領域の上面と下面との間に位置するように形成されることを特徴とする半導体装置の製造方法。 - 請求項1又は2に記載の半導体装置の製造方法において、
前記工程(e)の後に、前記トレンチ内における前記ゲート電極の上面を覆う絶縁膜を形成する工程(g)をさらに備え、
前記絶縁膜は、当該絶縁膜の上面が前記第3の半導体領域の上面と下面との間に位置するように形成されることを特徴とする半導体装置の製造方法。 - 請求項1〜3のうちのいずれか1項に記載の半導体装置の製造方法において、
前記工程(e)の後に、前記トレンチ内に露出する前記第3の半導体領域の表面にシリサイド層を形成する工程(h)をさらに備えていることを特徴とする半導体装置の製造方
法。 - 請求項1〜4のうちのいずれか1項に記載の半導体装置の製造方法において、
前記工程(d)において、前記第2の半導体領域は、注入エネルギーの異なる複数回のイオン注入により第2導電型不純物を前記半導体基板に導入することによって形成される
ことを特徴とする半導体装置の製造方法。 - 請求項1〜5のうちのいずれか1項に記載の半導体装置の製造方法において、
前記工程(b)と前記工程(c)との間に、前記トレンチの壁面を犠牲酸化して酸化膜を形成した後、当該酸化膜を除去する工程をさらに備えていることを特徴とする半導体装置の製造方法。 - 請求項1〜6のうちのいずれか1項に記載の半導体装置の製造方法において、
前記トレンチの側方における前記第1の半導体領域と前記第3の半導体領域との間に形成されている前記第2の半導体領域の第2導電型不純物の濃度分布において、ピーク位置から上方及び下方にそれぞれ0.25μm離れた位置での濃度がピーク濃度の2分の1未満であることを特徴とする半導体装置の製造方法。 - 請求項1〜7のうちのいずれか1項に記載の半導体装置の製造方法において、
前記第2の半導体領域の第2導電型不純物の濃度分布にピークが2つ存在することを特徴とする半導体装置の製造方法。 - 請求項1〜7のうちのいずれか1項に記載の半導体装置の製造方法において、
前記第2の半導体領域の第2導電型不純物の濃度分布にピークが3つ以上存在することを特徴とする半導体装置の製造方法。 - 請求項1〜9のうちのいずれか1項に記載の半導体装置の製造方法において、
前記第1の半導体領域は、第1導電型不純物の濃度が相対的に高い第4の半導体領域と、前記第4の半導体領域上に設けられ且つ第1導電型不純物の濃度が相対的に低い第5の半導体領域とを有することを特徴とする半導体装置の製造方法。
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JP5198752B2 (ja) * | 2006-09-28 | 2013-05-15 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5089191B2 (ja) | 2007-02-16 | 2012-12-05 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US8264036B2 (en) * | 2008-11-12 | 2012-09-11 | Fuji Electric Co., Ltd. | Power semiconductor device with low on-state voltage and method of manufacturing the same |
JP6006918B2 (ja) | 2011-06-06 | 2016-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体装置の製造方法、及び電子装置 |
JP5798865B2 (ja) * | 2011-09-29 | 2015-10-21 | セイコーインスツル株式会社 | 半導体装置及びその製造方法 |
JP6110900B2 (ja) * | 2015-07-07 | 2017-04-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP7073872B2 (ja) * | 2018-04-13 | 2022-05-24 | 株式会社デンソー | スイッチング素子とその製造方法 |
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