JP2005229066A - 半導体装置及びその製造方法 - Google Patents
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Abstract
【解決手段】半導体装置は、シリコン基板Sに形成されたP型ドレイン領域と、低濃度P型ドレイン領域(EPI)1と、低濃度ドレイン領域1の上方に形成された高濃度P型ソース領域8と、高濃度P型ソース領域8と低濃度P型ドレイン領域(EPI)1との間に形成されたN型基板領域3と、トレンチTと、トレンチT内部に形成されたゲート絶縁膜4及びゲート電極5と、トレンチTを塞ぐ絶縁膜7と、N型基板領域3と高濃度P型ソース領域8との間に形成されたN型ポケット領域6とを備えている。N型ポケット領域6により、低濃度P型ドレイン領域1側に印加される電界強度を強めることなく、低濃度P型ドレイン領域1からの空乏層の拡がりを阻止する障壁が形成される。
【選択図】 図1
Description
−半導体装置の構造−
図1(a),(b)は、第1の実施形態に係るトレンチゲート構造を有する半導体装置の構造を示す斜視図、及びI−I線に示す断面に沿った不純物濃度プロファイルを示す図である。なお、図1(a)においては、構造を見やすくするために、図4(c)に示すシリサイド層10の表示が省略されている。
図3(a)〜(c)は、第1の実施形態の半導体装置の製造工程の前半部分を示す断面図である。図4(a)〜(c)は、第1の実施形態の半導体装置の製造工程の後半部分を示す断面図である。
−半導体装置の構造−
図6(a),(b)は、第2の実施形態に係るトレンチゲート構造を有する半導体装置の構造を示す斜視図、及びVI−VI線に示す断面に沿った不純物濃度プロファイルを示す図である。なお、図5(a)においては、構造を見やすくするために、図5(c)に示すシリサイド層10の表示が省略されている。本実施形態の半導体装置の構造は、N型ポケット領域6を除くと、基本的に第1の実施形態(図1(a)参照)と同じ構成なので、同じ構造を有する部分の説明は省略する。
図5(a)〜(c)は、第2の実施形態の半導体装置の製造工程の後半部分のみを示す断面図である。本実施形態においても、製造工程の前半部分は、第1の実施形態における図3(a)〜(c)に示す通りであるので、図示及び説明を省略する。
なお、この工程は、次に示す図5(c)に示す工程の後でもよい。
2 高濃度P型ドレイン領域
3 N型基板領域
4 ゲート絶縁膜
5 ゲート電極
6 N型ポケット領域
6B N型ポケット領域
7 埋め込み絶縁膜
8 高濃度P型ソース領域
9 高濃度N型基板領域
10 シリサイド領域
11 マスク酸化膜
T トレンチ
S シリコン基板
Claims (11)
- 半導体基板と、
上記半導体基板の裏面領域に形成された第1導電型不純物を含む第1の半導体領域と、
上記半導体基板内における上記第1の半導体領域の上方に形成され第2導電型不純物を含む第2の半導体領域と、
上記半導体基板内における上記第2の半導体領域の上に形成され第1導電型不純物を含む第3の半導体領域と、
上記第2及び第3の半導体領域を通過して上記第1の半導体領域に到達するトレンチと、
上記トレンチの壁面に沿って形成されたゲート絶縁膜と、
上記ゲート絶縁膜の上で上記トレンチ内に形成されたゲート電極と、
上記トレンチの側方で上記第2の半導体領域と第3の半導体領域との間に形成され、上記第2の半導体領域よりも高ピーク濃度の第2導電型不純物を含むポケット領域と
を備えている半導体装置。 - 請求項1記載の半導体装置において、
上記ゲート電極は、上記トレンチの上部を除く部分に形成されており、
上記トレンチの上部を埋める絶縁膜をさらに備えている,半導体装置。 - 請求項1又は2記載の半導体装置において、
上記ポケット領域は、上記トレンチの壁面に近い領域のみに形成されている,半導体装置。 - 請求項1又は2記載の半導体装置において、
上記ポケット領域は、上記第2の半導体領域と第3の半導体領域との間の領域全体に亘って形成されている,半導体装置。 - 上記半導体基板の裏面領域に第1導電型不純物を含む第1の半導体領域を形成する工程(a)と、
上記半導体基板内における上記第1の半導体領域の上方に第2導電型不純物を含む第2の半導体領域を形成する工程(b)と、
上記半導体基板を選択的に堀り込んで、上記第2の半導体領域を貫通して上記第1の半導体領域に到達するトレンチを形成する工程(c)と、
上記トレンチの壁面に沿って、ゲート絶縁膜を形成する工程(d)と、
上記トレンチ内に導体膜を埋め込んで上記ゲート絶縁膜の上にゲート電極を形成する工程(e)と、
上記第2の半導体領域の上部に第1導電型不純物を導入して、第3の半導体領域を形成する工程(f)と、
上記工程(e)の後で上記工程(f)の前又は後に、第2導電型不純物のイオン注入により、上記第2の半導体領域と上記第3の半導体領域の間に、上記第2の半導体領域よりも高ピーク濃度のポケット領域を形成する工程(g)と
を含む半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
上記工程(e)では、上記ゲート電極を上記トレンチの上部を除く部分に形成し、
上記工程(g)は、上記半導体基板のうちトレンチを除く領域を覆う注入マスクを形成した後、半導体基板の主面に垂直な方向から傾いた方向から第2導電型不純物のイオン注入を行なうことにより、上記ポケット領域を上記トレンチの壁面に近い領域のみに形成する,半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
上記工程(g)の後で上記工程(f)の前又は後に、上記トレンチ内の上記ゲート電極の上方に絶縁膜を埋め込む工程をさらに含む,半導体装置の製造方法。 - 請求項6又は7記載の半導体装置の製造方法において、
上記工程(g)では、基板面に垂直な方向に対するイオン注入方向の傾き角は、7°〜45°の範囲にある,半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
上記工程(e)では、2,4又は8ステップのイオン注入を行なう,半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
上記工程(e)では、上記ゲート電極を上記トレンチの上部を除く部分に形成し、
上記工程(f)と上記工程(g)との前又は後、あるいは、上記工程(f)と上記工程(g)との間に、上記トレンチ内の上記ゲート電極の上方に絶縁膜を埋め込む工程をさらに含み、
上記工程(g)は、上記半導体基板全体に第2導電型不純物のイオン注入を行なうことにより、上記ポケット領域を上記第2の半導体領域と第3の半導体領域との間の領域全体に亘って形成する,半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
上記工程(e)の後で上記工程(f)の前又は後に、上記トレンチ内の上記ゲート電極の上方に絶縁膜を埋め込む工程をさらに含む,半導体装置の製造方法。
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JP2004038878A JP4091921B2 (ja) | 2004-02-16 | 2004-02-16 | 半導体装置及びその製造方法 |
US11/030,945 US7626229B2 (en) | 2004-02-16 | 2005-01-10 | Semiconductor device and method for fabricating the same |
CNB2005100040372A CN100461450C (zh) | 2004-02-16 | 2005-01-10 | 半导体装置及其制造方法 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014102916A1 (ja) * | 2012-12-26 | 2014-07-03 | 株式会社日立製作所 | 炭化珪素半導体装置 |
US8836019B2 (en) | 2008-11-21 | 2014-09-16 | Samsung Electronics Co., Ltd. | Recessed channel transistors, and semiconductor devices including a recessed channel transistor |
US9331194B2 (en) | 2012-10-18 | 2016-05-03 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
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2004
- 2004-02-16 JP JP2004038878A patent/JP4091921B2/ja not_active Expired - Lifetime
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2005
- 2005-01-10 US US11/030,945 patent/US7626229B2/en not_active Expired - Fee Related
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US8836019B2 (en) | 2008-11-21 | 2014-09-16 | Samsung Electronics Co., Ltd. | Recessed channel transistors, and semiconductor devices including a recessed channel transistor |
US9331194B2 (en) | 2012-10-18 | 2016-05-03 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
US9608057B2 (en) | 2012-10-18 | 2017-03-28 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
WO2014102916A1 (ja) * | 2012-12-26 | 2014-07-03 | 株式会社日立製作所 | 炭化珪素半導体装置 |
KR20210117118A (ko) * | 2020-03-17 | 2021-09-28 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 디바이스 및 그 제조 방법 |
US11244830B2 (en) | 2020-03-17 | 2022-02-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
KR102409130B1 (ko) * | 2020-03-17 | 2022-06-16 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 디바이스 및 그 제조 방법 |
US11742207B2 (en) | 2020-03-17 | 2023-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
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JP4091921B2 (ja) | 2008-05-28 |
CN100461450C (zh) | 2009-02-11 |
US20050179082A1 (en) | 2005-08-18 |
CN1658400A (zh) | 2005-08-24 |
US7626229B2 (en) | 2009-12-01 |
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