TWI724532B - 製造半導體裝置的方法及全繞閘極場效電晶體 - Google Patents

製造半導體裝置的方法及全繞閘極場效電晶體 Download PDF

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TWI724532B
TWI724532B TW108132109A TW108132109A TWI724532B TW I724532 B TWI724532 B TW I724532B TW 108132109 A TW108132109 A TW 108132109A TW 108132109 A TW108132109 A TW 108132109A TW I724532 B TWI724532 B TW I724532B
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layer
semiconductor
single crystal
crystal oxide
oxide layer
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TW108132109A
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TW202013525A (zh
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喬治凡利亞尼提斯
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台灣積體電路製造股份有限公司
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Abstract

一種製造半導體裝置的方法，形成單晶氧化層於基材上。在形成單晶氧化層後，形成隔離結構，以定義出主動區域。形成閘極結構於主動區域內的單晶氧化層上。形成源極/汲極結構。

Description

製造半導體裝置的方法及全繞閘極場效 電晶體
本揭露是關於一種半導體裝置及其製造方法，且特別是一種具單晶氧化層之半導體裝置及其製造方法。
做為場效電晶體或鐵電裝置的介電層是高可靠半導體裝置之關鍵元件之一。在未來的半導體裝置中，可能需要使用結晶氧化物為閘極介電層。
因此，本揭露之一實施例之一態樣是提供一種製造半導體裝置的方法，形成單晶氧化層於基材上。在形成單晶氧化層後，形成隔離結構，以定義出主動區域。形成閘極結構於主動區域內的單晶氧化層上。形成源極/汲極結構。
本揭露之一實施例之另一態樣是提供一種製造半導體裝置的方法，形成第一半導體層於半導體基材上。形成由單晶氧化層和位於單晶氧化層上之第二半導體層所組 成之一或多對材料層，並接續形成頂部單晶氧化層。藉由蝕刻頂部單晶氧化層、一或多對材料層、第一半導體層及半導體基材的一部分，來形成鰭結構。形成隔離絕緣層。形成犧牲閘極結構於鰭結構上。於源極/汲極區域內，去除在一或多對材料層中之頂部單晶氧化層及單晶氧化層。形成源極/汲極磊晶層於源極/汲極區域內。形成層間介電層。去除犧牲閘極結構，藉以形成閘極間隙。去除在一或多對材料層中的第一半導體層於閘極間隙內。形成閘極介電層在閘極間隙中。形成閘極電極結構在閘極間隙中。
本揭露之一實施例的又一態樣是提供一種全繞閘極場效電晶體(gate-all-around field effect transistor，GAAFET)，包含第一半導體線及第二半導體線，設置於底部鰭結構上，且第一半導體線和第二半導體線之每一者包含通道區域及源極/汲極區域。第一閘極介電層，包覆第一半導體線的通道區域。第二閘極介電層，包覆第二半導體線的通道區域。閘極電極，設置於第一閘極介電層及第二閘極介電層上，其中第一閘極介電層和第二閘極介電層之每一者包含單晶氧化層，單晶氧化層設置於通道區域的上表面及底表層上。閘極電極的一部分係設置在第一半導體線的通道區域與第二半導體線的通道區域之間。
10/100:基材
20:單晶氧化層
22:下層
24:上層
26:間隙
28:溝槽
30:淺溝槽隔離區域
31/135:絕緣材料層
40/140:閘極結構
42/165:閘極介電層
44/144:閘極電極層
46/146:硬遮罩
48/148:側壁間隙壁
50:源極/汲極磊晶層
60/160:層間介電層
65:接觸蝕刻停止層
70:金屬閘極電極
72/172:功函數調節層
74/174:主體閘極電極層
102:底部鰭結構
105:第一半導體層
107:第三半導體層
110:單晶氧化層
120:第二半導體層
130:鰭結構
144:犧牲電極層
150:源極/汲極磊晶層
170:金屬閘極結構
122/124:遮罩層
A-A’/B-B’:線
T:厚度
W:寬度
當結合隨附圖式閱讀時，自以下詳細描述將最佳地理解本揭露之一實施例的態樣。應注意，根據工業中之 標準實務，圖式中之各特徵並非按比例繪製。實際上，可出於論述清晰之目的任意增減所說明的特徵之尺寸。
〔圖1〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖2〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖3〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖4〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖5〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖6〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖7〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖8〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖9〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖10〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖11〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖12〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖13〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖14〕係繪示根據本揭露之一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖15〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖16〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖17A〕與〔圖17B〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖18〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖19A〕至〔圖19C〕係繪示根據本揭露之另一實施例之製造FET裝置的各個階段之一者的示意圖。
〔圖20A〕至〔圖20C〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖21A〕至〔圖21C〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖22A〕與〔圖22B〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖23A〕與〔圖23B〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖24A〕至〔圖24C〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖25A〕與〔圖25B〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖26A〕與〔圖26B〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖27A〕與〔圖27B〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖28A〕至〔圖28D〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖29A〕與〔圖29B〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖30A〕至〔圖30C〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖31A〕至〔圖31C〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖32A〕至〔圖32D〕係繪示根據本揭露之另一實施例之製造半導體FET裝置的各個階段之一者的示意圖。
〔圖33A〕至〔圖33C〕係繪示根據本揭露之一實施例之半導體FET裝置的各種閘極結構的示意圖。
以下揭露提供許多不同實施例或例示，以實施發明的不同特徵。以下敘述之成份和排列方式的特定例示是 為了簡化本揭露之一實施例。這些當然僅是做為例示，其目的不在構成限制。舉例而言，第一特徵形成在第二特徵之上或上方的描述包含第一特徵和第二特徵有直接附接的實施例，也包含有其他特徵形成在第一特徵和第二特徵之間，以致第一特徵和第二特徵無直接附接的實施例。為簡化及清楚，各種特徵可以不同的尺寸任意繪示。
此外，空間相對性用語，例如「下方(beneath)」、「在...之下(below)」、「低於(lower)」、「在...之上(above)」、「高於(upper)」等，是為了易於描述圖式中所繪示的元件或特徵和其他元件或特徵的關係。空間相對性用語除了圖式中所描繪的方向外，還包含元件在使用或操作時的不同方向。裝置可以其他方式定向(旋轉90度或在其他方向)，而本文所用的空間相對性描述也可以如此解讀。此外，術語「由……製成」可意謂「包含」或者「由……組成」任一者。在本揭露之一實施例中，除有特別說明，用語「A、B及C之一者」可意指「A、B及/或C」(A、B、C、A及B、A及C、B及C，或A、B及C)，且並非意指A的其中一元件、B的其中一元件及C的其中一元件。
針對根據本揭露之一實施例之場效電晶體(field-effect transistor，FET)或鐵電裝置(ferroelectric device)，結晶介電層是單晶，並對於通道具有特定結晶相，對稱且陡峭的介面。當需要結晶氧化物做為閘極介電層時，藉由多種方法來沈積氧化層在通道上，例如在非晶質或多晶相中的化學沉積(Chemical Vapor Deposition，CVD)或 原子層沉積(tomic Layer Deposition，ALD)。當閘極替換技術使用於FET裝置時，此沈積是在後段(或依製成而定於中段)中進行，此沈積在形成層間介電(interlayer dielectric，ILD)層後，此沈積後接著進行化學機械研磨(chemical mechanical polishing，CMP)及虛設閘極去除。在此沈積後，使用高溫退火以將氧化層結晶至標的晶相。在閘極替換技術中，閘極介電層的氧化層係形成於夾窄的空間上。，此夾窄的空間是由去除虛設電極和虛設閘極介電層後之側壁間隙壁所形成。
通常，結晶溫度(需要用來轉換非晶氧化層為單晶氧化層)是非常高的，當考量到此熱處理是在後段(或於中段)製程中進行，其不容許結晶溫度高於例如400℃。此特性限制了可在較低溫度結晶之氧化物材料的選擇。在一些情況下，結晶的退火製程並不一定會實現氧化物的完全結晶或實現所欲的結晶相(完全結晶、斜方晶、單斜晶、立方體晶或正方晶)。此外，透過退火，氧化物的結晶可能造成其部分總厚度(例如：接近通道的區域)為過渡區域的介電質，此過渡區域具有非理想結晶和性質。再者，當氧化膜形成在非平面且不平整的表面(例如：去除虛設(犧牲)閘極後的閘極空間)上和/或在非晶層上(如側壁間隙壁)，氧化層可能不會被形成為單晶。
在本揭露之一實施例中，單晶氧化層是在半導體製造操作的早期階段中形成。更特定地說，結晶氧化層是形成於大且平坦的表面上，在此表面上，未曾進行過蝕刻操 作或圖案化操作。在一些實施例中，單晶氧化層係在形成做為獨立隔離層的淺溝槽隔離(shallow trench isolation，STI)或鰭結構前，形成於基材的裝置區域上。在一些實施例中，在對準標記或其他非電路元件形成於基材的切割道中後，形成單晶氧化層。
圖1至圖4係繪示根據本揭露之一實施例之製造FET裝置的各個階段之示意圖。應理解的是，額外的操作可以於圖1至圖4中所示的製程之前、之中或之後提供，且在方法的額外實施例中，一些下述的操作可以被取代或省略。操作及/或製程的順序為可交替的。再者，在本揭露之一實施例中，源極與汲極是可交替使用的，且源極/汲極係指源極與汲極其中至少一者。
如圖1所示，提供基材10。在一些實施例，基材10包含位於其至少一表面部分上的單晶半導體層，如但不受限於：矽(Si)、鍺(Ge)、矽化鍺(SiGe)、砷化鎵(GaAs)、銻化銦(InSb)、磷化鎵(GaP)、銻化鎵(GaSb)、砷化銦鋁(InAlAs)、砷化銦鎵(InGaAs)、銻磷化鎵(GaSbP)、銻化砷鎵(GaAsSb)及磷化銦(InP)的單晶半導體材料。在某些實施例中，基材10是由結晶的Si、SiGe或Ge所製成。在一些實施例中，基材10可包含其表面區域、一或多層緩衝層(圖未繪示)。緩衝層可用以從基材的晶格常數至源極/汲極區域的晶格常數逐漸改變晶格常數。緩衝層可由磊晶成長單晶半導體材料所形成，如但不受限於：Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、 InGaAs、GaSbP、GaAsSb、氮化鎵(GaN)、GaP及InP的單晶半導體材料。在一特定實施例中，基材10包含磊晶成長於矽基材10上的SiGe緩衝層。SiGe緩衝層的鍺濃度可由最底緩衝層之30原子%鍺增加至最頂緩衝層之70原子%鍺。
其上形成有半導體裝置之基材的主要表面之晶向為(100)、(110)或(111)，其視其上所形成之結晶氧化物的種類而定。
如圖2所示，於基材10上形成單晶氧化層20。如前所述，單晶氧化層20是形成於大且平坦的表面上。特別地，在基材的至少一裝置區域(其中形成有半導體電路)上，未進行會產生不平整表面型態的蝕刻或圖案化製程，而單晶氧化層20形成在此平坦的裝置區域上。在一些實施例中，單晶氧化層20係直接形成於基材10上。
在一些實施例中，單晶氧化層是由選自於由二氧化鉿(HfO2)、La2Hf2O7、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3)及二氧化鋯鉿(HfZrO2)之組成群組所製成之一者所製成。在某些實施例中，La2Hf2O7或Y2O3係形成於(100)矽基材上。在其他實施例中，SrTiO3係形成於一(100)鍺基材上。只要氧化物具有實質類似於基材的結晶常數(晶格匹配)，可使用鑭系與錒系氧化物或其三元組合物。
在一些實施例中，單晶氧化層20的厚度是在約0.5nm至約10nm的範圍中，且在其他實施例中，厚度是在約1nm至約5nm的範圍中。可藉由CVD、ALD、分子束磊晶(molecular beam epitaxy，MBE)或其他適合的磊 晶膜形成方法來形成單晶氧化層20。在一些實施例中，成長溫度(例如：基材溫度)是在約650℃至約1000℃的範圍中。在一些實施例中，於形成結晶氧化物(即單晶氧化層20)後，在約650℃至約1000℃範圍的溫度進行退火操作以改善結晶度。
在其他實施例中，基材10上形成非晶質或多晶氧化層，接著在約650℃至約1000℃範圍的溫度進行退火操作，以轉換非晶質或多晶氧化層為單晶氧化層20。在一些實施例中，溫度係在約300℃至約650℃的範圍中。
然後，如圖3所示，於單晶氧化層20上形成包含下層22與上層24的硬遮罩層。在一些實施例中，下層22為氧化矽，上層24為氮化矽。硬遮罩層可藉由CVD形成。
接著，如圖4所示，藉由一或多個微影與蝕刻製程圖案化硬遮罩層，以形成間隙26。更進一步，如圖5所示，使用圖案化的硬遮罩層來蝕刻單晶氧化層20。在一些實施例中，硬遮罩層的蝕刻及單晶氧化層20的蝕刻是持續進行。
然後，如圖6所示，基材10是被溝槽蝕刻，以形成溝槽28。接著，如圖7所示，形成包含之一或多層的絕緣材料層31於基材上。，絕緣層的絕緣材料可包含藉由低壓化學氣相沈積(low-pressure chemical vapor deposition，LPCVD)、電漿CVD或流動式CVD所形成的氧化矽、氮化矽、氮氧化矽(SiON)、SiOCN、SiCN、摻氟矽酸鹽玻璃(fluorine-doped silicate glass，FSG)或低介電常數介電材料。如圖8所示，在絕緣層的形成後，可進 行退火操作。然後，進行平坦化操作，例如化學機械研磨(chemical mechanical polishing，CMP)方法及/或回蝕方法，如此單晶氧化層20的上表面由絕緣材料層暴露，且形成淺溝槽隔離(STI)區域30。在一些實施例中，平面戶操作停止於較低硬遮罩層(即前述的下層22)或較上硬遮罩層(即前述的上層24)，接著藉由適當的濕式及/或乾式蝕刻操作，去除剩下的硬遮罩層。
接下來，如圖9所示，形成犧牲(虛設)閘極結構40。犧牲閘極結構40包含犧牲閘極介電層42、犧牲閘極電極層44及殘餘的硬遮罩層46。在一些實施例中，犧牲閘極介電層42包含一或多層的絕緣材料，例如氧化矽基材料。在一實施例中，使用藉由CVD形成的氧化矽。在一些實施例中，犧牲閘極介電層42的厚度為在約1nm至約5nm之範圍。於單晶氧化層20及STI(即前述區域30)上，藉由第一毯覆性沈積犧牲閘極介電層42，形成犧牲閘極結構40。犧牲閘極電極層44接著毯覆性沈積於犧牲閘極介電層，且於犧牲閘極電極層44上形成硬遮罩層46。犧牲閘極電極層44包含如多晶矽或非晶矽的矽。在一些實施例中，犧牲閘極電極層44的厚度為在約100nm至約200nm之範圍。在一些實施例中，犧牲閘極電極層44是做為平坦化操作的標的。犧牲閘極介電層及犧牲閘極電極層是使用CVD沈積，包含LPCVD與電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)、物理氣相沈積(physical vapor deposition，PVD)、ALD或其他適合的 製程。接續，於犧牲閘極電極層上硬遮罩層46。硬遮罩層46包含一或多層，例如墊SiN層及氧化矽遮罩層。然後，在遮罩層上進行圖案化操作，且圖案化犧牲閘極電極層。再者，如圖9所示，在面對犧牲閘極電極層44及硬遮罩層46之相對的兩側，形成側壁間隙壁48。
接著，如圖10所示，藉由適合的蝕刻操作，去除未被犧牲閘極結構40覆蓋的單晶氧化層20。接下來，如圖11所示，於圖11中所示之源極/汲極區域上，形成半導體材料的一或多層，如源極/汲極磊晶層50。於n通道FET，源極/汲極磊晶層50包含Si、SiP、SiC及SiCP的一或多層。於p通道FET，源極/汲極磊晶層50包含Si、SiGe及Ge。於p通道FET，源極/汲極區域中亦可包含硼(B)。使用CVD、ALD或MBE磊晶成長方法，來形成源極/汲極磊晶層50。
然後，如圖12所示，於源極/汲極磊晶層50及犧牲閘極結構40上，形成層間介電(Inter-Layer Dielectric，ILD)層60。ILD層60包含含有矽、氧、碳及/或氫的化合物，例如氧化矽、SiCOH及SiOC。有機材料，例如聚合物，可被使用為ILD層60。如圖13所示，於形成ILD層60後，進行平坦化操作，例如CMP，如此暴露犧牲閘極電極層44的頂部分。在一些實施例中，如圖13所示，於形成ILD層60前，形成接觸蝕刻停止層65，例如氮化矽層或氧化矽層。
然後，去除犧牲閘極電極層44及犧牲閘極介電層42，藉以形成閘極間隙。犧牲閘極結構可使用電漿乾蝕 刻及/或濕式蝕刻去除。當犧牲閘極電極層44是多晶矽且ILD層60是氧化矽時，可使用如如四甲基氫氧化銨(Tetramethylammonium hydroxide，TMAH)溶液的濕式蝕刻劑，以選擇性地去除犧牲閘極電極層44。使用電漿乾式蝕刻及/或濕式蝕刻，接著去除犧牲閘極介電層42。
如圖14所示，在去除犧牲閘極結構後，於單晶氧化層20上形成金屬閘極電極70，在閘極間隙內做為閘極電極層。金屬閘極電極層(即金屬閘極電極70)包含功函數調節材料(即功函數調節層72)及主體閘極電極層74的一或多層。
功函數調節層72是由如如氮化鈦(TiN)、氮化鉭(TaN)、TaAlC、碳化鈦(TiC)、碳化鉭(TaC)、鈷(Co)、鋁(Al)、鋁鈦(TiAl)、鉿鈦(HfTi)、矽化鈦(TiSi)、TaSi或TiAlC的單一層之導電材料製成，或者是由前述材料之兩個或多個的多層之導電材料製成。於n通道FET，使用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi的一個或多個做為功函數調節層。於p通道FET，使用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co的一個或多個做為功函數調節層。藉由ALD、PVD、CVD、電子束蒸發或其他適合的製程，可形成功函數調節層72。再者，功函數調節層72可個別地形成n通道FET及p通道FET，其中，n通道FET及p通道FET可使用不同的金屬層。
主體閘極電極層74包含導電材料的一或多層，例如鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、 矽化鈷、TiN、氮化鎢(WN)、TiAl、氮化鋁鈦(TiAlN)、TaCN、TaC、鉭矽氮(TaSiN)、金屬合金、其他適合的材料及/或前述之組合。藉由CVD、ALD、電鍍或其他適合的方法，可形成主體閘極電極層74。金屬閘極電極層亦沈積於ILD層60的上表面上。接著，使用如CMP來平坦化形成於ILD層60上的金屬閘極電極層，直到暴露ILD層60的頂表面。在一些實施例中，於平坦化操作後，凹陷金屬閘極電極層(即金屬閘極電極70)，且於凹陷的閘極電極層上形成覆蓋絕緣層(圖未繪示)。覆蓋絕緣層包含氮化矽基材料(例如：SiN)的一或多層。藉由沈積絕緣材料接續平坦化操作，可形成覆蓋絕緣層。
應理解的是，FET經過更進一步的互補式金屬氧化半導體(complementary metal-oxide-semiconductor，CMOS)製程，以形成如接觸/介層窗、內連接金屬層、介電層及/或鈍化層等的各種形態。
如圖14所示，先形成做為閘極介電層的單晶氧化層於平面的基材上，然後進行形成金屬閘極電極的閘極替換操作。據此，閘極介電層不被形成於閘極間隙，此閘極間隙藉由移除犧牲閘極基材所形成的。在這種配置中，單晶氧化層20沈積於側壁間隙壁48的底部與基材10之間。再者，無單晶氧化層位於側壁間隙壁48與金屬閘極電極70之間，因此功函數調節層72直接接觸側壁間隙壁48。如此一來，由於無絕緣層位於側壁間隙壁48與金屬閘極電極70之間， 故有可能增加在金屬閘極電極70下方之有效的閘極長度。
如圖15至圖28D係繪示根據本揭露之一實施例之製造半導體FET裝置的各種階段之示意圖。應理解的是，額外的操作可以於圖15至圖28D中所示的製程之前、之中或之後提供，且在方法的附加實施例中，一些下述的操作可以被取代或省略，且在方法的額外實施例中，一些下述的操作可以被取代或省略。操作及/或製程的順序可為可替換的。參照圖1至圖14說明的前述實施例，可使用於圖15至圖28D相同或相似的材料、配置、尺寸及/或製程，且其細節的說明可被省略。
如圖15所示，提供基材100。在一些實施例中，基材100包含在其至少一表面部分的結晶半導體層。基材100可包含如(但不限於)Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP的單晶半導體材料。在某些實施例，基材100是由結晶Si、SiGe或Ge所製成。
如圖16所示，做為犧牲層的第一半導體層105於基材100上形成。在一些實施例中，第一半導體層105可做為緩衝半導體層的功用。由磊晶成長如(但不限於)Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP及InP的單晶半導體材料，可形成第一半導體層。在一些實施例中，基材100是單晶矽，且第一半導體層105是磊晶成長於基材100上的單晶矽鍺(SiGe)。SiGe層的鍺濃度可由最底緩衝層之30原 子%鍺，增加至最頂緩衝層之0原子%鍺。在一些實施例中，第一半導體層是由SixGe1-x所製成，且基材是由SizGe1-z所製成，其中x<z
Figure 108132109-A0305-02-0018-1
1。在特定實施例中，0.2<x<0.6且0.7<z
Figure 108132109-A0305-02-0018-2
1。在一些實施例中，第一半導體層105的厚度為在約5nm至約30nm之範圍。使用CVD、ALD或MBE的磊晶成長方法，來形成第一半導體層105。
接著，如圖17A及圖17B所示，在第一半導體層105上形成由單晶氧化層110與在單晶氧化層110上的第二半導體層120所組成之一或多對材料層，然後形成頂部單晶氧化層110。單晶氧化層110的形成是相同或相似於如前述之單晶氧化層20的形成。使用CVD、ALD或MBE之磊晶成長方法，來形成第二半導體層120。如圖17A及圖17B所示，形成兩對單晶氧化層110與第二半導體層120。然而，對數並不限於此，其可為一或多於兩對。在一些實施例中，對數可高達20對。
在對中的單晶氧化層110及頂部單晶氧化層之每一者的厚度為在約0.5nm至約10nm的範圍，且在其他實施例，其厚度在約1nm至約5nm的範圍。在一些實施例中，頂部單晶氧化層110的厚度是大於或小於在每對材料層中的頂部單晶氧化層110之厚度。在一些實施例中，此些對材料層中之單晶氧化層110的厚度是不同的。
在一些實施例中，第一半導體層105是由SixGe1-x所製成，而第二半導體層120是由SiyGe1-y所製成，其中x<y
Figure 108132109-A0305-02-0018-3
1。在特定實施例中，0.2<x<0.6且0.7<y
Figure 108132109-A0305-02-0018-4
1。 在一些實施例中，第二半導體層120是如基材100之相同的材料。第二半導體層120的厚度為在約5nm至約40nm的範圍，且在其他實施例中，其厚度為在約10nm至約30nm的範圍。
接著，如圖18所示，使用一個或多個微影與蝕刻操作，來圖案化頂結晶氧化層(即頂部單晶氧化層)、結晶氧化物(即單晶氧化層110)層與第二半導體層120所組成之一或多對材料層、第一半導體層105及部分之半導體基材100為一或多個鰭結構130。
在一些實施例中，於頂部單晶氧化層110上形成第一遮罩層122及第二遮罩層124。第一遮罩層122是墊氧化層，其係由氧化矽所製成，並可藉由熱氧化來形成。第二遮罩層124是由SiN所製成，其係藉由CVD(包含LPCVD、PECVD、PVD、ALD或其他適合的製程)所形成。使用圖案化操作(包含光學微影及蝕刻)，來圖案化遮罩層至遮罩圖案。
然後，使用圖案化遮罩層122與124，來圖案化頂結晶氧化層(即頂部單晶氧化層)的堆疊層、結晶氧化物(即單晶氧化層110)層與第二半導體層120所組成之一或多對材料層、第一半導體層105及部分之半導體基材100，藉以形成以X方向延伸的鰭結構130。八個鰭結構130是以X方向排列。然而，鰭結構的數量並不以八個為限，且可為1個至7個或多於八個。在一些實施例中，於鰭結構130的兩側形成一個或多個虛設鰭結構，以在圖案化的操作中提升圖 案保真度。如圖18所示，鰭結構130具有由頂結晶氧化層(即頂部單晶氧化層)構成的上層部分、結晶氧化物(即單晶氧化層110)層與第二半導體層120所組之一或多對以及第一半導體層105，且鰭結構130具有由部分半導體基材100所構成之底部鰭結構。在一些實施例中，沿著Y方向之鰭結構130上部的寬度為在約5nm至約40nm，在其他實施例中，其寬度為在約10nm至約25nm。
藉由任何適合的方法，可圖案化鰭結構130。舉例來說，使用一個或多個微影製程〔包含雙圖案(double-patterning)或多重圖案(multi-patterning)〕，可圖案化結構。一般而言，相較於使用單一且直接的光微影製程，結合微影及自對準(self-aligned)製程之雙圖案或多重圖案允許所製得之圖案可例如具有較小之間距。舉例來說，在一實施例中，在基材上形成犧牲層，且使用光微影製程，犧牲層係被圖案化。使用自對準製程，沿著圖案化的犧牲層的邊形成間隙壁。然後，移除犧牲層，且餘留的間隙壁可接著用於圖案化鰭結構130。
在形成鰭結構130後，於基材上形成包含絕緣材料的一或多層的絕緣材料層135，以使鰭結構130可完全地嵌入絕緣層中。絕緣層的絕緣材料可包含藉由LPCVD、電漿CVD或流動式CVD形成的氧化矽、氮化矽、SiON、SiOCN、SiCN、FSG或低介電常數介電材料。在絕緣層的形成後，可進行退火操作。然後，進行平坦化操作，例如CMP方法及/或回蝕方法。再者，如圖19A至圖19C所示， 凹陷絕緣材料層135，以使第一半導體層105由絕緣材層至少部分地被暴露出，藉以形成隔離絕緣層(即絕緣材料層135)(例如：STI)。圖19A係透視示意圖，圖19B係繪示圖19A之沿著線A-A’的剖視示意圖，而圖19C係繪示圖19A之沿著線B-B’的剖視示意圖。
如圖20A至圖20B所示，在形成隔離絕緣層(即絕緣材料層135)後，形成犧牲(虛設)閘極結構140。圖20A係透視示意圖，圖20B係繪示圖20A之沿著線A-A’的剖視示意圖，而圖20C係繪示圖20A之沿著線B-B’的剖視示意圖。在鰭結構的上部上形成犧牲閘極結構140，此鰭結構包含頂部單晶氧化層110、單晶氧化層110與第二半導體層120的多對層及第一半導體層105的部分。犧牲閘極結構140包含犧牲閘極介電層142及犧牲閘極電極層144。在一些實施例中，於犧牲閘極電極層144上形成殘餘的硬遮罩層146。犧牲閘極介電層142包含絕緣材料的一或多層，例如氧化矽基材料。在一實施例中，使用藉由CVD形成的氧化矽。在一些實施例中，犧牲閘極介電層142的厚度為在約1nm至約5nm之範圍。
於鰭結構上，藉由第一毯覆性沈積犧牲閘極介電層，形成犧牲閘極結構140。於鰭結構上，犧牲閘極電極層接著毯覆性沈積於犧牲閘極介電層上，如此，鰭結構完全嵌在犧牲閘極電極層中。犧牲閘極電極層包含如多晶矽或非晶矽的矽。在一些實施例中，犧牲閘極電極層的厚度為在約100nm至約200之範圍。在一些實施例中，犧性閘極電極 層為平坦化操作的對象。使用的CVD(包含LPCVD與PECVD)、PVD、ALD或其他適合之製程，沈積犧牲閘極介電層及犧性閘極電極層。接續地，於犧牲閘極電極層上，形成硬遮罩層。在一些實施例中，遮罩層包含墊SiN層及氧化矽遮罩層。
然後，如圖20A至圖20C所示，在遮罩層上進行圖案化操作，且圖案化犧牲閘極電極層為犧牲閘極結構140。犧牲閘極結構140包含犧牲閘極介電層142、犧牲閘極電極層144(例如多晶矽)及硬遮罩146。如圖20A至圖20C所示，藉由圖案化犧牲閘極結構，堆疊的鰭結構部分地暴露於犧牲閘極結構140之相對側，藉以定義源極/汲極(S/D)區域。在圖20A至圖20C中，形成一個犧牲閘極結構，然而犧牲閘極結構的數量不限於一個。在一些實施例中，兩個或多個犧牲閘極結構以X方向排列。在特定實施例中，於犧牲閘極結構的兩側形成一個或多個虛設犧牲閘極結構，以提升圖案保真度。
再者，於犧牲閘極結構140上形成側壁間隙壁148的覆蓋層。覆蓋層係以共型的方式被沈積，以使形成在各種表面(例如分別於側壁、水平的表面及犧牲閘極結構140的頂部)上的覆蓋層具有實質相同的厚度。在一些實施例中，覆蓋層具有為在約5nm至約20nm範圍的厚度。覆蓋層包含SiN、SiON及SiCN或任何其他適合的介電材料之一種或多種。藉由ALD、CVD或任何其他適合的方法，可形成覆蓋層。接著，如圖21A至圖21C所示，藉由異向性蝕 刻，去除覆蓋層的底部，藉以形成側壁間隙壁148。圖21A係透視示意圖，圖21B係繪示圖21A之沿著線A-A’的剖視示意圖，且圖21C係繪示圖21A之沿著線B-B’的剖視示意圖。在一些實施例中，硬遮罩層146的上部係被暴露的。在一些實施例中，如圖21B所示，其中一個鰭結構係設置於側壁間隙壁148之下。在其他實施例中，無鰭結構係設置於側壁間隙壁148之下。
接續地，如圖22A及22B所示，使用一個或多個蝕刻操作，來去除頂部單晶氧化層110及在此些對材料層中之單晶氧化層110。圖22A係透視示意圖，而圖22B係繪示圖22A之沿著線A-A’的剖視示意圖。可使用濕式蝕刻及/或乾式蝕刻來去除對第一半導體層105、第二半導體層120及側壁間隙壁148具選擇性的結晶氧化物。在一些實施例中，在側壁間隙壁148下方之部分結晶氧化層(即單晶氧化層110)的稍微被蝕刻。
然後，如圖23A及23B所示，形成源極/汲極磊晶層150。圖23A係透視示意圖，且圖23B係繪示圖23A之沿著線A-A’的剖視示意圖。如圖23B所示，源極/汲極磊晶層150包繞第二半導體層120且覆蓋暴露的第一半導體層105之上部。做為n通道FET，源極/汲極磊晶層150包含Si、SiP、SiC及SiCP的一或多層，或者做為p通道FET，源極/汲極磊晶層150包含Si、SiGe及Ge的一或多層。做為p通道FET，源極/汲極亦可包含硼(B)。使用CVD、ALD或MBE的磊晶成長方法，來形成源極/汲極磊晶層150。如圖23B 所示，在一些實施例中，分別形成源極/汲極磊晶層150於個別的源極/汲極區域上。在其他實施例中，鄰近的源極/汲極磊晶層150係合併的。
接下來，於源極/汲極磊晶層150及犧牲閘極結構140上，形成ILD層160。ILD層160的材料包含Si、氧、碳及/或氫，材料例如氧化矽、SiCOH及SiOC。有機材料，例如聚合物，可被使用於ILD層160。如圖24A至圖24C所示，在形成ILD層160後，進行平坦化操作(例如CMP)，以使犧牲閘極電極層144的頂部被暴露出。圖24A為透視示意圖，圖24B係繪示圖24A之沿著線A-A’的剖視示意圖，圖24C係繪示圖24A之沿著線B-B’的剖視示意圖。
然後，如圖25A及圖25B所示，去除包含犧牲電極層(即犧牲閘極電極層144)與犧牲閘極介電層142的犧牲閘極結構140，藉以形成閘極間隙149。圖25A係透視示意圖，且圖25B係繪示圖25A之沿著線A-A’的剖視示意圖。在犧牲閘極結構140的去除期間，ILD層160保護源極/汲極磊晶層150。使用電漿乾式蝕刻及/或濕式蝕刻可去除犧牲閘極結構。當犧牲閘極電極層144是多晶矽，且ILD層160是氧化矽，可使用如TMAH溶液的濕式蝕刻劑以選擇性地去除犧牲閘極電極層144。使用電漿乾式蝕刻及/或濕式蝕刻，接著去除犧牲閘極介電層142。在一些實施例中，由於在犧牲閘極的去除期間之側向蝕刻，側壁間隙壁148的水平部分可能出現。
如圖26A及圖26B所示，在去除犧牲閘極結構 後，去除第一半導體層105。圖26A係透視示意圖，且圖26B係繪示圖26A之沿著線A-A’的閘極間隙149內之剖視示意圖。由於第一半導體層105是由與於基材100(底部鰭結構102)及第二半導體層120不同材料所製成，藉由適合的化學溶液，第一半導體層105可選擇性地被去除。餘留的第二半導體層120為FET的通道區域。
如圖27A與圖27B所示，在去除第一半導體層105後，形成閘極介電層165。圖27A為透視示意圖，而圖27B係繪示圖27A之沿著線A-A’的閘極間隙149內之剖視示意圖。在一些實施例中，閘極介電層165是由與單晶氧化層110相同的材料所製成。在其他實施例中，閘極介電層165是由與單晶氧化層110不同的材料所製成。在特定實施例中，閘極介電層165包含一或多層的介電材料，介電材料例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合的高介電常數介電材料及/或前述之結合。
藉由CVD、ALD或任何適合的方法可形成閘極介電層165。在一實施例中，為了確保閘極介電層的形態與每個通道區域周圍具有一致的厚度，使用如ALD的高度共形沉積製程，形成閘極介電層165。在一實施例中，閘極介電層165的厚度係等同於或小於單晶氧化層110，且閘極介電層165的厚度為在約0.5nm至約5nm之範圍。
在一些實施例中，由於閘極介電層165之相對低的沈積溫度，例如300℃至500℃，閘極介電層165是 非晶矽或多晶矽的。如圖27B所示，每個第二半導體層120的頂表面與底表面係已被單晶氧化層110覆蓋。因此，閘極介電層165是直接地形成在第二半導體層120的側面上、最底部之單晶氧化層110上及閘極間隙149的餘留內壁上。因此，在第二半導體層120(通道區域)的頂表面與底表面之閘極介電質的有效厚度，係大於第二半導體層120的側面上之閘極介電質的有效厚度。
在一些實施例中，進行退火操作以結晶化所沈積的閘極介電層165。在這樣的情形下。整個閘極介電質係被結晶化。
接著，如圖28A與圖28B所示，在閘極間隙149內，形成金屬閘極結構170。圖28A係透視示意圖，且圖28B係繪示圖28A之沿著線A-A’的閘極間隙149內之剖視示意圖。金屬閘極結構170包含功函數調節材料(即功函數調節層172)與主體閘極電極層174的一或多層。
功函數調節層172是由如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的單一層之導電材料所製成，或者是由兩個或多個前述材料之所組成的多層導電材料所製成。於n通道FET，使用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi的一個或多個做為功函數調節層。於p通道FET，使用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co的一個或多個做為功函數調節層。藉由ALD、PVD、CVD、電子束蒸發或其他適合的製程，可形成功函數調節層172。再者，功函 數調節層172可個別地形成，其中，n通道FET及p通道FET可使用不同的金屬層。
主體閘極電極層174包含導電材料的一或多層，例如例如鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他適合的材料及/或前述之組合。藉由CVD、ALD、電鍍或其他適合的方法，可形成主體閘極電極層174。金屬閘極電極層亦沈積於ILD層160的上表面上。接著，使用如CMP來平坦化形成於ILD層160上的金屬閘極電極層，直到暴露ILD層160的頂表面。在一些實施例中，於平坦化操作後，凹陷金屬閘極電極層(即金屬閘極結構170)，且於凹陷的閘極電極層上形成覆蓋絕緣層(圖未繪示)。覆蓋絕緣層包含一或多層氮化矽基材料(例如：SiN)。藉由沈積絕緣材料接續平坦化操作，可形成覆蓋絕緣層。
可理解的是，全繞閘極場效電晶體(gate-all-around field effect transistor，GAA FET)經過更進一步的CMOS製程，以形成如接觸/介層窗、內連接金屬層、介電層及/或鈍化層等的各種特徵。
圖28C係繪示圖28A之沿著線A-A’之剖視示意圖，且圖28D係繪示圖28A之沿著線B-B’之剖視示意圖。如圖28C所示，閘極介電質包繞每個第二半導體層120。閘極介電質包含側部分(由閘極介電層165所製成)及結晶氧化層(即單晶氧化層110)，其中側部分係設置於於第二半導體層(做為線)的通道區域之側表面，結晶氧化層係設 置於第二半導體層120的上表面與下表面。在一些實施例中，無功函數調節層172係設置於第二半導體層120的鄰近通道區域間。換言之，第二半導體層120的鄰近通道區域間的間隙被閘極介電質完全地填滿。在一些實施例中，其中第二半導體層120之通道區域的寬度W與厚度T滿足1<W/T
Figure 108132109-A0305-02-0028-5
20。在其他實施例中，2<W/T
Figure 108132109-A0305-02-0028-6
10。
如圖28D所示，在源極/汲極區域中，第一半導體層105仍在第二半導體層120的源極/汲極區域與底部鰭結構102之間。無單晶氧化層設置於第二半導體層120的源極/汲極區域中。相對的，第一半導體層105與結晶氧化層(即單晶氧化層110)係設置於側壁間隙壁148的底部與底部鰭結構102之間。
在前述的實施例中，形成如犧牲層的第一半導體層105或中介層。在其他實施例中，未形成第一半導體層105，且單晶氧化層110與第二半導體層120所組成的一或多對材料層是直接形成於基材100上。
在前述的實施例中，頂部單晶氧化層及最底部之單晶氧化層的厚度係視閘極介電層165的沈積調整而定，以使包繞第二半導體層120的閘極介電質的厚度是實質一致的(如±10%)。
圖29A至圖32C係繪示根據本揭露的另一實施例之製造半導體FET裝置的各個階段之示意圖。應理解的是，額外的操作可以於圖29A至圖32C中所繪示的製程之前、之中或之後提供，且在方法的額外實施例中，一些下述 的操作可以被取代或省略。操作及/或製程的順序可為可替換的。參照圖1至圖28D說明的前述實施例，可使用於29A至圖32C相同或相似的材料、配置、尺寸及/或製程，且其細節的說明可被省略。
圖29A係繪示製造半導體FET裝置的各個階段之一者的透視示意圖，圖29B係繪示圖29A之沿著線A-A’之剖視示意圖。在此實施例中，於第一半導體層105形成於基材後，一或多個堆疊結構形成於第一半導體層105上。每個堆疊結構包含底單晶氧化層110、於單晶氧化層110上的第二半導體層120及頂部單晶氧化層110。再者，於第一半導體層105上，可替換地形成一個或多個堆疊結構及一個或多個第三半導體層107。在一些實施例中，第三半導體層107是以與基材100及第二半導體層120不同的材料所製成。在一些實施例中，第三半導體層107是由與第一半導體層105相同的材料所製成。
在圖29A與圖29B中，兩對堆疊結構將第三半導體層107夾於其中間。然而，堆疊結構的數量並不限於此，而可為一或多於兩對。在一些實施例中，堆疊結構的數量高達20。當堆疊結構的數量為N(N為自然數)，則第三半導體層的數量為N-1。
然後，進行相同或相似於圖18至圖25B的製造操作，且如圖30A至圖30C所示，形成閘極間隙149。圖30A係透視示意圖，圖30B係繪示圖30A之沿著線A-A’的閘極間隙149內之剖視示意圖，且圖30C係繪示圖30A之沿著線 B-B’之剖視示意圖。如圖31A至圖31C所示，在去除犧牲閘極結構後，接著去除第一半導體層105及第三半導體層107。圖31A係透視示意圖，圖31B係繪示圖31A之沿著線A-A’的閘極間隙149內之剖視示意圖，且圖31C係繪示圖31A之沿著線B-B’之剖視示意圖。相較於基材100(底鰭結構102)與第二半導體層120，當第一半導體層105與第三半導體層107是以不同的材料所製成時，藉由適合的化學溶液，可選擇性地去除第一半導體層及第三半導體層。餘留的第二半導體層120為FET的通道區域。
接著，進行相同或相似於圖27A至圖28D的製造操作，如圖32A至圖32D所示，於閘極間隙149內形成閘極介電層165與金屬閘極結構170。圖32A係透視示意圖，圖32B與圖32C係繪示圖32A之沿著線A-A’的閘極間隙149內之剖視示意圖，且圖32D係繪示圖32A之沿著線B-B’之剖視示意圖。如圖32C所示，在此實施例中，藉由閘極介電質(單晶氧化層110與閘極介電層165)及至少一功函數金屬層(即功函數調節層172)，包繞每個第二半導體層120(通道區域)。在一些實施例中，無主體金屬閘極電極(即主體閘極電極層174)係設置於通道區域之間，且在其他實施例中，至少一部分的主體金屬閘極電極(即主體閘極電極層174)係設置於通道區域之間。單晶氧化層110係設置於側壁間隙壁148之下，但不在源極/汲極區域中。
圖33A至圖33C係繪示根據本揭露之一實施例的各種閘極結構之示意圖。
圖33A對應於圖14的FET，圖33B對應於圖28A至圖28D的GAA FET，且圖33C對應於圖32A至圖32D的GAA FET。「氧化層1」係指單晶氧化層，且「層2」係指結晶氧化層、非晶氧化層或多晶氧化層之一者。在一些實施例中，其中通道區域的寬度W與厚度T滿足1<W/T
Figure 108132109-A0305-02-0031-7
20。在其他實施例中，2<W/T
Figure 108132109-A0305-02-0031-8
10。在一些實施例中，T的範圍為在約2nm至約10nm，且W的範圍為在約5nm至約20nm。
相較於先前技術，此處所述之各種實施例或例示提供各種優點。舉例來說，在本揭露之一實施例中，在裝置區域中的平坦表面上，形成單晶氧化層，且無圖案化操作無於此平坦表面上。在具有目標結晶度半導體基材上，這樣的沈積方法允許在原子層級上有精準的沈積控制，導致單晶氧化層成長。在一些實施例中，單晶氧化層可在無任何額外的退火製程下獲得。此外，由於單晶氧化層係於製造階段的早期形成，氧化物一旦達到完全的結晶度，只要製程溫度低於氧化層的熔點(例如HfO2的2758℃)，任何後續熱處理將不會改變結晶度。使用單晶氧化層做為閘極介電質，可獲得具有無過渡區域的通道之陡峭界面，實現閘極的長度縮減。
應理解的是，並非所有的優點均於須於此處討論，沒有特定的優點需列於所有的實施例或例示中，且其他實施例或例示可提供不同的優點。
根據本揭露之一實施例的一態樣，在一種製造 半導體裝置的方法中，形成單晶氧化層於基材上。在形成單晶氧化層後，形成隔離結構，以定義出主動區域。形成閘極結構於主動區域內的單晶氧化層上。形成源極/汲極結構。在一或多個前述與下述的實施例中，單晶氧化層是由選自於由二氧化鉿(HfO2)、鉿鑭複合氧化物(La2Hf2O7)、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3)及二氧化鋯鉿(HfZrO2)所組成之族群之一者所製成。在一或多個前述與下述的實施例中，在形成閘極結構後，去除形成於源極/汲極區域上的單晶氧化層。在一或多個前述與下述的實施例中，形成源極/汲極結構包含，磊晶地形成源極/汲極半導體磊晶層於被去除之單晶氧化層所在的源極/汲極區域上。在一或多個前述與下述的實施例中，閘極結構包含功函數調節層、閘極電極層及側壁間隙壁，且單晶氧化層係設置於側壁間隙壁的底部與基材之間。在一或多個前述與下述的實施例中，功函數調節層係與側壁間隙壁相接觸。在一或多個前述與下述的實施例中，單晶氧化層係在實質自650℃至1000℃範圍中的溫度上形成。在或多個前述與下述的實施例中，於形成單晶氧化層後，在實質自650℃至1000℃的範圍中溫度上進行退火操作。
根據本揭露之一實施例的另一態樣，在一種製造半導體裝置的方法中，形成第一半導體層於半導體基材上。形成由單晶氧化層和位於單晶氧化層上之第二半導體層所組成之一或多對材料層，並接續形成頂部結晶氧化層(即頂部單晶氧化層)。藉由蝕刻頂部結晶氧化層(即頂部單晶氧化 層)、一或多對材料層、第一半導體層及半導體基材的一部分，來形成鰭結構。形成隔離絕緣層。形成犧牲閘極結構於鰭結構上。於源極/汲極區域內，去除在一或多對材料層中之頂部單晶氧化層及單晶氧化層。形成源極/汲極磊晶層於源極/汲極區域內。形成層間介電層。去除犧牲閘極結構，藉以形成閘極間隙。去除在一或多對材料層中的第一半導體層於閘極間隙內。形成閘極介電層在閘極間隙中。形成閘極電極結構在閘極間隙中。在一或多個前述與下述的實施例中，單晶氧化層及頂部單晶氧化層係由選自由二氧化鉿(HfO2)、鉿鑭複合氧化物(La2Hf2O7)、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3)及二氧化鋯鉿(HfZrO2)所組成之族群之一者所製成。在一或多個前述與下述的實施例中，第一半導體層是由SixGe1-x所製成，且第二半導體層是由SiyGe1-y所製成，其中x<y
Figure 108132109-A0305-02-0033-9
1。在一或多個前述與下述的實施例中，形成側壁間隙壁於犧牲閘極結構之相對的側面上，其中頂部單晶氧化層及一或多對的材料層係在側壁間隙壁的下方。在一或多個前述與下述的實施例中，閘極介電層係由與在一或多對材料層中之頂部單晶氧化層及單晶氧化層相同的材料所製成。在一或多個前述與下述的實施例中，閘極介電層是非晶質。在一或多個前述與下述的實施例中，閘極介電層的厚度小於頂部單晶氧化層及在一或多對材料層中之單晶氧化層其中至少一者之厚度。在一或多個前述與下述的實施例中，頂部單晶氧化層的厚度不同於一或多對材料層中之單晶氧化層。在一或多個前述與下述的實施例中，第二半導體層的寬度 W及第二半導體層的厚度T滿足2<W/T
Figure 108132109-A0305-02-0034-10
10。
根據本揭露之一實施例的又一態樣，在製造半導體裝置的方法中，形成第一半導體層於半導體基材上。交替地形成堆疊結構與一或多個第三半導體層。堆疊結構的每一者包含底部結晶氧化層(即底部單晶氧化層)、於底部單晶氧化層上的第二半導體和頂部結晶氧化層(即頂部單晶氧化層)。藉由蝕刻堆疊結構形成鰭結構、一或多層第三半導體層、第一半導體層與半導體基材的一部分。形成犧牲閘極結構於鰭結構上。於源極/汲極區域內，去除在堆疊結構內的頂部單晶氧化層與底部單晶氧化層。形成源極/汲極磊晶層於源極/汲極區域內。形成層間介電層。去除犧牲閘極結構，藉以形成閘極間隙。去除在閘極間隙中的第一半導體層與一或多層的第三半導體層。形成閘極電極結構在閘極間隙中。在一或多個前述與下述的實施例中，頂部結晶氧化層(即頂部單晶氧化層)與底部結晶氧化層(即底部單晶氧化層)係由選自由二氧化鉿(HfO2)、鉿鑭複合氧化物(La2Hf2O7)、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3)及二氧化鋯鉿(HfZrO2)所組成之族群之一者所製成。在一或多個前述與下述的實施例中，閘極電極結構的部分是設置於在堆疊結構之一者中的底部結晶氧化層(即底部單晶氧化層)與在鄰近堆疊結構之者中之頂部結晶氧化層(即頂部單晶氧化層)。
根據本揭露之一實施例的再一態樣，半導體裝置包含通道、設置於通道上的閘極介電層、設置於閘極介電層上的閘極電極層、設置於閘極電極層之相對的兩面上之側 壁間隙壁與源極和汲極。閘極介電層包含結晶氧化層，且閘極介電層延伸至低於側壁間隙壁。在一或多個前述與下述的實施例中，結晶氧化層係由選自由二氧化鉿(HfO2)、鉿鑭複合氧化物(La2Hf2O7)、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3)及二氧化鋯鉿(HfZrO2)所組成之族群之一者所製成。在一或多個前述與下述的實施例中，閘極電極層包含功函數調節層與金屬閘極電極層，且功函數調節層與側壁間隙壁相接觸。
根據本揭露之一實施例的又另一態樣，一種全繞閘極場效電晶體(gate-all-around field effect transistor，GAAFET)，包含設置於底部鰭結構上且包括通道區域的半導體線、包覆通道區域的閘極介電層和設置於閘極介電層上的閘極電極。閘極介電層包含設置於上表面的單晶氧化層和半導體線之通道區域的下表面。在一或多個前述與下述的實施例中，單晶氧化層係由選自由二氧化鉿(HfO2)、鉿鑭複合氧化物(La2Hf2O7)、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3)及二氧化鋯鉿(HfZrO2)所組成之族群之一者所製成。在一或多個前述與下述的實施例中，閘極介電層包含設置於半導體線之通道區域的側表面之側部，且側部是由與結晶氧化層(即單晶氧化層)相同的材料製成。在一或多個前述與下述的實施例中，閘極介電層的側部是非晶質。在一或多個前述與下述的實施例中，單晶氧化層的厚度是不同於閘極介電層的側部之厚度。在一或多個前述與下述的實施例中，GAA FET更包含包覆半導體線的源極/汲極區域且 設置於底部鰭結構上之源極/汲極磊晶層。在一或多個前述與下述的實施例中，GAA FET更包含設置於閘極電極的相對側面之側壁間隙壁。中介層與單晶氧化層隙設置在側壁間隙壁與底部鰭結構之間。在一或多個前述與下述的實施例中，無單晶氧化層係設置於半導體線的源極/汲極區域。在一或多個前述與下述的實施例中，GAA FET更包含一或多個額外的半導體線，每個半導體線包含通道區域與源極/汲極區域。閘極介電層包覆一或多個額外半導體線之每一者的通道區域。在一或多個前述與下述的實施例中，閘極電極包含功函數調節層與金屬閘極電極層，且無功函數調節層係設置於在半導體線中鄰近的通道區域與一或多個額外的半導體線之間。在一或多個前述與下述的實施例中，半導體線的通道區域之寬度W與厚度T滿足2<W/T
Figure 108132109-A0305-02-0036-11
10。
根據本揭露之一實施例的又再一態樣，一種全繞閘極場效電晶體(gate-all-around field effect transistor，GAAFET)，包含第一半導體線及第二半導體線，設置於底部鰭結構上，且第一半導體線和第二半導體線之每一者包含通道區域及源極/汲極區域。第一閘極介電層，包覆第一半導體線的通道區域。第二閘極介電層，包覆第二半導體線的通道區域。閘極電極，設置於第一閘極介電層及第二閘極介電層上，其中第一閘極介電層和第二閘極介電層之每一者包含單晶氧化層，單晶氧化層設置於通道區域的上表面及底表層上。閘極電極的一部分係設置在第一半導體線的通道區域與第二半導體線的通道區域之間。在一或多個前 述與下述的實施例中，單晶氧化層係由選自由二氧化鉿(HfO2)、鉿鑭複合氧化物(La2Hf2O7)、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3)及二氧化鋯鉿(HfZrO2)所組成之族群之一者所製成。在一或多個前述與下述的實施例中，閘極介電層包含設置於第二半導體線之通道區域的側面上的側部，且閘極介電層是由與結晶氧化層(即單晶氧化層)相同的材料所製成。在一或多個前述與下述的實施例中，GAA FET更包含設置於第一半導體線的源極/汲極區域與底部鰭結構之間的第一中介半導體層，和設置於第二半導體線的源極/汲極區與第一半導體層的源極/汲極區域之間的第一中介半導體層。在一或多個前述與下述的實施例中，第一半導體線與第二半導體線的通道區域之寬度W與厚度T滿足2<W/T
Figure 108132109-A0305-02-0037-12
10。
前述內容概述若干實施例之特徵以使得熟習此項技術者可較佳地理解本揭露之一實施例的內容態樣。熟習此項技術者應理解，其可容易地使用本揭露之一實施例的內容做為設計或修改其他製程及結構之基礎用於進行本文中所介紹之實施例之相同的目的及/或達成相同的優點。熟習此項技術者應同時意識到，此等等效建構不偏離本揭露之一實施例的內容之精神及範疇，且其可在本文中進行各種變化、替代及修飾而不偏離本揭露之一實施例的內容之精神及範疇。
10:基材
20:單晶氧化層
30:淺溝槽隔離區域
48:側壁間隙壁
50:源極/汲極磊晶層
60:層間介電層
65:接觸蝕刻停止層
70:金屬閘極電極
72:功函數調節層
74:主體閘極電極層

Claims (10)

  1. 一種製造半導體裝置的方法，包含：形成一單晶氧化層於一基材上；在形成該單晶氧化層後，形成一隔離結構，以定義出一主動區域；形成一閘極結構於該主動區域內的該單晶氧化層上；在形成該閘極結構後，去除在一源極/汲極區域上之該單晶氧化層；以及形成一源極/汲極結構於該源極/汲極區域上。
  2. 如申請專利範圍第1項所述之製造半導體裝置的方法，其中該單晶氧化層是由選自於由二氧化鉿(HfO2)、鉿鑭複合氧化物(La2Hf2O7)、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3)及二氧化鋯鉿(HfZrO2)所組成之族群之一者所製成。
  3. 如申請專利範圍第1項所述之製造半導體裝置的方法，其中，該閘極結構包含一功函數調節層、一閘極電極層及複數個側壁間隙壁；以及該單晶氧化層係設置於該些側壁間隙壁的複數個底部與該基材之間。
  4. 如申請專利範圍第3項所述之製造半導體裝置的方法，其中該功函數調節層係與該側壁間隙壁相接觸。
  5. 一種製造半導體裝置的方法，該製造半導體裝置的方法包含：形成一第一半導體層於一半導體基材上；形成由一單晶氧化層和位於該單晶氧化層上之一第二半導體層所組成之一或多對材料層，並接續形成該頂部單晶氧化層；藉由蝕刻該頂部單晶氧化層、該一或多對材料層、該第一半導體層及該半導體基材的一部分，來形成一鰭結構；形成一隔離絕緣層；形成一犧牲閘極結構於該鰭結構上；於一源極/汲極區域內，去除在該一或多對材料層中之該頂部單晶氧化層及該單晶氧化層；形成一源極/汲極磊晶層於該源極/汲極區域內；形成一層間介電層；去除該犧牲閘極結構，藉以形成一閘極間隙；去除在該一或多對材料層中的該第一半導體層於該閘極間隙內；形成一閘極介電層在該閘極間隙中；以及形成一閘極電極結構在該閘極間隙中。
  6. 如申請專利範圍第5項所述之製造半導體裝置的方法，其中該第一半導體層是由SixGe1-x所製成，且該第二半導體層是由SiyGe1-y所製成，其中x<y
    Figure 108132109-A0305-02-0041-13
    1。
  7. 如申請專利範圍第5項所述之製造半導體裝置的方法，其中該閘極介電層的一厚度小於該頂部單晶氧化層及在該一或多對材料層中之該單晶氧化層其中至少一者之一厚度。
  8. 如申請專利範圍第5項所述之製造半導體裝置的方法，其中該頂部單晶氧化層的一厚度不同於該一或多對材料層中之該單晶氧化層。
  9. 如申請專利範圍第5項所述之製造半導體裝置的方法，其中該第二半導體層的一寬度W及該第二半導體層的一厚度T滿足2<W/T
    Figure 108132109-A0305-02-0042-14
    10。
  10. 一種全繞閘極場效電晶體(gate-all-around field effect transistor，GAAFET)，包含：一第一半導體線及一第二半導體線，設置於一底部鰭結構上，且該第一半導體線和該第二半導體線之每一者包含一通道區域及一源極/汲極區域；一第一閘極介電層，包覆該第一半導體線的該通道區域；一第二閘極介電層，包覆該第二半導體線的該通道區域；一閘極電極，設置於該第一閘極介電層及該第二閘極介電層上，其中第一閘極介電層和該第二閘極介電層之每一者包含一單晶氧化層，該單晶氧化層設置於該通道區域的一上表面及一底表層上；以及 該閘極電極的一部分係設置在該第一半導體線的該通道區域與該第二半導體線的該通道區域之間。
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