CN107251204A - 用于电子和空穴迁移率增强的双鳍集成 - Google Patents

用于电子和空穴迁移率增强的双鳍集成 Download PDF

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CN107251204A
CN107251204A CN201680011417.5A CN201680011417A CN107251204A CN 107251204 A CN107251204 A CN 107251204A CN 201680011417 A CN201680011417 A CN 201680011417A CN 107251204 A CN107251204 A CN 107251204A
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CN107251204B (zh
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刘作光
陈家佑
山下典洪
王苗苗
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Shanghai Youci Information Technology Co., Ltd
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International Business Machines Corp
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Abstract

提供了一种用于形成半导体器件的技术。在半导体层上的硬掩模层之上形成牺牲芯棒。在牺牲芯棒的侧壁上形成间隔体。移除牺牲芯棒以留下间隔体。掩模工艺留下暴露的间隔体的第一组，第二组被保护。响应于掩模工艺，第一鳍蚀刻工艺经由间隔体的第一组在半导体层中形成鳍的第一组。鳍的第一组具有垂直的侧壁轮廓。另一个掩模工艺留下暴露的间隔体的第二组，间隔体的第一组和鳍的第一组被保护。响应于其他的掩模工艺，第二鳍蚀刻工艺使用间隔体的第二组在半导体层中形成鳍的第二组。鳍的第二组具有梯形的侧壁轮廓。

Description

用于电子和空穴迁移率增强的双鳍集成
技术领域
本公开总体上涉及一种集成电路器件制造中的电子和空穴迁移率，并且更具体地涉及一种用于电子和空穴迁移率增强的双鳍集成。
背景技术
在固体物理中，电子迁移率表征了在被电场拉动时电子可以多快速地移动穿过金属或者半导体。在半导体中，对于空穴存在类似的量，称为空穴迁移率。术语载流子迁移率通常是指半导体中的电子和空穴迁移率两者。
电子和空穴迁移率是在施加的电场之下的带电粒子的电学迁移率的特殊情况。例如，在电场E施加到一块材料上时，电子通过以称为漂移速度的平均速度移动来响应。
电导率正比于迁移率与载流子浓度的乘积。例如，相同的电导率可以来自具有对于每个的高迁移率的少量的电子或者具有对于每个的小迁移率的大量电子。对于半导体，根据存在具有低迁移率的许多电子还是具有高迁移率的少量电子，晶体管和其他器件的行为可能非常不同。因此，迁移率是对于半导体材料非常重要的参数。几乎总是，当其他情况相同时，更高的迁移率导致更好的器件性能。
因此，本领域存在改善上述行为的需求。
发明内容
实施例包括形成半导体器件的方法。该方法包括在硬掩模层之上形成多个牺牲芯棒，其中硬掩模层设置在半导体层之上，在多个牺牲芯棒的侧壁上形成多个间隔体，移除多个牺牲心轴以留下多个间隔体，以及进行掩模工艺以留下暴露的多个间隔体的第一组，多个间隔体的第二组被保护。响应于掩模工艺，进行第一鳍蚀刻工艺，以使用多个间隔体的第一组在半导体层中形成鳍的第一组，其中鳍的第一组具有垂直的侧壁轮廓。进行另一个掩模工艺以留下暴露的多个间隔体的第二组，多个间隔体的第一组和鳍的第一组被保护。响应于其他掩模工艺，进行第二鳍蚀刻工艺，以使用多个间隔体的第二组在半导体层中形成鳍的第二组，其中鳍的第二组具有梯形的侧壁轮廓。
实施例包括形成半导体器件的方法。该方法包括在基板上形成梯形形状的鳍，其中梯形形状的鳍的梯形形状增强电子迁移率，以及在基板上形成垂直形状的鳍。垂直形状的鳍的笔直的垂直形状增强空穴迁移率，并且梯形形状的鳍具有比垂直形状的鳍更大的基部。集成电路由梯形形状的鳍和垂直形状的鳍形成。
实施例包括半导体器件。在基板上形成梯形形状的鳍，其中梯形形状的鳍的梯形形状增强电子迁移率。在基板上形成垂直形状的鳍，其中垂直形状的鳍的笔直的垂直形状增强空穴迁移率。梯形形状的鳍具有比垂直形状的鳍更大的基部。梯形形状的鳍和垂直形状的鳍作为集成电路中的元件一起形成。
通过本文所描述的技术，实现附加的特征和优点。其他实施例和方面在本文详细描述。为了更好地理解，参照说明书和附图。
附图说明
现在将参考优选的实施例，仅以示例性方式描述本发明，如以下附图所图示：
图1图示了根据现有技术的鳍场效应晶体管(FinFET)器件的示例，并且其中可以实现本发明的优选的实施例；
图2图示了根据本发明的优选的实施例的鳍结构的示例；
图3A到3J一起图示了根据本发明的优选的实施例的制造用于电子和空穴迁移率增强的双鳍集成结构的工艺流程，其中：
图3A图示了沉积在基板上的鳍材料层的层，和沉积在鳍材料上的鳍硬掩模，连同沉积在鳍硬掩模上的间隔体和牺牲层；
图3B图示了移除牺牲层以留下自支(free standing)间隔体；
图3C图示了在为NFET指定的区域之上沉积掩模；
图3D图示了蚀刻以获得垂直的鳍侧壁，同时保持对指定的NFET区域的保护；
图3E图示了从指定的NFET区域移除掩模；
图3F图示了在为PFET指定的区域之上沉积掩模；
图3G图示了蚀刻以获得渐缩的鳍侧壁，同时保持对指定的PFET区域的保护；
图3H图示了从指定的PFET区域移除掩模；
图3I图示了从垂直的鳍和渐缩的鳍的顶部上移除鳍硬掩模；以及
图3J图示了在垂直的鳍和渐缩的鳍两者之上沉积栅极氧化物和栅极；
图4图示了根据本发明的优选的实施例的渐缩的鳍的进一步的细节。
图5A和5B图示了根据本发明的优选的实施例的形成具有用于电子和空穴迁移率增强的双鳍集成的半导体器件的方法。
图6图示了根据本发明的优选的实施例的形成具有用于电子和空穴迁移率增强的双鳍集成的半导体器件的方法；以及
图7图示了根据现有技术的具有能力的计算机的示例，并且在其中可以实现本发明的优选的实施例。
在所公开的实施例的附图和以下详细的描述中，附图中图示的各种元件提供有三位或四位附图标记。每个附图标记最左边的(一个或多个)位对应于该元件第一次被图示的图。
具体实施方式
尽管平面场效应晶体管(FET)可能似乎已经达到其可扩展的寿命的尽头，但是半导体工业已经找到了采用FinFET的替代方法。FinFET技术被许多人视为下一代先进工艺的最佳选择。
采用先进的几何平面FET技术(诸如20纳米(nm))，源极和漏极侵入沟道，使得漏电流更容易在它们之间流动，并且使得非常难以完全关闭晶体管。FinFET是在基板上升起并且类似鳍的三维结构，由此得名。图1图示了FinFET器件100的一个示例。鳍10可以形成在基板50上。鳍10形成源极20和漏极25(在相对的端部上)，对于相同区域有效地提供比平面晶体管更多体积。栅极30环绕鳍10，在器件在“关闭”状态时，提供更好的沟道控制并且允许非常少量的电流通过主体泄露。进而，这使更低的阈值电压的使用成为可能，并且导致与平面晶体管相比更好的性能和功率。
图2图示了示例性鳍结构200。在FinFET中，鳍的(z方向)高度(HFin)是对于每英寸的总有效电流(Ieff)的大旋钮(great knob)(可变，variable)，因为Weff＝2HFin+DFin。DFin是在y方向上的宽度。Weff是有效沟道宽度。为了解释的目的，假设电流在箭头205、210、215的方向上(例如，在x方向上)移动，即使电子和空穴(电子的缺失)可以在相反的方向上移动。电流沿着鳍200的外表面流动。
鳍取向是非常有密切关系的，因为载流子迁移率通常是各向异性的(在各个方向上不相同)。例如，电子迁移率在(100)平面((100)平面等于(001)平面)上最高。(100)平面(即，x-y平面)具有在-x方向内的电流箭头205。电子迁移率(电流的流动)在表示为在电流箭头205中的流动的(100)平面中最高，但是空穴迁移率最低。(100)平面(x-y平面)是鳍200中的具有宽度“d”的顶部表面。
相反地，(110)平面中的空穴迁移率最大，但是电子迁移率最低。(110)平面(即，x-z平面)具有在-x方向上的电流210。空穴迁移率(电流的流动)在表示为电流箭头210中的流动的(110)平面中最高。(110)平面(x-z平面)是鳍200中的具有高度“a”的垂直侧壁。
另外，鳍结构200在基部处具有成角度的足。成角度的足以角度φ向外延伸。成角度的足产生示出电流箭头215的过渡平面。成角度的足的过渡平面中，电子迁移率和空穴迁移率既不是最高的也不是最低的，而是在之间。
在绝缘体上硅(SOI)FinFET中，平面(110)通常作为基板以提高空穴迁移率，因为电子迁移率本征地大于空穴迁移率。电子在负沟道场效应晶体管(NFET)中是多数载流子，同时空穴在正沟道场效应晶体管(PFET)中是多数载流子。在确定鳍的尺寸时，在增加鳍的空穴迁移率还是增加电子迁移率之间存在折衷。
根据实施例，公开了新颖的双鳍轮廓集成，以有益地使用对电子和空穴迁移率两者都有利的平面。图3A到3J一起图示了根据实施例的制造用于电子和空穴迁移率增强的双鳍集成结构的工艺流程。图3A图示了基板300，该基板300具有沉积在基板300上的鳍材料层302的层。鳍硬掩模304沉积在鳍材料层302上。
为了准备图案化(将来的)鳍并且限定鳍的节距(pitch)，进行间隔体光刻。间隔体光刻可以包括侧壁像转印(SIT)。牺牲层306的块(芯棒)由层沉积、图案化和蚀刻形成，并且间隔体308(SIT间隔体)在芯棒306的侧壁表面上形成。可以通过例如芯棒304和芯棒306上的毯式沉积(blanket deposition)以及之后的通过各向异性(方向性)蚀刻以移除间隔体层材料的水平设置的表面来形成间隔体层308。
基板300可以是诸如绝缘体的材料。鳍材料302可以是硅、锗等。鳍材料302的厚度确定了(正在制造的)鳍的高度。鳍硬掩模304可以是氧化物，诸如二氧化硅或者氧化锗。另外，鳍硬掩模304可以是氮化物。在鳍硬掩模304是氧化物时，间隔体308可以是氮化物，并且在鳍硬掩模304是氮化物时，间隔体308可以是氧化物。牺牲层306可以是多晶硅材料。间隔体308的宽度确定了鳍的宽度(正在为垂直的鳍和渐缩的鳍的顶部宽度制造)。
在图3B中，移除牺牲层306以留下自支间隔体308。四个自支间隔体308的区域限定了鳍的状况。为构建NFET指定两个左边的间隔体308，并且为构建PFET指定两个右边的间隔体。间隔体308的位置确定了将来的鳍的位置。间隔体308用于(同时形成的)PFET和NFET两者。间隔体308的规格(高度和宽度)可以对于PFET和NFET两者的鳍是相同的。
每个间隔体308的间隔体宽度313实质上相等。间隔体宽度313可以包含6-10nm的范围。间隔体中的每一个之间的节距311实质上相等。节距311可以是，例如，21nm-32nm。
图3C图示了掩模310沉积在两个左边的间隔体308(为NFET所指定的)之上并且沉积在鳍硬掩模304的左边部分之上，以保护两个左边的间隔体308和鳍硬掩模304的左边部分。此外，在发生蚀刻以准备PFET的鳍之前，掩模310保护为NFET指定的区域。
图3D图示了诸如反应离子蚀刻RIE的蚀刻，以移除不紧贴在两个右侧的间隔体308之下的鳍硬掩模304和鳍材料302。指定的PFET区域中的蚀刻形成PFET的笔直的鳍侧壁(110)平面，同时保持对指定的NFET区域的保护。微调可以是干法蚀刻的蚀刻和时间，以获得两个垂直的轮廓鳍315。例如，在蚀刻达到其终止点(例如，在基板300上停止)后，可以微调过蚀刻时间和角度以获得垂直的鳍。
在图3E中，通过例如干法蚀刻移除掩模310。图3F图示了掩模320沉积在两个右边的间隔体308之上并且沉积在指定的PFET区域中的硬掩模304之上，以保护两个右边的间隔体308和鳍硬掩模304的右边部分。在这种情况下，在发生蚀刻以准备NFET的鳍之前，掩模320保护为PFET指定的区域。掩模310和320可以是氧化物。
图3G图示了蚀刻(例如，RIE)，以获得接近两个渐缩的鳍325的(100)平面的渐缩的鳍侧壁。微调蚀刻(例如，干法蚀刻)和时间，以获得两个渐缩的鳍325。渐缩的鳍325形成为梯形形状，并且梯形的底部处的基部比梯形的顶部处的宽度更宽。例如，在蚀刻达到其终止点(例如，在基板300上停止)后，可以微调过蚀刻时间的缩短以获得渐缩的鳍。
图3H图示了掩模320从指定的PFET区域移除。鳍硬掩模304从渐缩的鳍325和垂直的鳍315的顶部上移除。在鳍材料302和鳍硬掩模304的相同的沉积工艺期间/共用鳍材料302和鳍硬掩模304的相同的沉积工艺，渐缩的鳍325和垂直的鳍315可以紧密接近，并且仍然对电子迁移率(NFET)和空穴迁移率(PFET)分别优化。渐缩的鳍325和垂直的鳍315之间的间隔“s”可以大致地为18-30nm。
图3I图示了鳍硬掩模304从垂直的鳍315和渐缩的鳍325的顶部移除。在图3I中，双鳍结构380具有制造为具有增强的NFET的电子迁移率的渐缩的鳍325和制造为具有增强的空穴迁移率的垂直的鳍315两者。垂直的鳍315和渐缩的鳍325两者具有高度“h”。渐缩的鳍325的顶部具有与垂直的鳍315相同的宽度“d”。然而，垂直的鳍325的基部具有更宽的基部宽度“bw”。顶部宽度“d”可以是约5或6纳米(nm)。基部宽度“bw”可以是约11或12纳米(nm)。此外，基部宽度“bw”设计为约顶部宽度“d”的两倍，使得电子迁移率沿着渐缩的平面(如图4中的渐缩的侧壁所示)改善。高度“h”可以是约30-45nm，或者根据预期应用的期望。
即使每个间隔体308的间隔体宽度313可以是相等的(或者接近相等的)，并且在每个间隔体308之间的间隔体节距311是相等的(或者接近相等的)(如图3B所示)，制造工艺配置为优化在渐缩的鳍325中的电子迁移率且优化垂直的鳍315中的空穴迁移率(两者在相同的微处理器上)。
图3J图示了栅极堆叠体，栅极堆叠体包含沉积在垂直的鳍315和渐缩的鳍325两者之上的栅极氧化物层340和栅电极层350，从而形成两个NFET 360和两个PFET 365。蚀刻栅电极层350和栅极氧化物层340(在栅电极层350之下)，以形成如图3J所示的结构380(使用本领域技术人员已知的任何技术)。栅极氧化物层340环绕(顶部和侧部)渐缩的鳍325和垂直轮廓的鳍315，并且如本领域技术人员所理解的，栅电极层350在栅极氧化物层340的顶部，使得形成NFET 360和PFET 365。栅电极层350的栅极材料可以包含硅、锗、金属、金属合金及其组合，其采用掺杂剂掺杂以导电。栅极氧化物层340可以是高k电介质，例如，诸如氧化铪的薄层。
尽管图3A到3J示出了在形成NFET的渐缩(梯形)的鳍325之前构建PFET的垂直轮廓的鳍，实施例不意味限制于这种顺序。在一个实施例中，可以在PFET的垂直轮廓的鳍315之前形成NFET的渐缩(梯形)的鳍325。
图4图示了根据实施例的渐缩的鳍325的其他细节。如图2所讨论的，在(100)平面(x-y平面)中的电子迁移率是最高的，其对应于电流205。渐缩的鳍325具有渐缩的侧壁420，已经优化渐缩的侧壁420，使得电子迁移率增加为好于垂直的鳍315中的垂直侧壁并且好于图2中的成角度的足。渐缩的侧壁420越平(即，越水平)，电流415中的电子迁移率越好。由于顶部宽度“d”和高度“h”保持恒定，可以增加基部宽度“bw”以对应地增加电子迁移率(其减小了角度φ)。相应地，基部宽度“bw”应该为顶部宽度“d”的长度的约两倍。
重新参考图3I和3J，在相同结构(电路)上，用NFET的渐缩的鳍325和PFET的垂直的鳍315来优化双鳍结构380。双鳍结构308可以是微处理器。在一个示例中，双鳍结构308可以是静态随机存取存储器(SRAM)，其是半导体微处理器中构建块/电路。可以在相同的电路中采用双鳍结构308，以形成诸如“与(AND)”电路、“或(OR)”电路以及“非(NOT)”电路的各种逻辑电路。例如，双鳍结构308可以用作反相器电路。
现在转向图5A和5B，根据实施例，提供了形成(具有用于电子和空穴迁移率增强的双鳍集成的)半导体器件的方法500。可以参考本文所讨论的图1-4、6以及7。
在框505处，在硬掩模层304之上形成多个牺牲芯棒306，其中硬掩模层304设置半导体层302之上，如图3A所示。
在框510处，在牺牲芯棒306的侧壁上形成多个间隔体308，如图3A所示。在框515处，移除牺牲芯棒306以留下多个间隔体308，如图3B所示。
在框520处，进行掩模工艺，以留下暴露的多个间隔体308的第一组，多个间隔体308的第二组被保护，如图3C所示。在框525处，进行第一鳍蚀刻工艺，以使用间隔体308的第一组(例如，间隔体308的右边组)在半导体层302中形成鳍的第一组(例如，垂直轮廓的鳍315)，使得鳍315的第一组具有垂直的侧壁轮廓，如图3D和3E所示。
在框530处，进行另一个掩模工艺以留下暴露的间隔体308的第二组(例如，间隔体308的左边组)，同时保护间隔体308的第一组和鳍315的第一组，如图3F所示。在框535处，进行第二鳍蚀刻工艺，以使用间隔体308的第二组在的半导体层302中形成鳍的第二组(例如，梯形/渐缩的鳍325)，使得鳍325的第二组具有梯形的侧壁轮廓，如图3G所示。
在掩模工艺期间，第一掩模310覆盖多个间隔体308的第二组，并且第一掩模可以是氧化物。
在另一个掩模工艺期间，第二掩模320覆盖多个间隔体308的第一组，并且第二掩模可以是氧化物。
多个间隔体308包括氧化物和氮化物中的至少一个。半导体层302包括硅和锗中的至少一个。鳍315的第一组包括正沟道场效应晶体管(PFET)器件，并且鳍325的第二组包括负沟道场效应晶体管(NFET)器件，如图3J所示。在鳍315的第一组和鳍325的第二组之上形成栅电极350。
鳍325的第二组的基部宽度(“bw”)是鳍325的第二组的顶部宽度的长度的至少两倍(可以参考图4)。鳍325的第二组的高度(“h”)与鳍315的第一组的高度(“h”)约为相等。梯形形状的鳍325具有比垂直形状的鳍的基部“d”更大的基部(“bw”)。
集成电路包含鳍315的第一组和鳍325的第二组。单独的微处理器(例如，结构380)包含具有鳍315的第一组和鳍325的第二组的集成电路，使得鳍的第一组包括PFET器件365并且鳍的第二组包括NFET器件360。
相比于仅具有梯形形状的鳍或者仅具有垂直形状的鳍，通过具有相同的微处理器上的梯形形状的鳍325和垂直形状的鳍315两者(例如，双鳍结构380是半导体微处理器(即，芯片))增加了微处理器的速度。在微处理器双鳍结构380中，由于梯形/渐缩形状的鳍325，电子流在NFET 360中优化，并且同时地，由于垂直形状的鳍315，空穴流在PFET 365中优化。
图6图示了根据实施例的形成用于电子和空穴迁移率增强的半导体器件双鳍集成的方法600。可以参考本文所讨论的图1-5和7。
在框605处，提供了负沟道场效应晶体管(NFET)360，其中NFET 360具有由于源极和漏极的梯形形状的鳍325。源极在栅极350的一侧上，同时漏极跨过栅极350在梯形形状的鳍325的相反侧上。
在框610处，提供了正沟道场效应晶体管(PFET)，其中PFET具有垂直形状的鳍315。
在框615处，梯形形状的鳍具有比垂直形状的鳍更大的基部(基部宽度“bw”)，并且梯形形状的鳍和垂直形状的鳍一起在微处理器中(例如，在双鳍结构380中)的相同基板300上。
梯形的鳍325的基部宽度“bw”约为梯形的鳍325的顶部宽度“d”的长度的两倍。梯形的鳍325的高度“h”约等于垂直形状的鳍315的高度。
图7图示了具有能力的计算机700的示例，其可以包含在示例性实施例中。本文所讨论的各种方法、进程、模块、流程图、工具、应用、电路、元件和技术也可以整合和/或利用计算机700的能力。此外，可以利用计算机700的能力以实现本文所讨论的示例性实施例的特征。可以利用计算机700的一个或多个能力以实现、整合、连接到和/或支持本文所在图1-6中所讨论的任意元件(如本领域技术人员所知的)。
通常，在硬件架构方面，计算机700可以包括一个或多个处理器710、计算机可读储存存储器720以及一个或多个输入和/或输出(I/O)器件770，该I/O器件经由本地接口(未示出)通信耦接。本地接口可以例如但不限于是如本领域中已知的一个或多个总线或者其他有线或者无线的连接。本地接口可以具有附加的元件，诸如控制器、缓存器(高速缓存)、驱动器、中继器以及接收器，以使通信成为可能。进一步地，本地接口可以包括地址、控制和/或数据连接，以使前述的部件之间的适当的通信成为可能。
处理器710是用于执行可以储存在存储器720中的软件的硬件器件。处理器710实质上可以是与计算机700相关联的若干个处理器之中的任何定制的或者商业可得的处理器、中央处理单元(CPU)、数据信号处理器(DSP)或者辅助处理器，并且处理器710可以是基于半导体的微处理器(以微芯片的形式)或者微处理器。注意到，存储器720可以具有分布式架构，其中各种部件彼此远离，但是可以由处理器710存取。
计算机可读存储器720中的软件可以包含一个或多个分开的程序，其中的每一个包括用于实现逻辑功能的可执行指令的有序列表。存储器720中的软件包含示例性实施例的适当的操作系统(O/S)750和一个或多个应用760。如所图示的，应用760包括为实现示例性实施例的特征、工艺、方法和操作的许多功能性的部件。计算机700的应用760可以代表如本文所讨论的许多应用、代理、软件组件、模块、接口、控制器等，但是程序760不意味着是限制。
操作系统750可以控制其他计算机程序的执行，并且提供调度、输入-输出控制、文件和数据管理、存储器管理以及通信控制和相关服务。
应用760可以是源程序、可执行程序(目标代码)、脚本或者包括将进行的指令集的任何其他实体。在源程序时，则程序通常经由编译器、汇编器、注释器等(其可以或可以不被包含在存储器720内)来翻译，以便与O/S 750相连接地适当操作。进一步地，应用760可以被写为(a)面向对象的编程语言，其具有数据和方法的种类，或者(b)进程编程语言，其具有例程、子例程和/或功能。
I/O器件770可以包括输入器件(或周边设备)，比如，例如但不限于鼠标、键盘、扫描仪、麦克风、照相机等。进一步地，I/O器件770也可以包括输出器件(或周边设备)，例如但不限于打印机、显示器等。最后，I/O器件770可以还包含与输入和输出两者通信的器件，例如但不限于NIC或者调制器/解调器(用于存取远程器件、其他文件、器件、系统或者网络)、射频(RF)或者其他收发器、电话接口、桥接器、路由器等。I/O器件770也包括用于通过各种网络(诸如因特网或内联网)进行通信的部件。I/O器件770可以利用蓝牙连接和线缆(经由例如通用串行总线(USB)端口、串行端口、并行端口、火线(FireWire)、HDMI(高清多媒体接口)、PCIe、或者专有接口等)连接至处理器710和/或与处理器710相通信。
当计算机700在操作中时，处理器710被配置为执行存储器720内储存的软件，以将数据通信到存储器720和从存储器720通信数据，并且通常依照软件来控制计算机700的操作。应用760和O/S 750全部地或部分地由处理器710读取，可能在处理器710内缓冲，且然后执行。
当在软件中实现应用760时，应当注意的是，应用760可以储存在实质上任何计算机可读取储存介质上，用于由任何计算机相关的系统或者方法使用或者用于与任何计算机相关的系统或者方法连接使用。
应用760可以实施在任何计算机可读介质中，用于由指令执行系统、设备、服务器或器件使用或者与指令执行系统、设备、服务器或器件连接使用，并且执行指令，该指令执行系统、设备、服务器或器件为诸如基于计算机的系统、包含处理器的系统或者可以从指令执行系统的指令中取出指令的其他系统、设备或者器件。
在示例性实施例中，其中应用760在硬件中实现，应用760可以采用本领域中众所周知的以下技术中的任何一个或者其组合来实现：具有根据数据信号实现逻辑功能的逻辑门的(一个或多个)离散逻辑电路、具有适当的组合逻辑门的专用集成电路(ASIC)、(一个或多个)可编程门阵列(PGA)、现场可编程门阵列(FPGA)等。
可以理解的是，计算机700包括可以包括在本文所讨论的各种器件、服务器和系统中的软件和硬件部件的非限制性示例，并且可以理解的是，示例性实施例中所讨论的各种器件和系统中可以包括附加的软件和硬件部件。
在一些实施例中，可以在给定的位置处和/或与一个或多个设备或者系统相连接地发生各种功能或者行动。在一些实施例中，可以在第一器件或者位置处进行指定的功能或者行动的部分，并且可以在一个或多个附加的器件或者位置处进行功能或者行动的剩余部分。
本文所使用的术语仅是为了描述特定的实施例的目的，并且不意图作为限制。这里所用的，单数形式“一”和“一个”旨在包括复数形式，除非上下文另有明确指示。将进一步理解，当在本说明书中使用时，术语“包括”指定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除存在或附加一个或多个其他特征、整数、步骤、操作、元件部件和/或其的组合。
以下权利要求书中的所有方式或步骤加上功能元件的对应结构、材料、行动和等同物旨在包括与明确要求保护的其它要求保护的元件相结合来进行功能的任何结构、材料或行动。本公开已经为了说明和描述的目的而呈现，但并不旨在穷举或限于所公开的形式。在不脱离本公开的范围和精神的情况下，对本领域普通技术人员来说，许多修改和变化将是显而易见的。选择和描述了实施例，以便最好地解释本公开的原理和实际应用，并且使得本领域的其他普通技术人员能够理解采用适合于预期的特定用途的各种修改的各种实施例的本公开。
本文所描绘的图解是说明性的。在不脱离本公开的精神的情况下，本文所描述的图解或步骤(或操作)可能存在许多变化。例如，可以以不同的顺序进行动作，或者可以添加、删除或修改动作。另外，术语“耦合”描述了在两个元件之间具有信号路径，并且不隐含元件之间没有介于中间的元件/连接的直接连接。所有这些变化被认为是本公开的一部分。
应当理解的是，本领域技术人员现在和将来都可以作出落入所附权利要求的范围内的各种改善和增强。

Claims (20)

1.一种形成半导体器件的方法，所述方法包括：
在硬掩模层之上形成多个牺牲芯棒，所述硬掩模层设置在半导体层之上；
在所述多个牺牲芯棒的侧壁上形成多个间隔体；
移除所述多个牺牲芯棒以留下所述多个间隔体；
进行第一掩模工艺以留下暴露的所述多个间隔体的第一组，所述多个间隔体的第二组被保护；
响应于所述掩模工艺，进行第一鳍蚀刻工艺，以使用所述多个间隔体的所述第一组在所述半导体层中形成鳍的第一组，其中所述鳍的第一组具有垂直的侧壁轮廓。
进行第二掩模工艺，以留下暴露的所述多个间隔体的所述第二组，所述多个间隔体的所述第一组和所述鳍的第一组被保护。
响应于所述第二掩模工艺，进行第二鳍蚀刻工艺，以使用所述多个间隔体的所述第二组在所述半导体层中形成鳍的第二组，其中所述鳍的第二组具有梯形的侧壁轮廓。
2.根据权利要求1所述的方法，其中在所述第一掩模工艺期间，第一掩模覆盖所述多个间隔体的所述第二组。
3.根据权利要求2所述的方法，其中所述第一掩模是氧化物。
4.根据前述权利要求中任一项所述的方法，其中在所述第二掩模工艺期间，第二掩模覆盖所述多个间隔体的所述第一组。
5.根据权利要求4所述的方法，其中所述第二掩模是氧化物。
6.根据前述权利要求中任一项所述的方法，其中所述多个间隔体包含氧化物和氮化物中的至少一个。
7.根据前述权利要求中任一项所述的方法，其中所述半导体层包括硅和锗中的至少一个。
8.根据前述权利要求中任一项所述的方法，其中所述鳍的第一组包括正沟道场效应晶体管(PFET)器件。
9.根据权利要求1至7中任一项所述的方法，其中所述鳍的第二组包括负沟道场效应晶体管(NFET)器件。
10.根据前述权利要求中任一项所述的方法，其中在所述鳍的第一组和所述鳍的第二组之上形成栅电极。
11.根据前述权利要求中任一项所述的方法，其中所述鳍的第二组的基部宽度是所述鳍的第二组的顶部宽度的长度的至少两倍。
12.根据前述权利要求中任一项所述的方法，其中所述鳍的第二组的高度约等于所述鳍的第一组的高度。
13.根据前述权利要求中任一项所述的方法，其中集成电路包含所述鳍的第一组和所述鳍的第二组。
14.根据权利要求13所述的方法，其中单独的微处理器包含具有所述鳍的第一组和所述鳍的第二组的所述集成电路，使得所述鳍的第一组包括正沟道场效应晶体管器件并且所述鳍的第二组包括负沟道场效应晶体管器件。
15.一种形成半导体器件的方法，所述方法包括：
在基板上形成梯形形状的鳍，其中所述梯形形状的鳍的梯形形状增强电子迁移率；以及
在所述基板上形成垂直形状的鳍，其中所述垂直形状的鳍的笔直的垂直形状增强空穴迁移率，并且其中所述梯形形状的鳍具有比所述垂直形状的鳍更大的基部；
其中集成电路由所述梯形形状的鳍和所述垂直形状的鳍形成。
16.根据权利要求15所述的方法，其中所述梯形形状的鳍包括负负沟道场效应晶体管器件；并且
其中所述垂直形状的鳍包括正沟道场效应晶体管器件。
17.根据权利要求16所述的方法，其中所述集成电路是微处理器。
18.根据权利要求15至17中任一项所述的方法，还包括在所述梯形形状的鳍和所述垂直形状的鳍之上形成栅电极。
19.一种半导体器件，包括：
在基板上形成的梯形形状的鳍，其中所述梯形形状的鳍的梯形形状增强电子迁移率；以及
在所述基板上形成的垂直形状的鳍，其中所述垂直形状的鳍的笔直的垂直形状增强空穴迁移率，其中所述梯形形状的鳍具有比所述垂直形状的鳍更大的基部；
其中所述梯形形状的鳍和所述垂直形状的鳍作为集成电路中的部件一起形成。
20.根据权利要求19所述的半导体器件，其中具有所述梯形形状的鳍和所述垂直形状的鳍两者的所述集成电路是微处理器。
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