CN1695227A - 应变鳍型场效应晶体管互补金属氧化物半导体器件结构 - Google Patents

应变鳍型场效应晶体管互补金属氧化物半导体器件结构 Download PDF

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CN1695227A
CN1695227A CN02829920.5A CN02829920A CN1695227A CN 1695227 A CN1695227 A CN 1695227A CN 02829920 A CN02829920 A CN 02829920A CN 1695227 A CN1695227 A CN 1695227A
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finfet
dielectric substance
stress
film
semiconductor device
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CN100378901C (zh
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布鲁斯·B·多丽丝
杜里塞蒂·奇达姆巴拉奥
米凯·耶翁
杰克·A·曼德尔曼
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明公开了一种半导体器件结构，包括：设置在衬底(1，2)上的PMOS器件(200)和NMOS器件(300)，所述PMOS器件包括对所述PMOS器件的有源区施加应力的压力层(6)，所述NMOS器件包括对所述NMOS器件的有源区施加应力的张力层(9)，其中所述压力层包括第一电介质材料，所述张力层包括第二电介质材料，并且所述PMOS和NMOS器件是FinFET器件(200，300)。

Description

应变鳍型场效应晶体管互补金属氧化物半导体器件结构
技术领域
本发明涉及双栅极半导体器件结构，尤其涉及FinFET器件。
背景技术
由于获得近乎理想的亚阈值斜率(sub-threshold slope)的能力、不存在体效应、免于短沟道效应以及非常高的电流驱动能力，双栅极半导体器件结构是未来一代微电子器件有前途的选择。
一种技术相关的双栅极器件结构是鳍型场效应晶体管(FinFET)。与其它双栅极器件相比，由于制造相对简单，所以FinFET特别具有吸引力。用于FinFET的沟道是薄的矩形Si岛，通常称为鳍。栅极包绕该鳍，从而沟道在鳍结构的垂直部分的两侧被栅控，提供了优于平面单栅极MOSFET的栅极控制。
FinFET是公知的。例如，Hu等人的第6413802号美国专利，标题为“FinFET Transistor Structures Having a Double Gate Channel ExtendingVertically from a Substrate and Methods of Manufacture”，2000年10月23日提交，2002年7月2日发表，特此引入其全文作为参考。FinFET具有提高的迁移率也是公知的，例如，Armstrong等人的第2002/0063292 A1号美国专利申请，标题为“CMOS Fabrication Process Utilizing Special TransistorOrientation”，2000年11月29日提交，2002年5月30日公开，特此引入其全文作为参考。这种现有技术方法旨在改善nFET迁移率，因而只能获得CMOS电路中的有限改善。因此，需要一种方法来改善位于相同晶片上的p-FinFET及n-FinFET的迁移率。
然而，本发明人确信利用应力层来提高迁移率的改善是可以实现的。
发明内容
根据本发明，一种半导体器件结构包括设置在衬底上的PMOS器件及NMOS器件，该PMOS器件包括对PMOS器件的有源区施加应力的压力层，该NMOS器件包括对该NMOS器件的有源区施加应力的张力层，其中压力层包括第一电介质材料，张力层包括第二电介质材料，并且PMOS及NMOS器件是FinFET器件。
本发明旨在提供一种用于提高迁移率的新颖的应变FinFET器件结构。整合方案(integration scheme)包括了一种新工艺流程，其为p-FinFET引入纵向方向上的压应力，同时也为n-FinFET引入在纵向方向上的张应力。这些应力极大提高了迁移率，因此提高了器件性能。在此处描述的本发明中，沟道中引起的纵向应力比标准的平面MOSFET中能获得的应力有大幅度提高，因为应力膜从薄FinFET的两侧施加，而不是在SOI层或块衬底(bulksubstrate)的表面上。
本发明的主要目的是提高双栅极CMOS器件结构中的迁移率。
本发明的另一目的是提高FinFET器件结构中的迁移率。
本发明的再一目的是改进制造应变FinFET器件结构的方法。
本发明及其它目的和特征将从下面结合附图的详细描述中变得更清楚。
附图说明
图1和2示意性示出根据现有技术的FinFET的垂直(对于鳍)和平行(对于鳍)的视图；
图3示意性示出根据现有技术的FinFET半导体器件结构的垂直视图；
图4至17示意性示出根据本发明的中间及最终FinFET半导体器件结构的各种视图。
具体实施方式
本发明旨在提供一种新颖的FinFET半导体器件结构及其制造方法。根据本发明的优选的最终结构示于图16、17中。
现在参照其余的图，特别是图1至3，示出已知的FinFET器件(图1、2)及器件结构(图3)。
首先，进行标准或常规的FinFET器件的制造处理：构图并蚀刻鳍；形成栅极电介质及导体、侧壁隔离物(未示出)；掺杂源极/漏极；以及自对准金属硅化(salicidation)。在自对准金属硅化之后，去除栅极侧壁隔离物，从而有助于进行根据本发明的将在鳍中诱发应变的处理。
更具体地，如参照图3所描述的，提供例如SOI晶片。该SOI晶片包括设置在SiO2掩埋层2之下的衬底1，如图3所示。在SiO2掩埋层2之上是绝缘体上硅(SOI)层，其被构图成形成每个器件的有源区的区域，图1、2和3中示为鳍3。鳍可以通过本领域中公知的标准光刻和蚀刻操作形成。可选择地，已知的侧壁图像转移法(side wall image transfer method)可用于形成每个鳍3。
鳍形成之后，进行本领域公知的牺牲氧化过程，从而去除鳍蚀刻过程带来的任何损伤。如果利用阱注入来调整FinFET器件的阈值电压，则在阱注入期间牺牲氧化层可用作防止沟道效应(channeling)的屏蔽。
然后，通过干或湿蚀刻化学制品去除牺牲氧化物。例如，稀释的氢氟酸可用于去除牺牲氧化物。牺牲氧化物去除之后，可形成栅极电介质。栅极氧化可以是热SiO2、氮化的SiO2或氧氮化物。栅极电介质可以是如TaO5、HfO2的高K材料，或任何其它栅极电介质材料。
然后，栅电极材料沉积在整个晶片上，之后进行光刻和蚀刻过程。在图中栅电极标记为电极4。
栅极形成之后，可以使用本领域所公知的再氧化操作来改善栅极电介质的特性。栅极再氧化也可以省略。
工艺流程进行到这点，源极/漏极扩展可以被注入，在另一可选方法中，偏移隔离层(offset spacer)可以用来在栅极边缘与注入的鳍区域之间产生一距离。可使用光刻掩模来阻挡nFET区域使其不被注入，同时允许pFET区域被注入，这对于常规CMOS工艺技术是公知的。可使用类似操作来注入nFET区域，同时阻挡pFET区域。
形成源极漏极扩展区域之后，可以利用扩展退火(extension anneal)来修复离子注入造成的损伤。在另一可选方法中，退火可以省略。然后，通过沉积100至1000范围内的SiN膜来制成深源极漏极隔离物，然后进行高度定向蚀刻(highly directional etch)从而从水平表面去除SiN膜，同时在栅电极的垂直部分上遗留所述膜。
现在使用阻挡掩模(block mask)和离子注入来形成用于nFET器件区域30及pEET器件区域20的源极和漏极区域，这在CMOS工艺技术中是标准的。然后利用常规快速热退火工艺来激活(activate)由注入形成的结。这之后，进行使用CoSi2、TiSi、NiSi或本领域已知的任何其他硅化物的常规的自对准金属硅化物工艺(salicide process)。
工艺流程进行到这点，开始发明性的步骤和结构(图4至17)来改善n-FinFET和p-FinFET器件的器件性能。首先，如图4和图5所示，通过例如低温沉积技术设置(例如沉积)SiO2衬层(膜)5。膜厚度在25至300的范围内，并且膜沉积温度在200至750℃的范围内。所述膜可以通过各种已知技术中的任何一种进行沉积，包括但不限于溅射沉积、等离子体增强化学气相沉积(PECVD)、快速热化学气相沉积(RTCVD)、或标准的化学气相沉积(CVD)技术。该SiO2膜5的目的是作为下一步将要沉积的第二膜的蚀刻停止物(etch stop)。因此，衬层或蚀刻停止层5不必是SiO2，而可以是能够为直接沉积在衬材料层5之上的下一膜提供足够的蚀刻停止能力的任何材料。
沉积衬层或蚀刻停止层5之后，压力膜(compressive film)6沉积在整个晶片之上，如图6和图7所示。在优选实施例中，压力膜6是通过例如PECVD沉积的SiN膜。膜6也可以400W至1500W范围内的高功率沉积，从而在膜中产生更多压应力。可以使用低沉积速率和温度范围来沉积所述膜，从而使该膜有压应力。理想地，膜中的压应力在-300MPa至-3000MPa的范围内并且膜厚度应该在200至2000的范围内。优选的沉积参数如下：480℃的工艺温度，5.75torr的压力，晶片与电极之间间隔395mil，流量为3000sccm的2％稀释SiH4气体、15sccm NH3气体及1060sccm N气体，使用900瓦的RF功率。这个工艺产生大约15.95/s的沉积速率及大约(±10％)-1400MPa的膜应力。
在压力膜6涂敷于晶片后，利用阻挡掩模7来遮蔽晶片的pFET区域，如图8和图9所示。该阻挡掩模可以通过本领域已知的常规光刻技术形成。该掩模通过常规光刻过程形成，其中光敏材料涂覆在晶片表面之上并通过掩模暴露。然后，将光敏材料显影，在晶片上留下阻挡pFET区域的抗蚀剂图像或特征图案。
形成阻挡掩模7之后，用已知的能够相对于阻挡掩模材料选择性地去除压力膜的湿蚀刻或干蚀刻技术去除压力膜6。如果压力膜是SiN，那么由CH2F2构成的等离子体是可用于此目的的干蚀刻化学制品的一个例子。在压力膜从晶片上的nFET区域去除之后，中间结构显现出来，如图10和图11所示。
发明性工艺流程进行到这点，使用本领域已知的溶剂或O2等离子体工艺从晶片去除阻挡掩模7，从而去除抗蚀剂或有机材料。然后，在整个晶片上沉积第二衬或蚀刻停止材料8，如图12或13所示。第二衬层8至少具有与前面描述的第一衬类似的特性。即，该衬将被用作后续膜蚀刻工艺的蚀刻停止物。
然后，张力膜9沉积在整个晶片之上，如图14和图15所示。张力膜为例如SiN，并且通过例如CVD、PECVD、RTCVD或能够沉积高度张力膜的任何其它沉积技术沉积。膜厚度应该在200至2000的范围内，并且应力应该在+200MPa至+2000MPa或更大张力的范围。优选的沉积参数是：480℃的工艺温度，6.25torr的压力，晶片与电极之间间隔490mil，流量为3000sccm的2％稀释SiH4气体、15sccm的NH3气体及1060sccm的N气体，使用340瓦的RF功率。这种工艺产生大约23/s的沉积速率及大约500MPa的膜应力。
发明性的工艺流程进行到这点，在晶片的nFET区域之上构图阻挡掩模10，如图16所示。此阻挡掩模的特性与前面描述的阻挡pFET区域的阻挡掩模的特性类似。在界定阻挡掩模之后，执行已知的湿或干蚀刻过程，从而从pFET区域去除张力膜9。该蚀刻对衬蚀刻停止材料8应该是选择性的。这样，用于从nFET区域去除张力膜的蚀刻不去除pFET区域上的压力膜。然后，使用与用于去除第一阻挡掩模相类似的方法来去除阻挡掩模，得到图17示出的最终器件结构200、300。
发明性工艺流程进行到这点，将50至500厚的具有-100MPa压力至+100MPa张力范围的低应力的薄膜(未示出)涂敷到晶片，从而用作阻挡层。此薄膜的目的是填充未被压力或张力薄覆盖的任何区域。该可选的膜可用于改善抑制进入到Si中的污染物，并且还有助于改善用于源极-漏极接触蚀刻的蚀刻停止特性。
在上面描述的操作被执行之后，可以使用本领域熟知的标准工艺方法(未示出)继续进行CMOS工艺。更具体地，后续处理包括：沉积和平坦化玻璃层(即BPSG、TEOS)；蚀刻源极/漏极接触，接触冶金沉积和平坦化；然后形成附加级的绝缘层、通孔和连线从而完成芯片。
出现于鳍的纵向侧壁上的应力膜叠在栅极导体上，在沟道中产生与膜中应力相同类型的应力(即压力/压力，张力/张力)。鳍的纵向侧壁上的源极/漏极区域中的应力是相反类型(即压力/张力，张力/压力)。为了进入源极/漏极扩散区，每个鳍顶表面上的膜可以被去除而不会消除纵向侧壁上的膜的效用。
尽管已经示出并描述了目前认为是优选的本发明的实施例，但本领域的技术人员应理解，在不偏离本发明的精神和范围的前提下，可对其做出各种改动和变形。
工业适用性
本发明适用于微电子半导体器件。

Claims (17)

1.一种半导体器件结构，包括：
设置在衬底(1，2)上的PMOS器件(200)和NMOS器件(300)，
所述PMOS器件(200)包括对所述PMOS器件的有源区(3)施加应力的压力层(6)，
所述NMOS器件(300)包括对所述NMOS器件的有源区(3)施加应力的张力层(9)，其中
所述压力层包括第一电介质材料(6)，所述张力层包括第二电介质材料(9)，并且所述PMOS和NMOS器件是FinFET器件(200，300)。
2.如权利要求1所述的半导体器件结构，其中所述第一电介质材料包括SiN。
3.如权利要求1所述的半导体器件结构，其中所述第二电介质材料包括SiN。
4.如权利要求1所述的半导体器件结构，其中所述第一电介质材料具有在-300MPa至-3000MPa范围内的基本均匀的压应力。
5.如权利要求1所述的半导体器件结构，其中所述第一电介质材料具有在200至2000范围内的基本均匀的厚度。
6.如权利要求1所述的半导体器件结构，其中所述第二电介质材料具有在+200MPa至+2000MPa范围内的基本均匀的张应力。
7.如权利要求1所述的半导体器件结构，其中所述第二电介质材料具有在200至2000范围内的基本均匀的厚度。
8.如权利要求1所述的半导体器件结构，其中所述第一电介质材料及第二电介质材料是SiN。
9.一种用于制造半导体器件结构的方法，包括：
在同一衬底(1，2)上设置p-FinFET器件区域(200)及n-FinFET器件区域(300)；
在所述p-FinFET器件区域及所述n-FinFET器件区域上设置第一衬(5)；
在所述第一衬上设置压力膜(6)；
在所述p-FinFET器件区域上设置第一掩模(7)；
从所述n-FinFET器件区域上去除所述压力膜；
去除所述第一掩模7；
在所述p-FinFET器件区域及所述n-FinFET器件区域上设置第二衬(8)；
在所述第二衬上设置张力膜(9)；
在所述n-FinFET器件区域上设置第二掩模(10)；
从所述p-FinFET器件区域上去除所述张力膜；及
然后去除所述第二掩模。
10.如权利要求9所述的方法，其中设置压力膜的所述步骤包括沉积具有大约-1400MPa的膜应力的压力膜。
11.如权利要求9所述的方法，其中设置张力膜的所述步骤包括沉积具有大约+500MPa的膜应力的张力膜。
12.如权利要求9所述的方法，其中所述压力膜是SiN。
13.如权利要求9所述的方法，其中所述张力膜是SiN。
14.如权利要求9所述的方法，其中所述压力膜设置为具有在200至2000范围内的基本均匀的厚度。
15.如权利要求9所述的方法，其中所述张力膜设置为具有在200至2000范围内的基本均匀的厚度。
16.如权利要求9所述的方法，其中设置压力膜的所述步骤包括沉积具有大于约-1400MPa的膜应力的压力膜。
17.如权利要求9所述的方法，其中设置张力膜的所述步骤包括沉积具有大于约+500MPa的膜应力的张力膜。
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CN104347508B (zh) * 2013-07-24 2017-05-17 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN104347508A (zh) * 2013-07-24 2015-02-11 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN104752221A (zh) * 2013-12-31 2015-07-01 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN104752221B (zh) * 2013-12-31 2017-11-03 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN104916539A (zh) * 2014-03-12 2015-09-16 中芯国际集成电路制造(上海)有限公司 一种制作半导体器件的方法
CN106206577A (zh) * 2015-01-16 2016-12-07 台湾积体电路制造股份有限公司 用于FinFET器件的方法和结构
CN106206577B (zh) * 2015-01-16 2019-04-23 台湾积体电路制造股份有限公司 用于FinFET器件的方法和结构
CN107251204A (zh) * 2015-02-24 2017-10-13 国际商业机器公司 用于电子和空穴迁移率增强的双鳍集成
CN106505040A (zh) * 2015-09-07 2017-03-15 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN106505040B (zh) * 2015-09-07 2020-02-11 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN106910739A (zh) * 2015-12-21 2017-06-30 三星电子株式会社 半导体器件

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AU2002368388A1 (en) 2004-06-18
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TW200425508A (en) 2004-11-16
JP2006507681A (ja) 2006-03-02
WO2004049406A1 (en) 2004-06-10
DE60223419D1 (de) 2007-12-20
EP1565931B1 (en) 2007-11-07
DE60223419T2 (de) 2008-09-04
EP1565931A1 (en) 2005-08-24
CN100378901C (zh) 2008-04-02
JP4384988B2 (ja) 2009-12-16

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