TWI233694B - Strained FinFET CMOS device structures - Google Patents

Strained FinFET CMOS device structures Download PDF

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TWI233694B
TWI233694B TW092133040A TW92133040A TWI233694B TW I233694 B TWI233694 B TW I233694B TW 092133040 A TW092133040 A TW 092133040A TW 92133040 A TW92133040 A TW 92133040A TW I233694 B TWI233694 B TW I233694B
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Bruce B Doris
Dureseti Chidambarrao
Meikei Ieong
Jack A Mandelman
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1233694 玖、發明說明： 【發明所屬之技術領域】 本發明是有關於雙閘極半導體裝置結構，尤其是鰭式場 效電晶體（FinFET)裝置。 曰 【先前技術】 雙閘極半導體裝置結構是下個世代微電子裝置的熱門人 選’因為有能力得到接近理想化的次臨界斜率、沒有本體 效應、不受短通道效應影響、很高的電流驅動力。鰭式場 效電晶體（FinFET)是一種雙閘極半導體裝置結構的相關技 術。與其它雙閘極裝置比較起來，該FinFE丁因為有非常簡 單的製程而尤其吸引人。FinFET的通道是Si的薄狀矩形孤 島’一般稱作鰭狀物（Fin)。閘極繞著該鰭狀物包起來，使 得該通道在鰭狀物結構之垂直部分的二側上被攔截下來， 提供優於平面單一閘極MOSFET(金氧半場效電晶體）的閘 極控制。
FinFET是眾所週知的。例如，見美國專利編號第6,413,8〇2 案，標題為丨’FinFET Transistor Structure Having a Double
Gate Channel Extending Vertically from a Substrate and
Method of Manufacture”，由 Hu 等人在 2000 年 10 月 23 曰提出 專利申請而於2002年6月2日取得專利，其内容在此合併到 本案中當作參考。FinFET具有強化的游動率也是眾所週知 的。例如，見美國專利申請序號第2002/0063292 A1案，標 題為 ’’CMOS Fabrication Process Utilizing Special Transistor Orientation1’，由Armstrong等人在2000年11月29曰提出專利
O:\89\89454 DOC 1233694 申請而於2002年5月30日公告，其内容在此合併到本案中當 作參考。該習用技術的方法是要改善nFET的游動率，並口 需要一種方法來改善相 能有限度的改善CMOS電路。因此 同晶圓上的p-FinFET與n-FinFET的游動率。 然而本發明人相信，對於改善使用應力層以加強游動率 是可以達成的。 【發明内容】 依據本發明，半導體裝置結構包括一 PM〇S裝置與一 NMOS裝置，都是被安置在基板上，該pivl〇s裝置包括一壓 細層’對PMOS裝置的主動區施加應力，而nm〇s裝置包括 伸展層，對NMOS裝置的主動區施加應力，其中該壓縮層 包括一第一介電材料，該伸展層包括一第二介電材料，而 且PMOS裝置與NMOS裝置都是鰭式場效電晶體（FinFE丁）裝 置。 本發明是一種給加強游動率用的新式應變FinFET裝置結 構。該整合設計結合了 一種新的處理流程，會在卜FinFET 的縱軸方向上感應出壓縮應力，也會在n_FinFE 丁的縱軸方 向上感應出拉伸應力。這些應力會大幅的加強游動率，並 因而加強裝置性能。在此所說明的本發明中，通道中所感 應出的縱軸應力會從標準平面MOSFET中被大幅的加強，因 為是從薄FinFET的二側塗佈上的應力薄膜，而非在S0I層或 本體基板的表面上。 本發明的主要目的在於加強雙閘極CMOS裝置結構的游 動率。
O:\89\89454.DOC 1233694 處理’以去除掉鰭狀物餘刻處理中的任何审 離子佈植是用來％ r f. 、仅。如果位阱 層可裝置的臨界電壓時，犧牲氡化 道現象師…以避免在進行位牌離子佈植時發生通 犧牲氡化物是藉乾式或濕式钱刻化學去除掉。例如 2 =稀釋氫氟酸來去除掉犧牲氧化物。在犧牲氧化物被 ::’可以形成閘極介電層。該閘極氧化可以是熱 、，氮化Si02或氧氮化物。該閘極介電層可以是高κ值 材料，比如Ta05、Hf02、或任何其它間極介電材料。 接著閘極材料被沉積在整個晶圓上，之後進行微影與钱 刻處理。閘極在圖式中是標示成電極4。 形成閘極後，可以使m技術中已知的再氧化操作來 改善問極介電質的特性。也可省去該間極再氧化處理。 、、此時的處理流程中，可以用另一方式而離子佈植出源極/ 、極I伸而且可以使用偏移間隔層來產生閘極邊緣與離 子佈植鰭狀物區之間的距離。如同在傳統CM〇S處理技術中 斤/、通的，可以使用微影光罩來讓1117£丁區免被離子佈植， 、讓pFET區被離子佈植。可以使用類似的操作來對丁 區進行離子佈植，而讓pFET區免被離子佈植。 在形成源極/汲極延伸後，可以使用延伸退火處理來修復 口離子佈植所造成的損壞。接著，藉沉積出ιοοΑ至1〇〇〇A 範圍内的SiN薄膜，而製造出深的源極汲極間隔層，之後進 行阿度方向性蝕刻，以便從水平表面上去除掉siN薄膜，而 在閘極的垂直部分上留下該薄膜。
〇 \89\89454.DOC 1233694 膜具有壓縮性。理想上，薄膜中的壓縮性是在-3〇〇 MPa至 -3〇〇請1^的範圍0，而且薄膜厚度必須是在2 —至2〇〇从 的靶圍内。較佳的沉積參數如下：處理溫度48〇。〇,壓力5乃 加，晶圓與電極間之間距395如卜流率3〇〇〇scc_2_ 釋SiH4氣體’流率15sccm的而3氣體，流率⑶⑼咖_ 氣體，使用900瓦的RF電力。該處理會產生約i5 95A/s的沉 積速率以及約的薄膜應力。 在壓縮薄膜6被加到晶圓後，使用如圖8與圖9中所示的阻 擋光罩7,遮蔽到晶圓的pFET區上。可以藉已知習用技術中 的傳統微影姓刻技術來形成阻撞光罩。藉傳統微影製程形 成先罩，其中光敏材料是被塗佈到晶圓表面上’並經由光 =曝先。然後對該光敏材料進行顯影處理，留下光阻影像 或阻擋晶圓上pFET區的特性。 光罩7後’藉已知的滿式姓刻或乾式姓刻技術去 二=溥膜6’能相對於阻擔光罩材料選擇性的去除掉該 “。専膜。如果該壓縮薄膜是_，則由 漿便是可以給該目的用之乾式蝕一2 2 、电 上的霜區中去除掉 ：例。從晶圓 圖顺圖Μ所示。 、後t顯不出中間結構，如 此時的處理流程中，使 理，阻浐光 a 知技術中的溶劑或02電漿處 丨且桉先罩7會從晶圓上被去 材料。接著，第二去除掉光阻或有機 沉積出來，如圖12與圖13所示:第二=在整個晶圓上 述第-内概層的類似特性。亦即第;;内襯層8具有至少如前 °亥内襯層是要用來當作
O:\89\89454.DOC 1233694 給後績薄膜 ί虫刻處理用的敍刻阻止居。 接著，在整個晶圓上沉積出拉伸薄膜9,如圖14與圖15 中所示。例如’拉伸薄膜是SiN ’並且是藉例如cvd、 PECVD、RTCVD或任何其它能沉積出高度拉伸薄膜的沉積 技術而沉積出來。薄膜厚度必須是在200人至2000入的範圍 内，並且應力必須是在+200河匕至+2000 MPa的範圍内或 是更大的拉伸。較佳的沉積參數是： 處理脈度48G C ’壓力6.25 toir，晶圓與電極間之間距49〇 mil，流率3000 “⑽的2%稀釋SiH4氣體，流率15 “㈣的n出 氣體與流率106〇SCCm的！^氣體，使用34〇瓦的1^電力。該 處理會產生約23A/s的沉積速率以及約5〇〇 Mpa的薄膜應 η 〇 … 此時的處理流程中，阻擋光罩10是在晶源的nFET區上被 定義出圖t，如圖16所示。該阻擋光罩的特性是類似於先 前所述阻擔PFET區之阻擋光罩的特性。在定義出阻擋光罩 後進行已知的濕式或乾式蝕刻處理，以便從pFET區去除 掉拉伸薄膜9。该蝕刻處理必須對内襯蝕刻阻止材料8具有 遥擇性。以這種方式，用來從11]?]£丁區上去除掉拉伸薄膜的 蝕刻處理並不會去除掉奸£丁區上的壓縮薄膜。接著使用去 除掉第一阻擋光罩的類似方法來去除掉該阻擋光罩，造成 最終的裝置結構200、3 00，如圖π所示。 此時的處理流程中，可以將具]〇〇 Mpa壓縮至+1〇〇 Mb 拉伸乾圍内之低應力且5〇A至5〇〇A範圍内的薄膜（未顯示） 塗佈到晶圓上，充當阻障層用。該薄膜的目的是要填滿任
O:\89\89454.DOC -12- 1233694 何未被壓縮薄膜或拉伸薄膜所覆蓋的區域。該可選擇的薄 膜可以用來改善壓制污染貫穿到Si内，並幫助改善姓刻^ 止特性給源極-汲極接觸蝕刻處理用。 在進行上述的操作之後，可以使用習用技術中的已知標 準處理方法（未顯示）來繼續CM0S處理。特別是，緊接著的 處理包括：玻璃層（比如BPSG、TE0S)的沉積與平坦化；源 極/汲極接觸的蝕刻處理，接觸冶金的沉積以及平坦化；然 後形成絕緣層、接觸孔以及接線的額外高度，以完成該晶 片0 在鰭狀物縱軸側壁上出現的應力薄膜，會覆蓋住閘極導 線，而在通道内造成應力，是屬於薄膜（亦即壓縮/壓縮、拉 伸/拉伸)内應力的同一型式。在鰭狀物縱軸側壁上的源極/ 及極内之應力是屬於相反的型式（亦即壓縮/拉伸、拉伸/壓 縮）°為了利用源極μ極擴散，每㈣狀物頂部表面上的薄 膜都可以去除掉，而不會影響到縱軸側壁上薄膜的效應。 雖然已經顯示出並說明本發明的較佳實施例，但是很明 顯的’對於熟知該技術領域的人士來說，可以在不偏離本 發明的精神與範圍内做不同的改變與修改。 工業應用性 本發明可以應用到微電子半導體裝置上。 【圖式簡單說明】 圖1與圖2是以示意圖方式顯示出依據習用技術之FinFET 胃於鰭狀物）與平行（相肖於鰭狀物）觀視圖。 圖）疋以不思圖方式顯示出依據習用技術之⑽而半導
OA89\89454.DOC -13 -

Claims (1)

1233694 拾、申請專利範圍： 1 · 一種半導體裝置結構，其係包括： 安置在一基板1、2上之一 PMOS裝置200與一 NMOS裝 置 300， 該PMOS裝置200包括會對該PMOS裝置的主動區3施 以應力之一壓縮層6， 該NMOS裝置300包括會對該NMOS裝置的主動區3施 以應力之一拉伸層9，其中 該壓縮層包括一介電材料6，該拉伸層包括一第二介 電材料9，而且該PMOS裝置與NMOS裝置都是應變鰭式 場效電晶體（FinFET)裝置200、300。 2 ·如申凊專利範圍中第1項之半導體裝置結構，其中該第 一介電材料包括SiN。 3·如申請專利範圍中第1項之半導體裝置結構，其中該第 二介電材料包括SiN。 4. 如申請專利範圍中第1項之半導體裝置結構，其中該第 一介電材料具有在-300 MPa至-3000 MPa範圍内基本上 均一性的壓縮應力。 5. 如申請專利範圍中第1項之半導體裝置結構，其中該第 一介電材料具有在200A至2000A範圍内基本上均一性 的厚度。 6. 如申請專利範圍中第1項之半導體裝置結構，其中該第 一介電材料具有在+200 MPa至+2000 MPa範圍内基本 上均一性的拉伸應力。 O:\89\89454.DOC 1233694 .如申凊專利範圍中第1項之半導體裝置結構，其中該第 一介電材料具有在200A至2000A範圍内基本上均一性 的厚度。 δ·如申請專利範圍中第i項之半導體裝置結構，其中該第 介電材料與第二介電材料是s iN。 9· 一種製造半導體裝置結構的方法，其係包括： 在相同基板1、2上，提供一 p-FinFET裝置區200與 一 n-FinFET裝置區 300 ; 在。亥p-FinFE丁裝置區與η·ρίηρΕΤ裝置區上沉積一第 一内襯層5 ; 在該第一内襯層上沉積一壓縮薄膜6 ; 在該p-FinFET裝置區上沉積一第一光罩7 ; 從該n-FinFET裝置區上去除該壓縮薄膜； 去除該第一光罩7; 在该ρ-FmFET裝置區與n-FinFET裝置區上沉積一第 二内襯層8 ; 在δ玄第一内概層上沉積一拉伸薄膜9 ; 在δ亥n-FinFET裝置區上沉積一第二光罩1〇 ; 從S p-FinFET裝置區上去除該拉伸薄膜；以及 接著去除該第二光罩。 10·如申請專利範圍中第9項之方法， 其中該沉積一壓縮薄膜的步驟包括沉積一具有約 -1400 MPa薄膜應力的壓縮薄膜。 Π ·如申請專利範圍中第9項之方法， O:\89\89454.DOC -2 - 1233694 其中该沉積一拉伸薄膜的步驟包括沉積一具有約 + 5 00 MPa薄膜應力的拉伸薄膜。 12.如申請專利範圍中第9項之方法，其中該壓縮薄膜是 SiN 〇 13·如申請專利範圍中第9項之方法，其中該拉伸薄膜是 SiN。 1 4.如申請專利範圍中第9項之方法， 其中違壓縮薄膜是沉積成具有在2〇〇a至2000A範圍 内基本上均一性的厚度。 1 5 ·如申請專利範圍中第9項之方法， 其中忒拉伸薄膜是沉積成具有在2〇〇入至⑼人範圍 内基本上均一性的厚度。 1 6 ·如申凊專利範圍中第9項之方法， 其中該沉積一壓縮薄膜的步驟包括沉積一具有比約 -1400 MPa還大之薄膜應力的壓縮薄膜。 1 7·如申請專利範圍中第9項之方法， 其中該沉積-拉伸薄膜的步驟包括沉積一具有比約 + 5〇〇MPa還大之薄膜應力的拉伸薄膜。 O:\89\89454.DOC I23 3套^^13綱。號專利申請案 中文說明書替換頁(93年12月） 衫丰㈣為修止 本發明的另一目的在於加強FinFET裝置結構的游動率。~T 本發明的進一步目的在於改善製造應變FinFET裝置結構 · 的方法。 本發明以及其它目的與特點從結合底下圖式的詳細說明 中都會更加明顯。 【實施方式】 本發明是一種新式FinFET半導體裝置結構以及一種製造
該結構的方法。依據本發明的較佳最終結構是顯示於圖 16、17 中。 現在參閱其它的圖式以及尤其是圖1-3,顯示出已知的 FinFET裝置（圖1、2)與裝置結構（圖3)。 一開始，標準或傳統FinFET裝置的製程是對Fin定義出圖 案並進行蝕刻、形成閘極介電層與導線、側壁間隔層（未顯 示）、源極/汲極摻雜處理、以及金屬矽化物處理。緊接在金 屬矽化物處理後，去除掉閘極側壁間隔層，以方便從依據 本發明續狀物中感應出應變的處理。 尤其如參閱圖3所說明的，例如，s〇I晶圓。該s〇i晶圓包 括一基板卜該基板1是被安置在埋植以〇2層2的底下，如圖 3所示。絕緣體上矽（801)層在埋植以〇2層2的頂部上，該s〇i 層被定義出圖案成數個區域，該等區域會形成每個裝置的 主動區’如圖卜2、3中的鰭狀物3。可以藉習用技術中已 知的標準微影與蝕刻操作來形成鰭狀物。另一方式是，可 :使用已知的側壁影像轉移方法形成每個鰭狀物:。：二 箭頭3 3 2標示電流方向之一縱方向。 在鰭狀物形成後 可以進行習 用技術中已知的犧牲氧化 O:\89\89454-931222.DOC 於年p片 >)日卜:止 補充 侧號專利 申請案 中文說明書替換頁(93年12月） 現在使用阻擋光罩與離子佈植，形成源極與汲極區給 nFET裝置區30以及PFET裝置區20用，如同CMOS處理技術 中的標準。接著進行傳統的快速熱退火處理，以啟動由離 子佈植所形成之接面。之後，進行傳統的金屬矽化物處理， 該金屬矽化物處理是使用CoSb、TiSi、NiSi或任何其它習 用技術中的已知矽化物。 此時的處理流程中，開始進行獨創性的步驟與結構（圖 4-17)，以改善nFET區130上nFET以及PFET區120上pFET的 裝置性能。首先，如圖4與圖5中所示，比如藉低溫沉積技 術來安置（比如沉積）Si〇2内襯層（薄膜）5。該薄膜的厚度是 在25-300A範圍内，而且該薄膜沉積溫度是在2〇〇_75〇<>c的 範圍内。可以藉不同已知技術的其中一種來沉積出該薄 膜，包括濺鍍沉積、電漿強化化學氣相沉積（pECVD)、快 速熱化學氣相沉積（RTCVD)、或標準化學氣相沉積（cvd) 技術，但並不受限於此。該Si〇2薄膜5的目的是要當作給第 二薄膜用的㈣阻止層，該第二薄膜接著會被沉積出來。 因此，内襯層或蝕刻阻止層5都必須是以〇2，但是也可以是 任何能提供足夠蝕刻阻能力給下個薄臈用的材料，該下個 薄膜是直接沉積在内襯材料層5的頂部上。另外，需1責： 箭頭432係標示電流方向之一縱方向。 — 在沉積出⑽或钕刻阻止層5後，如圖6與圖7中所示的產 縮薄膜6會在整個晶圓表面上沉積出來。在較佳實施例中， 壓縮溥膜6是藉比如叩⑽所沉積出來的_薄膜。|縮薄 膜6也可以在彻WWW範圍内的高功率下沉㈣來 可以使用低沉積速率與溫度範圍來沉積出該薄膜， O:\89\89454-931222.DOC • 10 - 123^和33040號專利申請案 ί .......................-- -D 中文說明書替換頁(93年12月） 丨於。|) ;5»〆十丄;叫 體裝置結構的垂直觀視圖。 L——-:二:上J .圖4顯示依據本發明-製造步驟之-垂直視圖，其中一 Si〇2内觀層係被沈積。 圖5顯示依據本發明圖4製造步驟之一平行視圖。 圖6顯示依據本發明-後續製造步驟之-垂直視圖，其中 一壓縮薄膜係被沈積。 圖7顯示依據本發明圖6製造步驟之一平行視圖。 圖8顯示依據本發明-後續製造步驟之一垂直視圖，其中 一阻擋光罩係被塗佈。 圖9頒示依據本發明圖8製造步驟之一平行視圖。 圖10顯示依棣本發明一後續製造步驟之一垂直視圖，其 中壓縮薄膜係自nFET區中除掉。 圖Π顯示依據本發明圖1〇製造步驟之一平行視圖。 圖12顯示依據本發明一後續製造步驟之一垂直視圖，其 中阻擋光罩係被除掉，且一第二内襯層係被沈積。 圖13顯示依據本發明圖12製造步驟之一平行視圖。 圖14顯示依據本發明一後續製造步驟之一垂直視圖，其 中一拉伸薄膜係被沈積。 圖15顯示依據本發明圖14製造步驟之一平行視圖。 圖16顯示依據本發明一後續製造步驟之一垂直視圖，其 中阻擔光罩係被塗佈，且拉伸薄膜係自pFET區中被除掉。 一圖17顯示依據本發明圖16製造步驟之一平行視圖，其中 i擔光罩係被塗佈’拉伸薄膜係|pFET區中被除掉，阻 擋光罩係被除掉，且最終裝置結構係被顯示。 O:\89\89454-931222.DOC -14- 德.ΓΡ 恢：广 1233|^433〇4〇號專利申請案 中文說明書替換頁(93年12月） 【圖式代表符號說明 1 基板 2 Si02 層 3 II狀物 4 電極 5 第一内襯層（薄膜） 6 壓縮層（薄膜）
7 阻擋光罩 8 第二内襯層 9 伸展層（薄膜） 20 pFET裝置區 30 nFET裝置區 200 PMOS 裝置 300 NMOS 裝置
O:\89\89454-931222.DOC -15-
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