JP5285947B2 - 半導体装置、およびその製造方法 - Google Patents
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Description
Jack Kavalieros et al., "Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering", [online] Intel Corporation, June 2006, [retrieved on 2008-01-28], Retrieved from the Internet: <URL: http://download.intel.com/technology/silicon/tri-gate_foils_VLSI_0606.pdf>.
(半導体装置の構成)
図1は、本発明の第1の実施の形態に係る半導体装置の斜視図である。また、図2(a)は、図1の切断線II−IIにおける断面を矢印の方向に見た断面図である。また、図2(b)は、図2(a)の部分拡大図である。
図3A(a)〜(c)、図3B(d)〜(f)は、本発明の第1の実施の形態に係る半導体装置の製造工程を示す斜視図である。
本発明の第1の実施の形態によれば、膨張膜7を形成することにより、フィン4内のチャネル領域に直接外力を加えて、チャネル領域にフィン4の高さ方向の圧縮歪みを発生させることができる。これにより、チャネル領域中の電子の移動度が向上し、それに伴ってn型トランジスタ1の動作速度が向上する。
本発明の第2の実施の形態は、p型トランジスタの動作速度を向上させる点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略する。
図5(a)は、本発明の第2の実施の形態に係る半導体装置の断面図である。また、図5(b)は、図5(a)の部分拡大図である。なお、図5(a)、(b)に示される断面は、図2(a)、(b)に示される第1の実施の形態に係る半導体装置の断面に対応する。
まず、図3B(e)に示した上面にゲートキャップ層12を有するゲート電極5を形成し、ゲート絶縁膜6のゲート電極5に接していない部分を除去するまでの工程を第1の実施の形態と同様に行う。ただし、第1の実施の形態における第1の膜10の代わりに、収縮膜13の前駆体膜を形成する。
本発明の第2の実施の形態によれば、収縮膜13を形成することにより、フィン4内のチャネル領域に直接外力を加えて、チャネル領域にフィン4の高さ方向の伸張歪みを発生させることができる。これにより、チャネル領域中の電子の移動度が向上し、それに伴ってp型トランジスタ20の動作速度が向上する。
本発明の第3の実施の形態は、フィンの上下に膨張膜を形成する点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略する。
図6(a)は、本発明の第3の実施の形態に係る半導体装置の断面図である。また、図6(b)は、図6(a)の部分拡大図である。なお、図6(a)、(b)に示される断面は、図2(a)、(b)に示される第1の実施の形態に係る半導体装置の断面に対応する。
図7A(a)〜(c)、図7B(d)〜(f)は、本発明の第3の実施の形態に係る半導体装置の製造工程を示す斜視図である。
本発明の第3の実施の形態によれば、フィン14の上下にそれぞれ膨張膜7a、7bを形成することにより、フィン14内のチャネル領域に上下方向から直接外力を加えることができる。このため、本実施の形態におけるn型トランジスタ21のチャネル領域に発生するフィン14の高さ方向の圧縮歪みは、第1の実施の形態におけるn型トランジスタ1のチャネル領域に発生するフィン4の高さ方向の圧縮歪みよりも大きくなり、トランジスタの動作速度をより向上させることができる。
本発明は、上記各実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。
半導体基板上に、フィン、前記フィンに接続されたパッド、および前記フィンと前記パッドの上と下の少なくともいずれかに位置する所定の膜を形成する工程と、
前記所定の膜の前記フィンとの界面上および前記パッドとの界面の外側の一部上に位置する部分を膨張または収縮させ、前記フィンに前記フィンの高さ方向の歪みを与える工程と、
ゲート絶縁膜を介して前記フィンの両側面を挟むようにゲート電極を形成する工程と、
を含む半導体装置の製造方法。
Claims (5)
- 半導体基板上に、フィンおよび前記フィンの上と下の少なくともいずれかに位置する所定の膜を形成する工程と、
ゲート絶縁膜を介して前記フィンの両側面を挟むようにゲート電極を形成する工程と、
前記所定の膜を膨張または収縮させ、前記フィンの前記ゲート電極に挟まれた領域に位置するチャネル領域に、ソースおよびドレイン間の方向に直交する前記フィンの高さ方向の歪みを与える工程と、
を含む半導体装置の製造方法。 - 前記所定の膜はSi1−xGex(0<x≦1)結晶からなる膜であり、前記チャネル領域に前記フィンの高さ方向の歪みを与える工程において、酸化処理を施されることにより膨張して前記チャネル領域に前記フィンの高さ方向の圧縮歪みを与えることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記所定の膜はオゾンTEOS膜であり、前記チャネル領域に前記フィンの高さ方向の歪みを与える工程において、熱処理を施されることにより収縮して前記チャネル領域に前記フィンの高さ方向の伸張歪みを与えることを特徴とする請求項1に記載の半導体装置の製造方法。
- 半導体基板上に形成され、内部のチャネル領域において、ソースおよびドレイン間の方向に直交する高さ方向の歪みを有するフィンと、
前記フィンの前記チャネル領域が含まれる部分の両側面を挟むように形成されたゲート電極と、
前記フィンの前記チャネル領域が含まれる部分の上と下の少なくともいずれかに形成され、前記フィンの前記歪みを発生させる歪み付与膜と、
を有する半導体装置。 - 前記歪み付与膜は、前記フィンの前記チャネル領域に高さ方向の圧縮歪みを発生させるSiGe酸化膜またはGe酸化膜、または前記フィンの前記チャネル領域に高さ方向の伸張歪みを発生させるSi酸化膜であることを特徴とする請求項4に記載の半導体装置。
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