CN106298540A - 具有脱氧栅极堆叠件的多栅极场效应晶体管 - Google Patents

具有脱氧栅极堆叠件的多栅极场效应晶体管 Download PDF

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CN106298540A
CN106298540A CN201510781155.8A CN201510781155A CN106298540A CN 106298540 A CN106298540 A CN 106298540A CN 201510781155 A CN201510781155 A CN 201510781155A CN 106298540 A CN106298540 A CN 106298540A
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layer
silicon
gate dielectric
fin
metal
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CN106298540B (zh
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杨育佳
叶致锴
柯志欣
吴政宪
陈亮吟
于雄飞
陈燕铭
杨建伦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了一种方法，包括：在半导体鳍上形成硅覆盖层；在硅覆盖层上方形成界面层；在界面层上方形成高k栅极介电层；以及在高k栅极介电层上方形成脱氧金属层。然后，对硅覆盖层、界面层、高k栅极介电层、和脱氧金属层执行退火。填充金属沉积在高k栅极介电层上方。本发明还提供了一种具有脱氧栅极堆叠件的多栅极场效应晶体管。

Description

具有脱氧栅极堆叠件的多栅极场效应晶体管
技术领域
本发明一般地涉及半导体技术领域，更具体地，涉及半导体器件。
背景技术
随着场效应晶体管的栅极长度减小，诸如漏极端感应势垒降低的短沟道效应恶化并且断态漏电流增加。为了抑制短沟道效应并且为了降低断态漏电流，等效氧化硅厚度(EOT)需要按比例减小。对于栅极长度充分小于20nm的场效应晶体管，EOT需要减小到1nm之下。
因为栅极泄露电流密度需要保持抑制在某些限值内，所以通过将给定介电材料的物理厚度而减小的EOT增加了不期望的栅极泄露电流密度。通过采用具有更高的介电常数或k值的栅极介电层，栅极介电材料的物理厚度可以增加给定的栅极电容密度，并且可以有效地抑制栅极泄露电流密度。
通过金属栅电极预先地使用高k栅极介电层。互补金属氧化物半导体(CMOS)技术时代能够在控制短沟道效应的同时，进一步扩大晶体管栅极长度。通常用于工业中的高k值栅极介电层是k约为20或者更高的氧化铪(HfO2)。HfO2通常形成在包括SiO2的界面层上，其中，使用原子层沉积形成该界面层。还可以使用中间k值为大约10的硅酸铪(HfSixOy)。
包括界面层上的高k值栅极介电层的栅极介电堆叠件的总EOT等于高k栅极介电层的EOT和界面层的EOT的总和。为了减小栅极介电堆叠件的EOT，k值高于HfO2的k值的栅极介电材料(诸如k值大于25的氧化镧或者其他介电材料)可以用于栅极堆叠件。可选地，可以通过从该界面层中提取氧而减小或去除界面层的厚度。在用于减小EOT的其他方法中，可以增加界面层的介电常数。
在上述方法中，界面状态密度应该保持为低(优选地，接近或低于1011/cm2eV)，以防止沟道的载流子迁移率劣化，并且栅极堆叠件可靠性不应该恶化。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种方法，包括：在半导体鳍上形成硅覆盖层；在所述硅覆盖层上方形成界面层；在所述界面层上方形成高k栅极介电层；在所述高k栅极介电层上方形成脱氧金属层；对所述硅覆盖层、所述界面层、所述高k栅极介电层、和所述脱氧金属层执行退火；以及在所述高k栅极介电层上方沉积填充金属。
根据本发明的另一方面，提供了一种方法，包括：在硅锗鳍上形成晶体硅覆盖层；在所述晶体硅覆盖层上方形成氧化硅层；在所述氧化硅层上方形成高k栅极介电层；在所述高k栅极介电层上方形成脱氧金属层；从所述氧化硅层的底部提取氧，以将所述底部转换为硅层，其中所述硅层与所述晶体硅覆盖层连续地接合；以及在脱氧之后，在所述高k栅极介电层上方沉积填充金属。
根据本发明的又一方面，提供了一种方法，包括：在硅锗鳍的中间部分上形成伪栅极堆叠件；在所述硅锗鳍的相对侧形成源极/漏极区域；所述源极/漏极区域上方形成层间介电层，其中所述伪栅极堆叠件位于所述层间介电层中；去除所述伪栅极堆叠件以在所述层间介电层中形成凹槽；在所述凹槽中外延生长硅覆盖层，其中，所述硅覆盖层位于所述硅锗鳍上；在所述硅覆盖层上方沉积氧化硅层并且所述氧化硅层与所述硅覆盖层接触；在所述氧化硅层上方形成高k栅极介电层；在所述高k栅极介电层上方形成脱氧金属层，其中，脱氧金属层对于氧的第一亲和性高于高k金属栅极层中金属的第二亲和性和硅的第三亲和性；执行退火以至少从所述氧化硅层的底部提取氧，从而将所述底部转换为硅层；以及在所述退火之后，将金属填充在所述凹槽中。
附图说明
当结合附图进行阅读时，根据以下详细的描述来更好地理解本发明的各个方面。注意，根据工业的标准实践，各个部件没有按比例绘制。实际上，为了讨论的清楚，可以任意地增加或减小各个部件的尺寸。
图1A至图17C示出了根据一些实施例的鳍式场效应晶体管(FinFET)的形成的截面图。
图18和图19示出了根据一些实施例的具有纳米线的金属氧化物半导体场效应晶体管(MOSFET)的截面图。
图20示出了根据一些实施例的用于形成FinFET的工艺流程。
图21A至图21F示出了根据一些实施例的半导体鳍的形成的截面图。
图22A至图22G示出了根据一些实施例的半导体鳍的形成的截面图。
具体实施方式
以下公开内容提供了许多不同的用于实施本发明的不同特征的实施例或实例。以下描述部件或配置的具体实例以简本发明。当然，这些仅仅是实例而不用于限制。例如，在以下的描述中，在第二部件上方或之上形成第一部件可以包括第一部件和第二部件被形成为直接接触的实施例，并且也可以包括可以在第一部件和第二部件形成附件部件使得第一部件和第二部分没有直接接触的实施例。此外，本发明可以在各个实例中重复参考标号和/或字母。这些重复是为了简化和清楚，其本身并不表示所讨论的各个实施例和/或结构之间的关系。
此外，为了易于描述，可以使用空间相对术语(诸如“在…下方”、“之下”、“下部”、“上方”、“上部”等)以描述图中所示一个元件或部件与另一个元件或部件的关系。除图中所示的定向之外，空间相对术语还包括使用或操作中设备的不同定向。装置可以以其他方式定向(旋转90度或处于其他定向)，本文所使用的空间相对描述可因此进行类似的解释。
根据多个示例性实施例提供了通过脱氧形成鳍式场效应晶体管(FinFET)的方法。示出了形成FinFET的中间阶段。讨论了实施例的一些变形例。在各个附图和所有的示例性实施例中，相同的参考标号用于指定相同的元件。
图1A至图17C示出了根据一些实施例的形成FinFET的中间阶段的截面图和透视图。图1A至图17C中所示的步骤还示例性地示出了图20所示的工艺流程200。在随后的讨论过程中，参照图20的工艺步骤讨论了图1A至图17C所示的工艺步骤。
图1A和图1B分别示出了集成电路结构的截面图和透视图。图1A示出了单个半导体鳍(在如图1B所示的多个鳍22中)的截面图。半导体鳍22形成在半导体衬底20上方，该半导体鳍可以为晶圆的一部分。根据本发明的一些实施例，衬底20为半导体衬底，该衬底还可以是硅衬底、松弛的硅碳衬底、松弛的硅锗衬底、绝缘体上硅衬底或者由其他半导体材料所形成的衬底。衬底20可以轻掺杂有p型或n型掺杂物。
半导体鳍22凸起到附近的隔离区域24的顶面上方，该隔离区域可以是浅沟槽隔离(STI)区域。根据一些实施例，半导体鳍22是硅锗鳍，其中硅锗表达为Si1-xGex，其中的值x为锗的摩尔分数(或者原子百分比)。锗百分比x可以高于约0.2，高于0.4、高于0.6，或者与1一样高。当锗百分数x为1时，半导体鳍22为没有硅的锗鳍。半导体鳍22的间距(图1B)可以小于30nm，小于24nm，甚至小于15nm。顶部鳍宽度W1可以小于10nm，小于约8nm，或者甚至小于约6nm。鳍高度H1可以大于30nm，或者大于约60nm。鳍高度H1为鳍22的顶面和隔离区域24的顶面之间的垂直位移。底部鳍宽度W2可以等于或略大于顶面鳍宽度W1。半导体鳍22的侧壁是基本笔直的并且基本竖直的。
隔离区域24形成为邻近半导体鳍22。根据本发明的一些实施例，隔离区域24由氧化硅形成，并且可以使用化学汽相沉积(CVD)进行沉积。在形成半导体鳍22的硅锗和下面的衬底20之间的界面可以与隔离区域的表面之间具有偏移。作为实例，偏移OS在约-10nm(当界面高于隔离区域24的顶面时)和约10nm(当界面低于隔离区域24的顶面时)之间的范围内。
根据本发明的一些实施例，松弛的或部分松弛的硅锗层26形成为衬底20的顶部。例如，图1A示例性地示出了Si1-yGey层26。锗百分比y小于鳍Si1-xGex 22的锗百分比。通过将x选择为大于y，Si1-xGex鳍22(其形成生成的FinFET的沟道)的自然晶格常数大于Si1-yGey层26的自然晶格常数。因此，生成的FinFET的沟道(Si1-xGex)经受压缩应力或压应变。
Si1-xGex鳍22可以与硅鳍一起形成。图1B示出了与多个硅鳍23(没有锗)相邻的多个Si1-xGex鳍22，该多个硅鳍23形成在松弛或部分松弛的硅锗(Si1-yGey)层26上。SiGe鳍22和硅鳍23可以或者不可以具有相同的物理尺寸，诸如鳍宽度W1和W2和/或鳍高度H1(图1A)。根据本发明的一些实施例，Si1-xGex鳍22用于形成p沟道FinFET，同时硅鳍23用于形成n沟道FinFET。由于硅鳍23形成在完全或部分松弛的Si1-yGey层26上，所以硅鳍23经受沟道长度方向上的拉伸应力(应变)。存在沟道长度方向上的拉伸应力增加了硅的载流子迁移率，并且改善了驱动电流和n沟道FinFET的速度。
以下将简单描述用于形成Si1-xGex鳍22的示例性工艺。在图20所示的工艺流程中将相应的步骤示出为步骤202。图21A至图21F中示意性地示出了根据一些实施例的相应步骤。首先，如图21A所示，提供了半导体衬底20。半导体衬底20可以是硅衬底、松弛的SiGe衬底(或者硅衬底上方的松弛的SiGe层)或者由如上所述的其他材料形成。如图21B所示，STI区域24形成为延伸到半导体衬底20中。在相邻的STI区域24之间狭长地夹置衬底20的带。如图21C所示，衬底带可以通过蚀刻凹进，以生成凹槽25。凹槽25的底部可以高于STI区域24的底面。接下来，如图21D所示，通过外延在凹槽25(图21C)中选择性地生长半导体衬底22。当衬底20为SiGe衬底(或者包含松弛的SiGe层)时，半导体衬底22可以由硅形成，或者当衬底20为硅衬底时，该半导体衬底可以为Si1-xGex区域。STI区域24然后凹进以形成半导体鳍。例如，图21E示出了在由硅形成的衬底20上的SiGe鳍22，并且图21F示出了在包括SiGe的衬底20上的硅鳍23。
图22A至图22G示出了根据一些实施例的半导体鳍22A和22B的形成。参照图22A，提供了衬底20。衬底20可以为块状硅衬底，或者可以包括松弛的Si1-yGey层26。图22B示出了衬底20或者松弛的SiGe层26中的STI区域24的形成。接下来，如图22C所示，通过使衬底22或者SiGe层26的部分凹进来形成凹槽25A。参照图22D，通过外延在凹槽25A(图22C)中形成Si1-xGex区域22(示出为22A)，其中，锗原子百分比x大于锗原子百分比y。此外，在形成凹槽25A时，如图22E所示，同时形成凹槽25B。参照图22F，通过外延在凹槽25B中形成Si1-ZGeZ区域22(示出为22B)，其中，锗原子百分比z小于锗原子百分比y。在随后的步骤中，STI区域24(如图22D和22F所示)凹进，生成图22G所示的结构，其中，鳍22(包括22A和22B)形成在相同的衬底20上。
图1A和图1B还示出了在图21A至图21F以及图22A至22G所示的步骤中所形成结构。生成的STI区域的深度D1(图1A)在约200nn和约1000nm之间的范围内。
图2示出了SiGe鳍22的钝化。在图20中所示的工艺流程中将相应的步骤示出为步骤204。根据本发明的一些实施例，钝化包括鳍22上方沉积覆盖层28。覆盖层28延伸到SiGe鳍22的顶面和侧壁上并与SiGe鳍22的顶面和侧壁接触。覆盖层28在随后的工艺中防止SiGe鳍22的损害。覆盖层28可以形成在SiGe鳍22和硅鳍23(图1B)上，或者形成在SiGe鳍22上但不形成在硅鳍23上。
根据本发明的一些实施例，覆盖层28由晶体硅制成，并且可以使用甲硅烷(SiH4)、乙硅烷(Si2H6)、丙硅烷(Si3H8)或者诸如高阶硅烷的其他含硅前体通过低温外延形成在SiGe鳍22上方。含硅前体还可以包含氯，例如，SiH2Cl2。外延生长温度可以为高于室温(大约21℃)的升高温度。例如，温度可以为约500℃、425℃或者更低、甚至375℃或者更低。低生长温度在外延期间将锗分离的可能性最小化，其中，锗分离会导致不期望的锗覆盖层的形成。覆盖层28的厚度小于约1.5nm。
根据本发明的实施例，覆盖层28为通过CVD所沉积的非晶硅层。可以在约400℃或更小的温度下执行沉积。根据又一可选实施例，覆盖层28是由氧化硅(SiO2)或其他介电材料所形成的介电层。形成方法可以包括原子层沉积(ALD)。覆盖层28还可以包括III-V族化合物半导体层，诸如磷化铝铟(InAlP)或者磷化镓铟(InGaP)。应该理解，覆盖层28还可以包括多层或者在上述实施例中的材料的组合。例如，覆盖层28可以包括晶体硅上的非晶硅、晶体硅上的SiO2、或者晶体硅上非晶硅上的SiO2。
图3A和图3B分别示出了在形成伪栅极34的过程中的截面图和透视图。在图20所示的工艺流程中将相应的步骤示出为步骤206。根据一些实施例，伪栅极34包括鳍22和23(图3B)上方的伪栅极介电层30、伪栅极介电层30上方的伪栅电极32。伪栅极介电层30可以由氧化硅形成，并且伪栅电极32可以有多晶硅形成(多晶Si)。形成工艺可以包括伪栅极介电层30和伪栅电极32的沉积，并且平坦化，以使伪栅极32的顶面平齐。另外，伪栅极34可以包括硬掩模35，该伪栅极由氧化硅或氮化硅形成。然后执行光刻步骤，以图案化沉积的伪栅极介电层30、伪栅极32和硬掩模35。因此，生成了图2A和图2B所示的结构。
图4A、4B、5A和5B示出了源极和漏极区域的形成。在图20所示的工艺流程中将相应的步骤示出为步骤208。图4A和图4B分别为截面图和透视图。首先，栅极隔离件38形成在伪栅极34的侧壁上。形成工艺包括毯式沉积步骤和随后的干蚀刻工艺。栅极间隔件38可以包括氮化硅、碳化硅、氮氧化硅、氧化硅、它们的组合或者它们的多层。
在形成栅极间隔件38之后，暴露的鳍22通过蚀刻凹进，因此形成凹槽40。在图4A和图4B中还示出了生成的结构。接下来，如图5A和图5B所示，分别示出了形成源极/漏极区域42的截面图和透视图。根据本发明的一些实施例，源极/漏极区域42(p沟道FinFET的)的形成与n沟道FinFET的源极/漏极区域(未示出，与源极/漏极区域42类似)的形成分离。在源极/漏极区域42的外延过程中，随着外延的进行，可以原位掺杂p型掺杂物。在外延之后，可以(或者不可以)执行离子注入，以将p型掺杂剂或者其他接触电阻增强的物质(诸如，镱、铝、锡等)引入源极/漏极区域42。
类似地，在n沟道FinFET的源极/漏极区域的外延过程中，随着外延的进行，可以原位掺杂n型掺杂物。在外延之后，可以(或者不可以)执行离子注入，以将n型掺杂物或者其他接触电阻增强的物质(例如，镱、铝、锡等)引入n沟道FinFET的源极/漏极区域。
接下来，可以执行源极/漏极掺杂物激活退火，以采用快速热退火(RTA)、毫秒退火(MSA)、尖峰退火、激光退火(LSA)、或者其他退火技术。
图6A、6B、7A和7B示出了根据本发明的一些实施例的源极/漏极区域42和n沟道FinFET的源极/漏极区域的形成。除了在外延之后，鳍22和23减薄(如图6B所示)而不是完全被蚀刻之外，这些实施例类似于图4A、4B、5A和5B所示的实施例。在减薄工艺中，稍微横向蚀刻鳍22。例如，如果原始鳍宽度为6nm，鳍宽度在每侧减小约1nm至2nm。在鳍22和23减薄之后，执行源极/漏极外延工艺以完成源极/漏极42和n沟道FinFET的源极/漏极区域的形成，其中，工艺细节可以与参照图6A和图6B所讨论的相同。图7B示出了通过包含图7A中的线7B-7B的垂直面所获得的截面图。
根据一些实施例，如图8所示，形成主间隔件45。主间隔件45的形成可以包括形成一个或多个毯式介电层，诸如氧化硅、氮化硅等，并且蚀刻毯式介电层以去除介电层的水平部分。毯式介电层的剩余的垂直部分为主间隔件。
此外参照图8，沉积接触蚀刻停止层(CESL)46。CESL 46可以包括固有应力的幅值为1GPa或者更高的氮化硅(Si3N4)。根据本发明的一些实施例，还可以使用固有应力的幅值大于1GPa的其他介电材料。固有应力为用于p沟道FinFET的压缩应力和用于n沟道FinFET的拉伸应力。
接下来，形成层间介电层(ILD)50。形成工艺可以包括沉积可流动的CVD介电层，然后进行热固化或者紫外线辐射固化，使得形成二氧化硅(SiO2)。然后执行平坦化，以平坦化ILD 50的顶面。在图9中示出了生成结构。接下来，ILD 50稍微凹进，使得如图10所示，形成凹槽52。在随后的工艺步骤，沉积硬掩模54(图11)，然后，进行如图12A所示的平坦化步骤。硬掩模54可以包括氮化硅(Si3N4)，从而随后的工艺步骤中保护ILD 50和下面的结构。
图12B示出了图12A中的结构的一部分的透视图。如图12所示，通过伪栅极34来覆盖半导体鳍22。
图13A至图17C示出了替换栅极(或者RPG)工艺的截面图和透视图，其中，利用替换栅极来替换伪栅极34(图12A和图12B)。在随后的讨论过程中，作为实例，讨论p沟道FinFET的栅极替换。教导的概念可容易地应用于形成n沟道FinFET的替换栅极的形成。
图13A和图13B分别示出了在去除如图12A和图12B所示的伪栅极34时截面图和透视图。因此形成凹槽51。在图20所示的工艺流程中将相应的步骤示出为步骤210。首先，通过蚀刻去除伪栅电极32和伪栅极介电层30(图3A)。因此，暴露了如图3A所示的覆盖层28。在覆盖层28为晶体硅层的实施例中，覆盖层28可以被去除或者可以保持未被去除。在覆盖层28不是由晶体硅形成的实施例中，去除覆盖层28。在图20所示的工艺流程中将相应的步骤示出为步骤212。去除覆盖层28有利地去除覆盖层28中的任何污染物。
然后，外延生长晶体硅覆盖层56。在图20所示的工艺流程中将相应的步骤示出为步骤214。在图14中示出了示出有生成的覆盖层的生成结构，其中将硅覆盖层示出为59，该覆盖层可以仅包括晶体硅衬底28，仅包括晶体硅层56，或者晶体硅层28上的晶体硅层56。晶体硅层59的厚度在1原子层(约0.136nm)至约20原子层(约2.7nm)的范围内。根据一些示例性实施例，硅层59的厚度小于10个原子层的厚度(约1.36nm)。
在RPG工艺阶段中外延生长硅覆盖层59的一些实施例中，可以在SiGe鳍22(用于p沟道器件)以及硅鳍23(用于n沟道器件，图3B)上生长该硅覆盖层。可选地，可以在SiGe鳍22上生长硅覆盖层59，但不是在硅鳍23上生长该硅覆盖层，从而通过诸如SiO2的硬掩模来覆盖该硅鳍23，以防止覆盖层59外延形成在硅鳍23上方。
晶体硅层59具有以下有利特征：防止SiGe鳍22中的锗原子向外扩散到随后形成的高k介电材料中，以形成不期望的化合物。另外，晶体硅层59还防止锗与随后形成的界面层中的氧发生反应(诸如氧化硅)以形成不期望的氧化锗。然而，在角部57(图14)处的晶体硅层59可以比诸如晶体硅层59在其他位置处的垂直部分和水平部分更薄。这导致晶体硅层59的阻止能力折衷。图15A、15B和16示出了用于增加晶体硅在角部57处的厚度的脱氧工艺。
在形成如图14所示的结构之后，例如，使用稀释的HF溶液执行表面清洁。接下来，如图15A所示，界面层58形成在晶体硅层59上。在图20所示的工艺流程中将相应的步骤示出为步骤216。界面层58由氧化硅形成，从而通过等离子体增强的原子层沉积来形成该界面层。可选地，可以使用水蒸汽(H2O)或者O2通过CVD、热氧化来形成该界面层58，或者使用诸如过氧化氢(H2O2)或臭氧(O3)的氧化剂由气相或液相化学氧化来形成该界面层。界面层58的厚度可以小于1nm。
接下来，在界面层58上形成高介电常数(高k)栅极介电层60。在图20所示的工艺流程中还将相应的步骤示出为步骤216。根据本发明的一些实施例，例如，高k栅极介电层60通过使用ALD由氧化铪(HfO2)形成。高k栅极介电层60还可以包括氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)或者它们的组合。高k栅极介电层60的物理厚度可以在约1.0nm和约10nm之间的范围内。
脱氧金属层62沉积在高k栅极介电层60上。在图20所示的工艺流程中将相应的步骤示出为步骤218。脱氧金属层62比金属氧化物中的金属(高k栅极介电层60中)和硅(在界面层58中)具有更高的亲氧性。脱氧金属层62可以包括金属或金属化合物，诸如Ti、Hf、Zr、Ta、Al、TiN、TaN、TaSiN、TiSiN或者诸如TiAl的它们的组合。脱氧金属层62还可以由金属氮化物(例如，TiN或者TaN)或者诸如TiAlN的金属合金氮化物形成。沉积方法包括物理汽相沉积、CVD或者ALD。脱氧金属层62具有在升高的温度下从界面层58中提取氧的功能。
根据本发明的一些实施例，脱金属覆盖层64形成在脱氧金属层62的顶部上，以防止脱氧金属层62的氧化，其中，在随后脱氧退火之前、期间或之后可能发生氧化。脱金属覆盖层64可以包括另一金属或者诸如TiN、TiSiN、TaN、TaSiN的金属化合物。可选地，脱金属覆盖层64为硅层。脱金属覆盖层64和脱氧金属层62由不同的材料形成，但是一些候选材料可以相同。在可选实施例中，形成非脱氧覆盖层。
接下来，执行脱氧退火工艺(通过图15A中的箭头所示)以开始并能够脱氧。在图20所示的工艺流程中还将相应的步骤示出为步骤218。使用尖峰退火执行脱氧退火，其中，时间持续时间为毫秒，例如，在约10毫秒和约500毫秒之间。相应的晶圆的温度可以在约400℃和约1,100℃之间的范围内。根据一些示例性实施例中，温度在约700℃和约1,000℃之间的范围内。
脱氧工艺化学地减小界面层58，并且界面层58具有减小的厚度或者可以被去除(完全被转换)。该脱氧工艺至少从界面层58的底部夺取氧，因此，界面层58中的硅保持晶体硅层59的顶部上形成附加的硅层。图15B示出了图15A中的部分65的放大示图。在图15B中示出了箭头，以指示由于脱氧而导致的氧原子的移动。因此，如图16所示，形成晶体(或者多晶硅/非晶硅)硅层70，该晶体硅层包括晶体硅层59和晶体硅层59顶部上的附加硅层。在从界面层58的底部提取氧之后，附加的硅层由界面层58的剩余硅形成。在脱氧工艺之后，可以保留界面层58的中间部分，或者可选地，在脱氧之后，不保留界面层58。在图16的生成结构中，使用虚线示出剩余的界面层58，以指示在脱氧退火之后是否存在该界面层。
有利地，作为脱氧的结果，通过界面层58下方的硅覆盖层59的存在来提高硅层的形成，并且改善了生成的硅层的厚度均匀性。在角部57处，外延生长的硅覆盖层59薄，并且锗分离问题在角部57处严重。在本发明的一些实施例中，由于脱氧工艺而增加硅层的厚度，因此，改善了硅覆盖层的阻挡能力。尤其是，硅覆盖层在角部57处的厚度增加明显改善了硅覆盖层的阻挡能力，并且降低了角部57处的锗分离。
在脱氧退火工艺期间，高k栅极介电层60可以与界面层58的顶部混合，并且从界面层58的底部中提取氧，以形成可以为金属硅酸盐的混合化合物。层72示出为表示混合化合物和剩余的高k栅极介电层60(如果有的话)，从而可能具有增加的氧含量。例如，当高k栅极介电层60包括HfO2时，混合化合物72包括硅酸铪(HfSiO4)。当高k栅极介电层60包括ZrO2时，混合化合物72包括硅酸锆(ZrSiO4)。
在脱氧工艺之后，可以通过蚀刻去除脱金属覆盖层64。还去除了脱氧金属层62，或者保持未被去除。在图20所示的工艺流程中相应的去除步骤示出为步骤220。在鳍间距非常小(诸如小于约24nm)的实施例中，脱氧金属层62更可能被去除，以改善随后的金属填充。根据可选实施例，没有去除脱氧金属层62。
接下来，如图17A、17B、和17C所示，执行金属填充工艺，以形成替换金属栅极74。在图20所示的工艺流程中将相应的步骤示出为步骤222。为了允许独立优化n沟道和p沟道FinFET的电性能，根据生成的FinFET的类型，可以独立地形成n型金属堆叠件(用于n沟道晶体管)和p型金属堆叠件(用于p沟道晶体管)。金属堆叠件74可以包括功函层、势垒层和填充金属层(未示出)。n型金属功函层包括具有充分低的有效功函层的金属，该金属选自但不限于由钛、铝、碳化钽、碳氮化钽、氮硅化钽的组、或它们的组合。p型金属功函层包括具有充分高的有效功函层的金属，该金属选自但不限于碳化钛、氮化钽、钌、钼、钨、铂的组或者它们的组合。填充金属层可以包括铝、钨、铜、或者其他导电金属。然后执行化学机械抛光步骤，以平坦化各种金属层，并且以提供用于形成多层互连件的基本平坦的平面。图17A、17B、和17C分别示出了生成的FinFET 76的沟道宽度方向上的截面图、透视图和沟道长度方向上的截面图。接下来，可以形成接触塞(未示出)。在图20中所示的工艺流程中将相应的步骤示出为步骤224。
图18和图19示出了可以通过本发明的教导应用两个结构。在图18中，NMOS器件300包括可以用于形成全环栅晶体管的多个硅纳米线302。应该注意，尽管纳米线302被示出为悬浮，但是实际上在相对端部上支撑该纳米线，该相对端部没有位于所示的平面上。PMOS器件400包括以交替布局堆叠的SiGe纳米线402和硅纳米线404，其中，硅纳米线404具有比SiGe纳米线402减小的宽度。纳米线302、402和404形成在硅衬底20上方。
在图19中，NMOS器件300包括可以用于形成全环栅晶体管的多个锗纳米线312(其没有硅)。PMOS器件400包括以交替布局方式堆叠的锗纳米线422和SiGe纳米线414，其中，硅纳米线404具有比SiGe纳米线具有更小的宽度。纳米线312、412和414形成在SiGe衬底420上方。
如图18和图19所示，纳米线具有可以经受薄硅覆盖层和锗分离的多个角部。因此，可以采用本发明的概念，其中，使用本发明的方法环绕纳米线302、402、和404(图18)和纳米线312、412和414(图19)形成如图16所示的硅覆盖层70。
本发明的实施例具有一些有利特征。通过使用脱氧以增加现有晶体硅层的厚度，增加了硅层的薄角部的厚度，并且防止锗分离问题。
根据本发明的一些实施例，方法包括在半导体鳍上形成硅覆盖层；在硅覆盖层上方形成界面层；在界面层上方形成高k栅极介电层；以及在高k栅极介电层上方形成脱氧金属层。然后，对硅覆盖层、界面层、高k栅极介电层和脱氧金属层执行退火。填充金属沉积在高k栅极介电层上方。
优选地，在所述退火期间，从所述界面层的底部提取氧，并且所述界面层的底部被转换为硅层。
优选地，形成所述硅覆盖层包括沉积没有锗的晶体硅层。
优选地，方法进一步包括：在所述退火之前，在所述脱氧金属层上方沉积脱金属覆盖层，其中，所述脱金属覆盖层和所述脱氧金属层由不同的材料形成。
优选地，方法进一步包括：在所述退火之后，去除所述脱金属覆盖层。
优选地，在所述退火之后，所述界面层包括：与所述高k栅极介电层混合的顶部，以形成化合物层；以及转换为硅层的底部，其中，所述硅层和所述化合物层彼此接触。
优选地，在所述退火之后，所述界面层包括：与所述高k栅极介电层混合的顶部，以形成化合物层；转换为硅层的底部；以及中间部分，介于所述硅层和所述化合物层之间并且与所述硅层和所述化合物层接触。
优选地，所述退火包括尖峰退火。
根据本发明的可选实施例，方法包括在硅锗鳍上形成晶体硅覆盖层，在硅覆盖层上方形成氧化硅层，在氧化硅层上方形成高k栅极介电层，在高k栅极介电层上方形成脱氧金属层，并且从氧化硅层的底部中提取氧以将底部转换为硅层，其中，硅层与晶体硅覆盖层连续接合。在脱氧之后，填充金属沉积在高k栅极介电层上方。
优选地，方法进一步包括：在脱氧之后，去除所述脱氧金属层。
优选地，方法进一步包括：在形成所述晶体硅覆盖层之前，从所述硅锗鳍中去除硅层。
优选地，去除的硅层包括非晶硅。
优选地，方法进一步包括：在脱氧之前，在所述脱氧金属层上方沉积脱金属覆盖层，所述脱金属覆盖层和所述脱氧金属层由不同的材料形成。
优选地，方法进一步包括：在脱氧之后，去除所述脱金属覆盖层。
根据本发明的可选实施例，方法包括在硅锗鳍的中部形成伪栅叠层，在硅锗鳍的相对侧形成源极/漏极区域，在源极/漏极区域上方形成层间介电层，和在层间介电层中形成伪栅极堆叠件，去除伪栅极堆叠件以在层间介电层中形成凹槽，在凹槽中外延生长硅覆盖层，其中该硅覆盖层位于硅锗鳍上。氧化硅层沉积在硅覆盖层上方并且接触该硅覆盖层。高k栅极介电层形成在氧化硅层上方。脱氧金属层形成在高k栅极介电层上方。脱氧金属层比高k栅极介电层中的金属的第二亲和性和硅的第三亲和性具有更高的第一对于亲氧性。执行退火以至少从氧化硅层的底部提取氧，以将底部转换为硅层。在退火之后，金属填充在凹槽中。
优选地，方法进一步包括：从所述凹槽中去除附加硅层，其中，所述附加硅层与所述硅锗鳍的侧壁和顶面接触，并且从所述硅锗鳍的侧壁和顶面生长所述硅覆盖层。
优选地，方法进一步包括：在所述退火之后，去除所述脱氧金属层。
优选地，所述退火包括尖峰退火。
优选地，方法进一步包括：在所述退火之后，在所述脱氧金属层上方沉积脱金属覆盖层，其中，所述脱金属覆盖层和所述脱氧金属层由不同的材料形成。
优选地，方法进一步包括：在所述退火之后，去除所述脱金属覆盖层。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以容易地以本公开为基础设计或修改用于执行与本文所述实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员还应该意识到，这些等效结构不背离本发明的精神和范围，并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。

Claims (10)

1.一种方法，包括：
在半导体鳍上形成硅覆盖层；
在所述硅覆盖层上方形成界面层；
在所述界面层上方形成高k栅极介电层；
在所述高k栅极介电层上方形成脱氧金属层；
对所述硅覆盖层、所述界面层、所述高k栅极介电层、和所述脱氧金属层执行退火；以及
在所述高k栅极介电层上方沉积填充金属。
2.根据权利要求1所述的方法，其中，在所述退火期间，从所述界面层的底部提取氧，并且所述界面层的底部被转换为硅层。
3.根据权利要求1所述的方法，其中，形成所述硅覆盖层包括沉积没有锗的晶体硅层。
4.根据权利要求1所述的方法，进一步包括：在所述退火之前，在所述脱氧金属层上方沉积脱金属覆盖层，其中，所述脱金属覆盖层和所述脱氧金属层由不同的材料形成。
5.根据权利要求4所述的方法，进一步包括：在所述退火之后，去除所述脱金属覆盖层。
6.根据权利要求1所述的方法，其中，在所述退火之后，所述界面层包括：
与所述高k栅极介电层混合的顶部，以形成化合物层；以及
转换为硅层的底部，其中，所述硅层和所述化合物层彼此接触。
7.根据权利要求1所述的方法，其中，在所述退火之后，所述界面层包括：
与所述高k栅极介电层混合的顶部，以形成化合物层；
转换为硅层的底部；以及
中间部分，介于所述硅层和所述化合物层之间并且与所述硅层和所述化合物层接触。
8.根据权利要求1所述的方法，其中，所述退火包括尖峰退火。
9.一种方法，包括：
在硅锗鳍上形成晶体硅覆盖层；
在所述晶体硅覆盖层上方形成氧化硅层；
在所述氧化硅层上方形成高k栅极介电层；
在所述高k栅极介电层上方形成脱氧金属层；
从所述氧化硅层的底部提取氧，以将所述底部转换为硅层，其中所述硅层与所述晶体硅覆盖层连续地接合；以及
在脱氧之后，在所述高k栅极介电层上方沉积填充金属。
10.一种方法，包括：
在硅锗鳍的中间部分上形成伪栅极堆叠件；
在所述硅锗鳍的相对侧形成源极/漏极区域；
所述源极/漏极区域上方形成层间介电层，其中所述伪栅极堆叠件位于所述层间介电层中；
去除所述伪栅极堆叠件以在所述层间介电层中形成凹槽；
在所述凹槽中外延生长硅覆盖层，其中，所述硅覆盖层位于所述硅锗鳍上；
在所述硅覆盖层上方沉积氧化硅层并且所述氧化硅层与所述硅覆盖层接触；
在所述氧化硅层上方形成高k栅极介电层；
在所述高k栅极介电层上方形成脱氧金属层，其中，脱氧金属层对于氧的第一亲和性高于高k金属栅极层中金属的第二亲和性和硅的第三亲和性；
执行退火以至少从所述氧化硅层的底部提取氧，从而将所述底部转换为硅层；以及
在所述退火之后，将金属填充在所述凹槽中。
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