TW201701360A - 半導體裝置的形成方法 - Google Patents

半導體裝置的形成方法 Download PDF

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TW201701360A
TW201701360A TW104138702A TW104138702A TW201701360A TW 201701360 A TW201701360 A TW 201701360A TW 104138702 A TW104138702 A TW 104138702A TW 104138702 A TW104138702 A TW 104138702A TW 201701360 A TW201701360 A TW 201701360A
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Taiwan
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layer
forming
germanium
dielectric constant
metal
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TW104138702A
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TWI569336B (zh
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育佳 楊
葉致鍇
柯誌欣
吳政憲
陳亮吟
雄飛 于
陳燕銘
建倫 楊
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一方法，包括形成矽蓋層於半導體鰭狀物上，形成界面層於矽蓋層上，形成高介電常數閘極介電物於界面層上，以及形成除氧金屬層於高介電常數閘極介電物上。接著在矽蓋層、界面層、高介電常數閘極介電、與除氧金屬層上進行回火。填充金屬層沉積於高介電常數閘極介電物上。

Description

半導體裝置的形成方法
本揭露關於半導體裝置的形成方法，更特別關於鰭狀物角落過薄造成之阻擋能力不足及鍺隔離等問題的解決方法。
當場效電晶體的閘極長度縮短，會劣化短通道效應如汲極誘發能障降低(DIBL)，且增加關閉狀態的漏電流。為抑制短通道效應以降低關閉狀態的漏電流，需減少等效氧化矽厚度(EOT)。當場效電晶體之閘極長度小於20nm時，EOT需減少至小於1nm。
藉由減少已知介電常數之物理厚度縮小EOT的作法，會增加閘極漏電流密度。然而閘極漏電流密度具有特定限制而不能隨意增加。藉由採用較高介電常數之閘極介電物，可在特定閘極電容密度下增加其物理厚度，並有效抑制閘極漏電流。
在進階互補式金氧半(CMOS)技術世代中，高介電常數之閘極介電物可與金屬閘極搭配使用，以進一步縮小閘極長度並控制短通道效應。產業中的一般高介電常數閘極介電物為氧化鉿(HfO2)，其介電常數大於或等於約20。HfO2通常形成於界面層如氧化矽上，且其形成方法為原子層沉積(ALD)。具有中介電常數如約10的鉿矽酸鹽(HfSixOy)亦可作為閘極介電 物。
包含高介電常數之閘極介電物於界面層上的閘極介電物堆疊，其EOT為高介電常數之介電物的EOT加上界面層之EOT。為降低閘極介電物堆疊的EOT，閘極介電物堆疊可採用介電常數大於HfO2之介電常數的閘極介電材料如氧化鑭，或介電常數大於25的其他閘極介電材料。在其他實施例中，可藉由除去界面層的氧以減少甚至消除界面層厚度。在其他降低EOT的方法中，可增加界面層的介電常數。
在上述方法中，需維持低界面態密度(比如小於或等於約1011/cm2eV)以避免劣化通道中的載子移動率，並避免劣化閘極堆疊的可信度。
本揭露一實施例提供之半導體裝置的形成方法，包括：形成矽蓋層於半導體鰭狀物上；形成界面層於矽蓋層上；形成高介電常數閘極介電物於界面層上；形成除氧金屬層於高介電常數閘極介電物上；在矽蓋層、界面層、高介電常數閘極介電物、與除氧金屬層上進行回火步驟；以及沉積填充金屬於高介電常數閘極介電物上。
本揭露一實施例提供之半導體裝置的形成方法，包括：形成結晶矽蓋層於矽鍺鰭狀物上；形成氧化矽層於結晶矽蓋層上；形成高介電常數閘極介電物於氧化矽層上；形成除氧金屬層於高介電常數閘極介電物上；自氧化矽層之底部除氧，使氧化層之底部轉換為矽層，且矽層與結晶矽蓋層連續地接合；以及在上述除氧步驟後，沉積填充金屬於高介電常數閘 極介電物上。
本揭露一實施例提供之半導體裝置的形成方法，包括：形成虛置閘極堆疊於矽鍺鰭狀物的中間部份上；形成多個源極/汲極區於矽鍺鰭狀物之相反兩側上；形成層間介電物於源極/汲極區上，且虛置閘極堆疊位於層間介電物中；移除虛置閘極堆疊以形成凹陷於層間介電物中；磊晶成長矽蓋層於凹陷中，且矽蓋層位於矽鍺鰭狀物上；沉積氧化矽層於矽蓋層上，且氧化矽層接觸矽蓋層；形成高介電常數閘極介電物於氧化矽層上；形成除氧金屬層於高介電常數閘極介電物上，其中除氧金屬層對氧之第一親和力，大於高介電常數閘極介電物中的金屬對氧之第二親和力與矽對氧之第三親和力；進行回火步驟，自氧化矽層之底部除氧並使氧化矽層之底部轉換為矽層；以及在回火步驟後，將金屬填入凹陷中。
D1‧‧‧深度
H1‧‧‧高度
OS‧‧‧偏離距離
W1‧‧‧頂部寬度
W2‧‧‧底部寬度
7B-7B‧‧‧剖線
20、420‧‧‧基板
22、22A、22B‧‧‧半導體鰭狀物
23‧‧‧矽鰭狀物
24‧‧‧隔離區
25、25A、25B、40、51、52‧‧‧凹陷
26‧‧‧矽鍺層
28‧‧‧蓋層
30‧‧‧虛置閘極介電物
32‧‧‧虛置閘極
34‧‧‧虛置閘極堆疊
35、54‧‧‧硬遮罩
38‧‧‧閘極間隔物
42‧‧‧源極/汲極區
45‧‧‧主要間隔物
46‧‧‧CESL
50‧‧‧ILD
56‧‧‧結晶矽蓋層
57‧‧‧角落
58‧‧‧界面層
59‧‧‧矽蓋層
60‧‧‧高介電常數閘極介電物
62‧‧‧除氧金屬層
64‧‧‧除氧金屬蓋層
65‧‧‧部份
66‧‧‧回火製程
67‧‧‧移動方向
70‧‧‧矽層
72‧‧‧層狀物
74‧‧‧金屬堆疊
76‧‧‧FinFET
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、222、224‧‧‧步驟
300‧‧‧NMOS裝置
302、404‧‧‧矽奈米線
400‧‧‧PMOS裝置
402、414‧‧‧矽鍺奈米線
312、412‧‧‧鍺奈米線
第1A-1B、2、3A-7A、3B-7B、8-11、12A-12B、13A-13B、14、15A-15B、16、17A-17C圖係某些實施例中，鰭狀物場效電晶體(FinFET)之形成方法的剖視圖與透視圖。
第18與19圖係某些實施例中，具有奈米線之金氧半場效電晶體(MOSFET)之剖視圖。
第20圖係某些實施例中，FinFET之形成製程的流程圖。
第21A至21F圖係某些實施例中，半導體鰭狀物之形成方法的剖視圖。
第22A至22G圖係某些實施例中，半導體鰭狀物之形成方 法的剖視圖。
下述內容提供的不同實施例可實施本揭露的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本揭露。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本揭露之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
多種實施例提供鰭狀物場效電晶體(FinFET)之方法，其包含除氧步驟。下述內容說明FinFET之形成方法的中間階段，並說明某些實施例的變化。在下述多種圖式與實施例中，將以類似標號標示類似單元。
第1A至17C圖係某些實施例中，FinFET之形成方法其中間階段的剖視圖與透視圖。第1A至17C圖所示之步驟亦圖示於第20圖中的製程流程200。在下述內容中，1A至17C圖之製程步驟將搭配第20圖中的製程步驟說明。
第1A與1B圖分別為積體電路結構的剖視圖與透視 圖。第1A圖係單一半導體鰭狀物22之剖視圖，其可對應第1B圖所示之多個半導體鰭狀物22。半導體鰭狀物22形成於基板20上，且半導體基板可為部份晶圓。在本揭露某些實施例中，基板20可為半導體基板，比如矽基板、鬆弛矽碳基板、鬆弛矽鍺基板、絕緣層上矽基板、或其他半導體材料形成之基板。基板20可輕掺雜p型或n型雜質。
半導體鰭狀物22凸起於相鄰之隔離區24的上表面上，且隔離區24可為淺溝槽隔離(STI)區。在某些實施例中，半導體鰭狀物22為矽鍺鰭狀物如Si1-xGex，其中x為鍺的莫爾比例(或原子%)。x可高於約0.2，高於約0.4、高於約0.6、或高達1。當x=1時，半導體鰭狀物22為鍺鰭狀物而不含矽。半導體鰭狀物22之間距(見第1B圖)可小於30nm、小於24nm、或甚至小於15nm。鰭狀物的頂部寬度W1可小於10nm、小於約8nm、或甚至小於約6nm。鰭狀物的高度H1可大於約30nm，或大於約60nm。鰭狀物的高度H1為半導體鰭狀物22的上表面至隔離區24的上表面之間的垂直距離。鰭狀物的底部寬度W2可略大於或等於鰭狀物的頂部寬度W1。半導體鰭狀物22之側壁為實質上平直且實質上垂直。
隔離區22與半導體鰭狀物22相鄰。在本揭露某些實施例中，隔離區24為氧化矽，且其沉積方法可為化學氣相沉積(CVD)。矽鍺組成之半導體鰭狀物22與下方之基板20之間的界面可偏離隔離區24的表面。舉例來說，偏離距離OS可介於約-10nm(即界面高於隔離區24之上表面)至約10nm(即界面低於隔離區24之上表面)之間。
在本揭露某些實施例中，鬆弛或部份鬆弛的矽鍺層26可作為基板20的頂部。舉例來說，第1A圖包含矽鍺層26(Si1-yGey)，其中y小於半導體鰭狀物22(Si1-xGex)之x。由於x大於y，半導體鰭狀物22之原始晶格常數大於矽鍺層26之原始晶格常數，且半導體鰭狀物22可形成FinFET之通道。綜上所述，FinFET之通道(Si1-xGex)將處於壓縮應力下。
Si1-xGex之半導體鰭狀物22可與矽鰭狀物一起形成。第1B圖顯示多個Si1-xGex之半導體鰭狀物22與多個矽鰭狀物23(不含鍺)相鄰，並形成於鬆弛或部份鬆弛的矽鍺層26(Si1-yGey)上。矽鍺之半導體鰭狀物22與矽鰭狀物23可具有相同或不同的物理尺寸如頂部寬度W1、底部寬度W2、及/或高度H1(見第1A圖)。在本揭露某些實施例中，矽鍺之半導體鰭狀物22用以形成p型通道FinFET，而矽鰭狀物23用以形成n型通道FinFET。由於矽鰭狀物23形成於完全或部份鬆弛的矽鍺層26上，矽鰭狀物23在通道長度的方向中處於拉伸應力下。通道長度中的拉伸應力可增加矽中的電子遷移率，並改善n型通道FinFET之驅動電流與速度。
形成Si1-xGex之半導體鰭狀物22的製程將簡述如下。上述步驟即第20圖之製程流程中的步驟202。某些實施例中的對應步驟將圖示於第21A至21F圖中。首先如第21A圖所示，提供半導體的基板20。半導體的基板20可為矽基板、鬆弛SiGe基板(或矽基板上的鬆弛SiGe層)、或其他材料，如前所述。形成隔離區24(STI)以延伸至半導體的基板20中，如第21B圖所示。相鄰的隔離區24(STI)之間夾設窄條狀的基板20。蝕刻窄 條狀的基板使其凹陷，以形成凹陷25如第21C圖所示。凹陷25的底部高於隔離區24(STI)的下表面。接著如第21D圖所示，選擇性地磊晶成長半導體鰭狀物22於凹陷25中。當基板20為矽鍺基板或含有鬆弛矽鍺層時，半導體鰭狀物22可為矽。當基板20為矽基板時，半導體鰭狀物22可為Si1-xGex。接著使隔離區24(STI)凹陷以露出半導體鰭狀物。舉例來說，第21E圖顯示SiGe的半導體鰭狀物22位於矽的基板20上，而第21F圖顯示矽鰭狀物23位於含矽鍺的基板20上。
第22A至22G圖係某些實施例中，半導體鰭狀物22A與22B之形成方法的示意圖。如第22A圖所示，提供基板20。基板20可為基體矽基板，或可包含鬆弛之矽鍺層26(Si1-yGey)。第22B圖形成隔離區24(STI)於基板20或鬆弛之矽鍺層26(Si1-yGey)中。接著如第22C圖所示，使部份基板20或矽鍺層26凹陷，以形成凹陷25A。如第22D圖所示，磊晶形成Si1-xGex之半導體鰭狀物22A於凹陷25A中，其中半導體鰭狀物22A之x大於矽鍺層26之y。此外，在形成凹陷25A時，可同時形成凹陷25B如第22E圖所示。如第22F圖所示，磊晶形成Si1-zGez之半導體鰭狀物22B於凹陷25B中，其中半導體鰭狀物22B之z小於矽鍺層26之y。在後續製程中，使隔離區24(STI，見第22D與22F圖)凹陷，以形成第22G圖所示之結構。如此一來，半導體鰭狀物22A與22B形成於相同的基板20上。
第21A至21F圖與第22A至22G圖之步驟形成之結構，如第1A與1B圖所示。上述步驟形成之STI其深度D1(見第1A圖)可介於約200nm至約1000nm之間。
第2圖顯示鈍化SiGe的半導體鰭狀物22。上述步驟亦圖示於第20圖中製程流程的步驟204。在本揭露某些實施例中，上述鈍化步驟包含沉積蓋層28於半導體鰭狀物22上。蓋層28延伸於SiGe之半導體鰭狀物22之上表面與側壁上，並與其接觸。蓋層28保護SiGe的半導體鰭狀物22，使其免於被後續製程損傷。蓋層28可形成於SiGe之半導體鰭狀物22與矽鰭狀物23上(見第1B圖)，亦可只形成於SiGe之半導體鰭狀物22而不位於矽鰭狀物23上。
在本揭露某些實施例中，蓋層28之組成為結晶矽，且其形成於SiGe之半導體鰭狀物22上的方法可為採用矽烷(SiH4)、二矽烷(Si2H6)、三矽烷(Si3H8)、或其他含矽前驅物(如高矽數矽烷)的低溫磊晶。含矽前驅物亦可含氯，比如SiH2Cl2。上述磊晶成長溫度可升溫至高於室溫(約21℃)。舉例來說，磊晶溫度可為小於或等於約500℃、小於或等於約425℃、甚至小於或等於約375℃。低成長溫度可在磊晶時最小化鍺隔離的現象，其中鍺隔離會形成不需要的鍺蓋。蓋層28之厚度可小於約1.5nm。
在本揭露某些實施例中，蓋層28為CVD沉積之非晶矽層。上述沉積溫度可小於或等於約400℃。在其他實施例中，蓋層28為介電材料如氧化矽或其他介電物，且其形成方法可為原子層沉積(ALD)。蓋層28亦可包含III-V族半導體化合物層如磷化銦鋁(InAlP)或磷化銦鎵(InGaP)。可以理解的是，蓋層28亦可包含多層結構或上述實施例所述之材料的組合。舉例來說，蓋層28可包含結晶矽上非晶矽、結晶矽上氧化矽、或結 晶矽上的非晶矽上氧化矽。
第3A與3B圖分別為形成虛置閘極堆疊34之剖視圖與透視圖。上述步驟亦圖示於第20圖中的製程流程之步驟206。在某些實施例中，虛置閘極堆疊34包含虛置閘極介電物30位於半導體鰭狀物22與矽鰭狀物23上(見第3B圖)，以及虛置閘極32位於虛置閘極介電物30上。虛置閘極介電物30可為氧化矽，且虛置閘極32可為多晶矽。閘極堆疊34之形成製程可包含沉積虛置閘極介電物30與虛置閘極32，以及進行平坦化使虛置閘極32之上表面齊平。此外，虛置閘極堆疊34可包含硬遮罩35，其可為氧化矽或氮化矽。接著可進行光微影製程以圖案化虛置閘極介電物30、虛置閘極32、與硬遮罩35。綜上所述，可形成第3A與3B圖所示之結構。
如第4A、4B、5A、與5B圖所示，形成源極與汲極區。上述步驟亦圖示於第20圖中製程流程的步驟208。第4A與4B圖分別為剖視圖與透視圖。首先，形成閘極間隔物38於虛置閘極堆疊34之兩側上，其形成製程包含毯覆性地沉積，接著乾蝕刻。閘極間隔物38可包含氮化矽、碳化矽、氮氧化矽、氧化矽、上述之組合、或上述之多層結構。
在形成閘極間隔物38後，蝕刻露出的半導體鰭狀物22使其凹陷，以形成凹陷40。上述結構亦圖示於第4A與4B圖中。接著如第5A與5B圖所示，形成源極/汲極區42。第5A與5B圖分別為剖視圖與透視圖。在本揭露某些實施例中，形成p型通道FinFET之源極/汲極區42之製程，與形成n型通道FinFET之源極/汲極區(未圖示，但與源極/汲極區42類似)之製程為分 開的製程。在磊晶源極/汲極區42時，p型雜質可臨場掺雜於磊晶製程。在磊晶製程後可視情況(非必要)進行離子佈植，將p型雜質或其他改良接點電阻(如釔、鋁、錫、或類似物)之掺質導入p型通道FinFET之源極/汲極區42中。
類似地，在磊晶形成n型通道FinFET之源極/汲極區時，可臨場掺雜n型雜質於磊晶製程。在磊晶製程後可視情況(非必要)進行離子佈植，將n型雜質或其他改良接點電阻(如釔、鋁、或類似物)之掺質導入n型通道FinFET之源極/汲極區中。
接著可進行源極/汲極掺質活化回火，比如快速熱回火(RTA)、微秒回火(MSA)、尖峰回火、雷射回火(LSA)、或其他回火技術。
如第6A、6B、7A、與7B圖所示之本揭露的某些實施例，形成源極/汲極區42與n型通道FinFET之源極/汲極區。這些實施例與前述之第4A、4B、5A、與5B圖類似，除了在磊晶前先薄化半導體鰭狀物22與矽鰭狀物23(見第6B圖)，而非完全蝕刻半導體鰭狀物22與矽鰭狀物23。在薄化製程中，稍微橫向移除半導體鰭狀物22。舉例來說，原本的鰭狀物寬度若為6nm，則鰭狀物之寬度可由兩側縮短約1nm至約2nm。在薄化半導體鰭狀物22與矽鰭狀物23後，可進行源極/汲極區之磊晶製程以完成源極/汲極區42與n型通道FinFET之源極/汲極區。上述磊晶製程的細節與第5A及5B圖之內容類似。第7B圖係第7A圖中剖線7B-7B的垂直平面之剖視圖。
在某些實施例中，形成主要間隔物45如第8圖所 示。主要間隔物45之形成方法可包含形成一或多個毯覆性的介電層如氧化矽、氮化矽、或類似物，在蝕刻毯覆性的介電層以移除其水平部份。毯覆性的介電層其保留的垂直部份即主要間隔物45。
如第8圖所示，沉積CESL(接點蝕刻停止層)46。CESL可包含氮化矽，其本質應力大於或等於約1GPa。在本揭露某些實施例中，亦可採用本質應力大於1GPa的其他介電材料。上述本質應力對p型通道FinFET屬壓縮應力，但對n型通道FinFET屬拉伸應力。
接著形成ILD(層間介電物)50，其形成製程可包含沉積可流動的CVD介電物，再進行熱硬化或紫外線硬化以形成氧化矽。接著可進行平坦化製程以平坦化ILD 50的上表面。上述製程形成之結構如第9圖所示。接著使ILD 50稍微凹陷以形成凹陷52，如第10圖所示。在後續製程步驟中，沉積硬遮罩54如第11圖所示，再進行平坦化步驟如第12A圖所示。硬遮罩54可包含氮化矽，可在後續製程步驟中保護ILD 50與下方結構。
第12B圖係第12A圖中部份結構的透視圖。如第12A與12B圖所示，虛置閘極堆疊34覆蓋半導體鰭狀物22。
第13A至17C圖係置換閘極製程之剖視圖與透視圖，可將第12A與12B圖所示之虛置閘極堆疊34置換為置換閘極。在下述內容中，將以p型通道FinFET之置換閘極製程為例，其概念明顯可應用於n型通道FinFET之置換閘極製程。
第13A與13B圖分別為剖視圖與透視圖，其移除第 12A與12B圖中的虛置閘極堆疊34，因此形成凹陷51。上述步驟亦圖示於第20圖中製程流程的步驟210。首先，蝕刻移除第3A圖中的虛置閘極32與虛置閘極介電物30。綜上所述，將露出第3A圖中的蓋層28。在蓋層28為結晶矽層的實施例中，可移除或保留蓋層28。在蓋層28不是結晶矽層的實施例中，將移除蓋層28。上述步驟亦圖示於第20圖中製程流程的步驟212。移除蓋層28的有利於移除蓋層28中的任何污染。
接著磊晶成長結晶矽蓋層56。上述步驟亦圖示於第20圖中製程流程的步驟214。具有蓋層之上述結構如第14圖所示，其矽蓋層59可只有結晶矽的蓋層28、只有結晶矽蓋層56、或結晶矽的蓋層28與其上之結晶矽蓋層56。矽蓋層59之厚度可介於1原子層(約0.136nm)至約20原子層(約2.7nm)之間。在某些實施例中，矽蓋層59之厚度小於10原子層(約1.36nm)。
在某些實施例中，矽蓋層59係磊晶成長於閘極置換製程中，其可成長於p型通道裝置之矽鍺的半導體鰭狀物22與n型通道裝置(見第3B圖)之矽鰭狀物23上。在其他實施例中，矽蓋層59可成長於矽鍺的半導體鰭狀物22上，但不成長於矽鰭狀物23上，其中硬遮罩如氧化矽覆蓋矽鰭狀物23以避免矽蓋層59磊晶形成其上。
矽蓋層59有利於阻擋矽鍺之半導體鰭狀物22中的鍺原子向外擴散至後續形成的高介電常數材料，可避免形成不需要的化合物。此外，矽蓋層59亦避免鍺與後續形成之界面層(如氧化矽)中的氧反應，可避免形成不需要的氧化鍺。然而如第14圖所示，矽蓋層59之角落57可能比其他位置的矽蓋層 59(如矽蓋層59之垂直部份與水平部份)薄太多。這會降低矽蓋層59的阻擋能力。第15A、15B、與16圖顯示除氧製程，以增加矽蓋層其角落57之厚度。
在形成第14圖中的結構後，進行表面清潔(比如採用稀HF溶液)。接著如第15A圖所示，形成界面層58於矽蓋層59上。上述步驟亦圖示於第20圖中製程流程的步驟216。界面層58可為氧化矽，其形成方法可為電漿增強原子層沉積。在其他實施例中，界面層58之形成方法可為CVD、採用水蒸汽或氧的熱氧化、或採用氧化劑如雙氧水或臭氧的氣相/液相化學氧化。界面層58之厚度可小於1nm。
接著形成高介電常數閘極介電物60於界面層58上。上述步驟亦圖示於第20圖中製程流程的步驟216。在本揭露某些實施例中，高介電常數閘極介電物60可為氧化鉿(HfO2)，且其形成方法可為ALD。高介電常數閘極介電物60亦可為氧化鋯(ZrO2)、氧化鑭(La2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、氧化鍶鈦(SrTiO3)、或上述之組合。高介電常數閘極介電物60之物理厚度可介於約1.0nm至約10nm之間。
除氧金屬層62沉積於高介電常數閘極介電物60上。上述步驟亦圖示於第20圖中製程流程的步驟218。除氧金屬層62對氧的親和力，高於介電常數閘極介電物60中金屬氧化物的金屬與界面層58中的矽對氧的親和力。除氧金屬層62可包含金屬或金屬化合物如Ti、Hf、Zr、Ta、Al、TiN、TaN、TaSiN、TiSiN、或上述之組合如TiAl。除氧金屬層62亦可為金屬氮化物如TiN或TaN，亦可為金屬合金之氮化物如TiAlN。除氧金屬 層62之沉積方法包含物理氣相沉積、CVD、或ALD。除氧金屬層62可在升溫時除去界面層58中的氧。
在本揭露某些實施例中，除氧金屬蓋層64形成於除氧金屬層62之頂部上，可在後續之除氧回火之前、之中、或之後避免氧化除氧金屬層62。除氧金屬蓋層64可包含另一金屬或金屬化合物如TiN、TiSiN、TaN、或TaSiN。在其他實施例中，除氧金屬蓋層64為矽層。除氧金屬蓋層64與除氧金屬層62可為不同材料，不過他們在某些材料上的選擇可能相同。在又一實施例中，可省略除氧金屬蓋層。
接著可進行除氧回火製程66(見第15A圖)，以開始進行除氧。上述步驟亦圖示於第20圖中製程流程的步驟218。除氧回火的方法可為尖峰回火，歷時微秒等級的時間(比如介於約10微秒至約500微秒之間)。個別晶圓的溫度可介於約400℃至約1100℃之間。在某些實施例中，溫度可介於約700℃至約1000℃之間。
除氧製程可化學地縮減界面層58，即減少界面層58之厚度或完全消除(完全轉換)界面層58。除氧製程至少由界面層58之底部剝奪氧，因此保留界面層58中的矽作為矽蓋層59之頂部上的額外矽層。第15B圖係第15A圖中部份65之放大圖。由於除氧步驟，第15B圖中氧原子具有移動方向67。綜上所述，形成結晶(或多晶/非晶矽層)的矽層70如第16圖所示，其包含矽蓋層59與其頂部上的額外矽層。額外矽層係除去界面層58之底部的氧後，界面層58其保留的矽層。除氧製程後可保留界面層58之中間部份，但也可不保留界面層58。在第16圖中的 結構，保留的界面層58以虛線表示，因其可能存在或不存在於除氧回火後。
位於界面層58下之矽蓋層59有利於除氧後形成矽層，並改良矽層的厚度一致性。磊晶成長的矽蓋層59其角落57可能過薄，且角落57的鍺隔離可能很嚴重。在本揭露某些實施例中，除氧製程可增加矽層厚度，因此改善矽蓋層的阻擋能力。特別的是，矽蓋層其角落57之厚度增加可明顯改善矽蓋層的阻擋能力，並降低角落57的鍺隔離。
在除氧回火製程中，高介電常數介電物60可與界面層58之頂部與自界面層58之底部除去的氧混合，以形成混合化合物如金屬矽酸鹽。層狀物72指的是混合化合物與保留的高介電常數介電物60(若有任何高介電常數介電物60存在)，其具有增加的氧含量。舉例來說，當高介電常數介電物60包含HfO2，層狀物72如混合化合物包含鉿矽酸鹽(HfSiO4)。當高介電常數介電物60包含ZrO2，層狀物72如混合化合物包含鋯矽酸鹽(ZrSiO4)。
在除氧製程後，可蝕刻移除除氧金屬蓋層64。除氧金屬層62亦可移除，但亦可保留。上述步驟亦圖示於第20圖中製程流程的步驟220。在鰭狀物間距非常小的實施例中(比如小於約24nm)，較傾向移除除氧金屬層62以改良後續的金屬填充。在其他實施例中，則不移除除氧金屬層62。
接著如地17A、17B、與17C圖所示，進行金屬填充製程以形成置換的金屬堆疊74。上述步驟亦圖示於第20圖中製程流程的步驟222。依最後形成FinFET種類，分別形成用於n 型通道電晶體的n型金屬堆疊與用於p型通道電晶體的p型金屬堆疊，以最佳化n型通道與p型通道FinFET之電性效能。金屬堆疊74可包含功函數層、阻障層、與填充金屬層(未圖示)。n型金屬功函數層包括之金屬具有足夠低的有效功函數，包含但不限於鈦、鋁、碳化鉭、碳氮化鉭、氮化鉭矽、或上述之組合。p型金屬功函數層包括之金屬具有足夠高的有效功函數，包含但不限於氮化鈦、氮化鉭、釕、鉬、鎢、鉑、或上述之組合。填充金屬層可包含鋁、鎢、銅、或其他導電金屬、接著進行化學機械拋光平坦化多種金屬層，可提供實質上平坦的表面以形成多層內連線。第17A、17B、與17C圖分別顯示上述步驟形成之FinFET 76其於通道寬度方向的剖視圖、其透視圖、以及其於通道長度方向的剖視圖。接著可形成接點插塞(未圖示)。上述步驟亦圖示於第20圖中製程流程的步驟224。
第18與19圖顯示本揭露教示可實施之兩種結構。在第18圖中，NMOS裝置300包含多個矽奈米線302，其可用於形成全環繞式閘極電晶體。必需注意的是雖然圖示中的奈米線302看似懸浮，但實際上其相反兩端上各自有支撐(未圖示)。PMOS裝置400包含交替堆疊的矽鍺奈米線402與矽奈米線404，且矽奈米線404之寬度小於矽鍺奈米線402之寬度。矽奈米線302、矽鍺奈米線402、與矽奈米線404形成於矽的基板20上。
在第19圖中，NMOS裝置300包含多個鍺奈米線312(可不含矽)，其可用於形成全環繞式閘極電晶體。PMOS裝置400可包含交替堆疊的鍺奈米線412與矽鍺奈米線414，且矽鍺 奈米線414之寬度小於鍺奈米線412之寬度。鍺奈米線312、鍺奈米線412、與矽鍺奈米線414形成於矽鍺的基板420上。
如第18與19圖所示，奈米線其多個角落可能遭遇矽蓋層過薄與鍺隔離等問題。綜上所述，可採用本揭露概念中第16圖之之矽層70，以本揭露之方法形成矽層70包覆矽奈米線302、矽鍺奈米線402、與矽奈米線404(見第18圖)與鍺奈米線312、鍺奈米線412、與矽鍺奈米線414(見第19圖)。
本揭露實施例具有某些優點。除氧可增加已存之結晶矽層的厚度，比如增加矽層於角落部份之薄層厚度，並避免鍺隔離問題。
在本揭露某些實施例中，方法包括：形成矽蓋層於半導體鰭狀物上；形成界面層於矽蓋層上；形成高介電常數閘極介電物於界面層上；以及形成除氧金屬層於高介電常數閘極介電物上。在矽蓋層、界面層、高介電常數閘極介電物、與除氧金屬層上進行回火步驟。沉積填充金屬於高介電常數閘極介電物上。
在本揭露其他實施例中，方法包括：形成結晶矽蓋層於矽鍺鰭狀物上；形成氧化矽層於結晶矽蓋層上；形成高介電常數閘極介電物於氧化矽層上；形成除氧金屬層於高介電常數閘極介電物上；以及自氧化矽層之底部除氧，使氧化層之底部轉換為矽層，且矽層與結晶矽蓋層連續地接合。在上述除氧步驟後，沉積填充金屬於高介電常數閘極介電物上。
在本揭露又一實施例中，方法包括：形成虛置閘極堆疊於矽鍺鰭狀物的中間部份上；形成多個源極/汲極區於 矽鍺鰭狀物之相反兩側上；形成層間介電物於源極/汲極區上，且虛置閘極堆疊位於層間介電物中；移除虛置閘極堆疊以形成凹陷於層間介電物中；以及磊晶成長矽蓋層於凹陷中，且矽蓋層位於矽鍺鰭狀物上。沉積氧化矽層於矽蓋層上，且氧化矽層接觸矽蓋層。形成高介電常數閘極介電物於氧化矽層上。形成除氧金屬層於高介電常數閘極介電物上。除氧金屬層對氧之第一親和力，大於高介電常數閘極介電物中的金屬對氧之第二親和力與矽對氧之第三親和力。進行回火步驟，自氧化矽層之底部除氧並使氧化矽層之底部轉換為矽層。在回火步驟後，將金屬填入凹陷中。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本揭露。本技術領域中具有通常知識者應理解可採用本揭露作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本揭露精神與範疇，並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
58‧‧‧界面層
59‧‧‧矽蓋層
60‧‧‧高介電常數閘極介電物
62‧‧‧除氧金屬層
64‧‧‧除氧金屬蓋層
65‧‧‧部份
67‧‧‧移動方向

Claims (10)

  1. 一種半導體裝置的形成方法，包括：形成一矽蓋層於一半導體鰭狀物上；形成一界面層於該矽蓋層上；形成一高介電常數閘極介電物於該界面層上；形成一除氧金屬層於該高介電常數閘極介電物上；在該矽蓋層、該界面層、該高介電常數閘極介電物、與該除氧金屬層上進行一回火步驟；以及沉積一填充金屬於該高介電常數閘極介電物上。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該回火步驟自該界面層之底部除氧，使該界面層之底部轉換成矽層。
  3. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該矽蓋層之步驟包括沉積不含鍺的一結晶矽層。
  4. 如申請專利範圍第1項所述之半導體裝置的形成方法，更包括：在該回火步驟前，先沉積一除氧金屬蓋層於該除氧金屬層上，且該除氧金屬蓋層與該除氧金屬層之材料不同。
  5. 如申請專利範圍第4項所述之半導體裝置的形成方法，更包括：在該回火步驟後，移除該除氧金屬蓋層。
  6. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該回火步驟後的該界面層包括：一頂部，與該高介電常數閘極介電物混合以形成一化合物 層；以及一底部，轉換成一矽層，且該矽層與該化合物層彼此接觸。
  7. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該回火步驟後的該界面層包括：一頂部，與該高介電常數閘極介電物混合以形成一化合物層；一底部，轉換成一矽層；以及一中間部，位於該矽層與該化合物層之間並接觸該矽層與該化合物層。
  8. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該回火步驟包括尖峰回火。
  9. 一種半導體裝置的形成方法，包括：形成一結晶矽蓋層於一矽鍺鰭狀物上；形成一氧化矽層於該結晶矽蓋層上；形成一高介電常數閘極介電物於該氧化矽層上；形成一除氧金屬層於該高介電常數閘極介電物上；自該氧化矽層之底部除氧，使該氧化層之底部轉換為矽層，且該矽層與該結晶矽蓋層連續地接合；以及在上述除氧步驟後，沉積一填充金屬於該高介電常數閘極介電物上。
  10. 一種半導體裝置的形成方法，包括：形成一虛置閘極堆疊於一矽鍺鰭狀物的中間部份上；形成多個源極/汲極區於該矽鍺鰭狀物之相反兩側上；形成一層間介電物於該些源極/汲極區上，且該虛置閘極堆 疊位於該層間介電物中；移除該虛置閘極堆疊以形成一凹陷於該層間介電物中；磊晶成長一矽蓋層於該凹陷中，且該矽蓋層位於該矽鍺鰭狀物上；沉積一氧化矽層於該矽蓋層上，且該氧化矽層接觸該矽蓋層；形成一高介電常數閘極介電物於該氧化矽層上；形成一除氧金屬層於該高介電常數閘極介電物上，其中該除氧金屬層對氧之第一親和力，大於該高介電常數閘極介電物中的金屬對氧之第二親和力與矽對氧之第三親和力；進行一回火步驟，自該氧化矽層之底部除氧並使該氧化矽層之底部轉換為矽層；以及在該回火步驟後，將一金屬填入該凹陷中。
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