CN106549061A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN106549061A
CN106549061A CN201610697938.2A CN201610697938A CN106549061A CN 106549061 A CN106549061 A CN 106549061A CN 201610697938 A CN201610697938 A CN 201610697938A CN 106549061 A CN106549061 A CN 106549061A
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Prior art keywords
gate
gate stack
active region
dielectric
isolated
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汪柏澍
陈建茂
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明实施例公开了半导体器件及其制造方法。半导体器件包括：具有由多个隔离部件限定的有源区域的半导体衬底；在整个有源区域上方延伸并且延伸至隔离部件的一部分上的栅极堆叠件，其中栅极堆叠件包括位于有源区域上并且位于隔离部件的一部分上的栅极介电层、和位于栅极介电层上的栅电极；以及包括对栅极堆叠件的侧壁加衬的垂直部分和延伸至隔离部件的顶部表面上的水平部分的保护性密封件，其中在顶视图中，水平部分围绕栅极堆叠件的位于有源区域外部的部分。

Description

半导体器件及其制造方法
技术领域
本发明的实施例涉及半导体领域，更具体地涉及半导体器件及其制造方法。
背景技术
半导体集成电路(IC)工业已经经历了快速发展。IC材料和设计中的技术进步已经产生了数代IC，其中每一代IC比上一代IC都具有更小更复杂的电路。然而，这些进步已经增大了处理和制造IC的复杂程度，并且为了实现这些进步，需要IC处理和制造中的类似发展。当通过各种技术节点减小诸如金属氧化物半导体场效应晶体管(MOSFET)的半导体器件规模时，已经采用了几种策略以提高器件性能，诸如使用高k(HK)介电材料和金属栅极(MG)电极结构、应变工程、3D栅极晶体管和超薄主体(UTB)。尽管制造MOSFET器件的现有方法通常能满足其预期目的，但是这些方法不能在所有的方面完全符合要求。继续寻求具有提高的可靠性和增强的性能的改善的制造方法。
发明内容
本发明的实施例提供了一种半导体器件，包括：半导体衬底，具有由多个隔离部件限定的有源区域；栅极堆叠件，在整个所述有源区域上方延伸并且延伸至所述隔离部件的一部分上，其中，所述栅极堆叠件包括位于所述有源区域上并且位于所述隔离部件的所述部分上的栅极介电层、和位于所述栅极介电层上的栅电极；以及保护性密封件，包括对所述栅极堆叠件的侧壁加衬的垂直部分和延伸至所述隔离部件的顶部表面上的水平部分，其中，从上往下看，所述水平部分围绕所述栅极堆叠件的位于所述有源区域外部的部分。
本发明的实施例还提供了一种用于制造半导体器件的方法，包括：在半导体衬底中提供有源区域和多个隔离部件；在所述有源区域上并且在所述隔离部件的一部分上形成栅极介电层；在所述栅极介电层上形成伪栅极；形成保护性密封件，所述保护性密封件包括对所述栅极堆叠件的侧壁加衬的垂直部分和延伸至所述隔离部件的顶部表面上的水平部分，其中，从上往下看，所述水平部分围绕所述栅极堆叠件的位于所述有源区域外部的部分；通过蚀刻去除所述伪栅极以形成栅极沟槽，其中，所述保护性密封件在所述蚀刻期间保护所述栅极介电层不受损坏；以栅电极填充所述栅极沟槽。
本发明的实施例还提供了一种半导体器件，包括：半导体衬底，具有由多个浅沟槽隔离(STI)部件限定的有源区域；栅极堆叠件，在整个所述有源区域上方延伸并且延伸至所述浅沟槽隔离(STI)部件的一部分上，其中，所述栅极堆叠件包括位于所述有源区域上并且位于所述浅沟槽隔离(STI)部件的所述部分上的高k(HK)介电材料、和位于所述高k(HK)介电材料上的栅电极；以及保护性密封件，包括对所述栅极堆叠件的侧壁加衬的垂直部分和延伸至所述浅沟槽隔离(STI)部件的顶部表面上的水平部分，其中，从上往下看，所述水平部分围绕所述栅极堆叠件的位于所述有源区域外部的部分，并且其中，所述保护性密封件暴露所述栅极堆叠件的顶部表面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个实施例。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1是根据本发明的实施例的用于制造半导体器件的方法的流程图。
图2至图9是根据本发明的一些实施例的制造半导体器件的中间阶段的截面图。
图10是根据本发明的一些实施例的半导体器件的顶视图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明实施例。当然，这些仅仅是实例，而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明实施例可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一元件或部件的关系。类似地，诸如“前侧”和“背侧”的术语可以用于本文以更容易地识别各个组件，以及例如，可以识别这些组件位于另一组件的相对侧上。除了附图中所示的方位之外，空间相对术语旨在包括使用中或操作中的器件的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且本文使用的空间相对描述符可以同样地作相应的解释。
在具体地描述所示出的实施例之前，通常描述本发明公开的实施例的特定有利部件和实施例。总的来说，本发明实施例是半导体器件及其制造方法以提供简单和成本效益的工艺流程，以实现保护性密封件(seal)以避免湿蚀刻消耗隔离部件并且然后进入栅极电介质，诸如高k(HK)电介质，从而防止栅极电介质受到蚀刻的损坏。
图1是根据本发明的实施例的用于制造具有能够防止栅极电介质受到蚀刻损坏的保护性密封件的半导体器件的方法100的一个实施例的流程图。图2和图8是在各个制造阶段的半导体器件200的一个实施例的截面图。参考图1至图9共同描述半导体结构200及其制造方法100。应该理解，可以在方法100之前、期间和之后提供附加的步骤，并且对于方法的其他实施例，可以代替或去除所描述的一些步骤。
参考图1，用于制造半导体器件200的方法100开始于步骤110，该步骤提供具有由多个隔离部件230限定的有源区域220的半导体衬底210，以得到图2示出的结构。在一些实施例中，示例性的半导体衬底210可以是块状硅衬底。可选地，示例性的半导体衬底210可包括：元素半导体，诸如晶体结构的硅或锗；化合物半导体，诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；或它们的组合。示例性半导体衬底210还可以包括各个有源区域220，诸如配置为用于N型金属氧化物半导体晶体管器件的区域和配置为用于P型金属氧化物半导体晶体管器件的区域。此外，可以以p型或n型杂质掺杂示例性的半导体衬底210。掺杂区掺杂有：诸如硼或BF2的p型掺杂剂；诸如磷或砷的n型掺杂剂；或它们的组合。根据本领域中已知的设计需要(例如，p型阱或n型阱)，示例性衬底210可以包括各个掺杂区域。可以以P阱结构、N阱结构、双阱结构或使用凸起结构在半导体衬底210上直接形成掺杂区。此外，示例性半导体衬底210可以是应变的以用于性能增强。例如，外延层可以包括与块状半导体的半导体材料不同的半导体材料，块状半导体诸如通过包括选择性外延生长(SEG)的工艺形成的位于块状硅上面的硅锗层或位于块状硅锗上面的硅层。此外，示例性的半导体衬底210可以包括的绝缘体上半导体(SOI)结构，诸如掩埋介电层。同样可选地，示例性的半导体衬底可以包括诸如掩埋氧化物(BOX)层的掩埋介电层，诸如通过称为注氧隔离(SIMOX)技术、晶圆接合、SEG的方法或其他适当的方法形成。实际上，各个实施例可以包括各种衬底结构和材料的任何结构和材料。
在一些实施例中，示例性的半导体衬底210还包括形成在半导体衬底210中以限定和分离诸如有源区域220的各个器件的各个隔离部件230，诸如浅沟槽隔离件(STI)。示例性的隔离部件230的形成可以包括在半导体衬底中蚀刻沟槽以及通过诸如氧化硅、氮化硅或氮氧化硅的绝缘材料填充沟槽。填充的沟槽可以具有多层结构，诸如具有填充沟槽的氮化硅的热氧化物衬垫层。在一个实施例中，可以使用如下工艺顺序来生成示例性的隔离部件230：生长焊盘氧化物，形成低压化学汽相沉积(LPCVD)氮化物层，使用光刻胶并且掩蔽来图案化隔离部件230开口，在半导体衬底中蚀刻沟槽，可选择地生长热氧化物沟槽衬垫以改善沟槽界面，用CVD氧化物填充沟槽，以及使用化学机械平坦化(CMP)来去除多余的介电金属层。
方法100继续至步骤120和130，在半导体衬底210上形成多个栅极堆叠件以获得在图3和图4中示出的结构。在一些实施例中，栅极堆叠件240、250在整个有源区域220上延伸并且延伸至隔离部件230的一部分上。在一些实施例中，栅极堆叠件包括有源区域220和隔离部件230的一部分上的栅极介电层240、和栅极介电层240上的伪栅极250。在一些实施例中，示例性的栅极介电层240包括高k(HK)介电材料，选自由氧化铪、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金和它们的组合组成的组。在一些实施例中，通过诸如ALD的合适的工艺来形成示例性的栅极介电层240。形成高k介电材料层的其他方法包括金属有机物化学汽相沉积(MOCVD)、物理汽相沉积(PVD)、UV-臭氧氧化或分子束外延(MBE)。在一些实施例中，可以在半导体衬底210上形成界面层(未示出)。界面层可包括通过诸如原子层沉积(ALD)、热氧化或紫外线-臭氧氧化的适当的技术形成的氧化硅。在一些实施例中，示例性的栅极介电层240形成在有源区域220和隔离部件230的一部分上，并且然后为栅极250形成在栅极介电层上。在一些实施例中，在步骤130中，可以在后高k介电/金属栅极工艺中制造示例性的半导体器件200。在一些实施例中，在后高k介电/金属栅极工艺中，如图4中示出，最初形成伪栅极250，并且然后去除并且以金属栅电极替代，这稍后将详细说明。
在一些实施例中，在步骤120和130中，在半导体衬底上形成多个栅极堆叠件240、250。多个栅极堆叠件可以包括介电层和伪栅极。在一些实施例中，可以在栅极介电层240上形成盖(capping)层(未示出)。盖层可以包括由本领域已知的合适的工艺形成的难熔金属及它们的氮化物(例如，TiN、TaN、W2N、TiSiN、TaSiN)。可以在盖层上形成伪栅极250(例如，多晶硅层)。通过诸如传统方式的CVD的合适的技术形成伪栅极250(例如，多晶硅层)。在一些实施例中，示例性的伪栅极250选自由多晶硅、非晶硅、微晶硅和它们的组合组成的组。示例性的栅极堆叠件可以形成在衬底的不同区域中，例如，限定用于NFET器件的区域、限定用于PFET器件的区域、限定用于高电阻晶体管的区域、限定用于非功能晶体管(也称为伪晶体管)的区域和/或由用于集成电路的设计限定的其他合适的区域。
在一些实施例中，可以在伪栅极250(例如，多晶硅层)上形成图案化的硬掩模(未示出)以限定各个栅极堆叠区域和暴露要去除的栅极堆叠件材料层的各个开口。图案化的硬掩模包括氮化钛、氮化硅和/或氧化硅，或可选地包括光刻胶。图案化的硬掩模可以包括双层。在一些实施例中，硬掩模可以包括由CVD工艺沉积的氮化钛、氧化硅和氮化硅的双层。使用光刻工艺进一步图案化氮化钛、氮化硅和氧化硅层以形成图案化的光刻胶层，以及使用蚀刻工艺以蚀刻位于图案化的光刻胶层的开口内的氮化钛、氮化硅和氧化硅。
在一些实施例中，通过使用图案化的硬掩模作为蚀刻掩模，可以应用蚀刻工艺以通过蚀刻伪栅极250(例如，多晶硅层)、盖层(未示出)、栅极介电层240和界面层(未示出)来形成栅极堆叠件。蚀刻工艺包括干蚀刻、湿蚀刻或干蚀刻和湿蚀刻的组合。干蚀刻工艺可以实施含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体、和/或它们的组合。蚀刻工艺可以包括多步蚀刻以获得蚀刻选择性、灵活性和期望的蚀刻轮廓。在一些实施例中，以常规的方式采用多步干蚀刻。
方法100继续至步骤140，形成保护性密封件260。在一些实施例中，如图5所示，在步骤140中，共形沉积密封材料260'以覆盖栅极堆叠件240、250和隔离部件230的顶部表面。然后参考图6，形成蚀刻掩模270以覆盖隔离部件230的顶部表面上的密封材料260'，在顶视图中该蚀刻掩模围绕栅极堆叠件240、250的位于有源区域220外部的部分，而暴露栅极堆叠件240、250的顶部表面上的密封材料260'。在一些实施例中，蚀刻掩模270可以是由光刻工艺形成的图案化的光刻胶层。示例性的光刻工艺包括在衬底上方旋涂光刻胶层、将光刻胶暴光于图案、执行曝光后烘焙工艺和显影光刻胶以形成图案化的光刻胶层。在其他的实施例中，蚀刻掩模270可以是图案化的硬掩模，包括(但不限制于)氮化硅、氧化硅、氮氧化硅或它们的组合。可以由CVD工艺沉积图案化的硬掩模并且然后通过光刻和蚀刻工艺进行图案化。
参考图7，在蚀刻掩模270的形成之后，然后执行蚀刻工艺以去除被蚀刻掩模270暴露的密封材料260'以得到保护性密封件260，其后是蚀刻掩模270的去除。可以由灰化或选择性的湿蚀刻去除蚀刻掩模270。如图7中示出，在一些实施例中，示例性的保护性密封件260包括对栅极堆叠件240、250的侧壁加衬的垂直部分2601和延伸至隔离部件230的顶部表面上的水平部分2602。应当注意，在顶视图中，水平部分2602围绕栅极堆叠件的位于有源区域220外部的部分，这将在图10中示出。在一些实施例中，示例性的保护性密封件包括氮化硅、氮氧化硅或它们的组合。在一些实施例中，蚀刻是采用包括稀释的HF(DHF)溶液、缓冲氧化物蚀刻(BOE)溶液、热磷酸或H2O2的湿蚀刻。保护性密封件260能够在随后的处理中防止栅极电介质240和绝缘部件230(诸如STI)受到损坏。例如，已经观察到在用于形成栅极间隔件的湿蚀刻工艺中，湿蚀刻剂可以消耗隔离部件、渗透进入栅极堆叠件并且损坏栅极电介质240。然而，保护性密封件260能够在随后的处理(诸如间隔件形成、伪栅极去除等)期间防止湿蚀刻剂渗透进入栅极介电质240和隔离部件230。这样，半导体器件200可以制造为具有提高的可靠性和操作性能。
在栅极堆叠件的形成之后，半导体器件200可以经受附加的CMOS处理以形成本领域已知的NFET和PFET器件的各个部件。这样，本文只简单讨论各个部件。各个部件可以包括：轻掺杂源极/漏极区域(n型和p型LDD)、侧壁或栅极间隔件、源极/漏极(S/D)区域、硅化物部件、接触蚀刻停止层(CESL)和层间电介质(ILD)。应当注意，可以在PFET和NFET器件中分别形成诸如硅锗(SiGe)、碳化硅(SiC)部件的应变的结构以促进和增强器件的性能。
在一些实施例中，可以在源极/漏极区域(或它们的一部分)的形成之前或之后邻接栅极堆叠件240、250的侧壁形成栅极间隔件(未示出)。栅极间隔件可以包括一种或多种介电材料，诸如氧化硅、氮化硅、氮氧化硅或它们的组合。可以通过沉积介电材料和后面的各向同性刻蚀工艺形成间隔件元件，然而其他的实施例是可能的。在一些实施例中，在栅极堆叠件的侧壁上形成保护性密封件260并且在保护性密封件260上形成主间隔件。在一个实施例中，间隔件包括附加的层。例如，首先在保护性密封件上形成介电层(未示出)，然后在介电层上形成主间隔件。相应地，主间隔件能够被认为是具有间隔件的双层间隔件。在一些实施例中，保护性密封件包括氮化硅，介电层包括氧化硅，并且主间隔件包括氮化硅。通过传统方式的沉积、光刻和蚀刻工艺形成间隔件。
在一些实施例中，通过诸如一种或多种离子注入的适当的技术形成源极和漏极区域(未示出)。源极/漏极区域可以包括合适的掺杂剂的类型引入：n型或p型掺杂剂。源极/漏极区域可以包括光晕或低剂量漏极(LDD)注入、源极/漏极注入、源极/漏极激活和/或其他合适的工艺。在一些实施例中，源极/漏极区域可以包括突起的源极/漏极区域、应变的区域、外延生长的区域和/或其他的合适的技术。在实施例中，源极/漏极激活工艺可以包括快速热退火。在一些实施例中，可以对掺杂的源极/漏极区域执行硅化。硅化物材料可以包括硅化镍(NiSi)、镍铂硅化物(NiPtSi)、镍铂锗硅化物(NiPtGeSi)、硅化镍锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)、其他合适的导电材料和/或它们的组合。硅化物部件能够由包括沉积金属层、退火金属层使得金属层能够与硅反应以形成硅化物、以及然后去除未反应的金属层的工艺形成。
在一些实施例中，在源极和漏极(S/D)区域的形成之后，可以执行一个或多个退火工艺以激活S/D区域。退火工艺包括快速热退火(RTA)、激光退火工艺或其他合适的退火工艺。作为实例，高温热退火步骤可以施加在范围900℃至1100℃内的任何温度，但是其他的实施例可以使用在不同的范围内的温度。作为另一个实例，高温退火包括具有很短时间段的“尖峰”退火工艺。
在一些实施例中，源极和漏极区域可以包括用于适当的应变效应的外延生长的半导体材料，从而导致沟道中的增强的载流子迁移率。在一个实施例中，在用于p型FET(PFET)的源极和区域中外延生长硅锗。在另一个实施例中，在用于n型FET(NFET)的源极和区域中外延生长碳化硅。形成应变的结构的方法包括蚀刻以在半导体衬底中形成凹槽并且外延生长以在沟槽中形成晶体半导体材料。
参考图8，在源极和漏极区域的形成之后，在半导体衬底上和栅极堆叠件之间沉积ILD(层间介电)层290。ILD层290的沉积填充在相邻的栅极堆叠件之间的间隙中。之后，可以对ILD层290执行化学机械抛光(CMP)和/或蚀刻工艺以平坦化ILD层290直到暴露伪栅极250。ILD层290可以包括诸如原硅酸四乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃、或掺杂的氧化硅(诸如硼磷硅硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、掺杂硼的硅玻璃(BSG))、和/或其他合适的介电材料的材料。可以通过PECVD工艺或其他合适的沉积技术来沉积ILD层290。在一些实施例中，ILD层290可以包括由高纵横比工艺(HARP)和/或高密度等离子体(HDP)沉积工艺形成的氧化物。
方法100继续至步骤150和160，执行替代栅极方法以形成HK/金属栅极堆叠件。仍参考图8，在暴露伪栅极250之后，通过干蚀刻、湿蚀刻、干蚀刻和湿蚀刻的组合或其他的合适的工艺去除栅极堆叠件中的伪栅极250，从而在栅极结构中形成栅极沟槽300。例如，可以使用湿蚀刻工艺以去除伪栅极250。湿蚀刻工艺可以包括暴露于含氢氧化物溶液(例如，氢氧化铵)、去离子水和/或其他合适的蚀刻剂溶液。应该理解，可以使用其他的蚀刻化学剂以去除伪栅极250。
然后方法100继续至步骤160，如图9所示，其中在由方法100的步骤150提供的栅极沟槽300中形成栅电极280。在一些实施例中，示例性的栅电极280包括金属栅极，并且也可以包括栅极介电层、盖层、填充层和/或其他合适的层(未示出)。金属栅极中包括的功函数金属层(未示出)可以是n型或p型功函数层。示例性的p型功函金属包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、其他合适的p型功函材料或它们的组合。示例性的n型功函金属包括Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的n型功函材料或它们的组合。功函数层可以包括多个层。可以通过CVD、PVD和/或其他合适的工艺沉积功函金属层。在一些实施例中，形成的栅电极280是包括p型功函数层的p型金属栅极。
栅电极280(金属栅极堆叠件)的介电层(未示出)可以包括高k介电层，诸如氧化铪(HfO2)。可选地，高k介电层可以可选地包括其他高k电介质，诸如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合或其他合适的材料。可以通过ALD和/或其他合适的方法形成介电层。介电层可以与以上在方法100的步骤120中描述的在栅极结构中形成的栅极介电层240的构成相同或不同。
在一些实施例中，栅电极280的填充层(未示出)可以包括Al、W、或Cu和/或其他合适的材料。可以通过CVD、PVD、镀敷和/或其他合适的工艺形成填充层。填充金属可以沉积在功函数金属层上方并且从而填充在沟槽或开口的剩余部分中。
在一些实例中，执行平坦化工艺以暴露栅极栅极结构的顶部表面。平坦化工艺可以包括化学机械平坦化(CMP)。在一些实施例，可以执行金属CMP以去除多余的金属层。CMP工艺为栅极堆叠件和ILD层290提供基本平坦的表面。
在一些实施例中，一种制造半导体器件的方法还可以包括形成多层互连。多层互连件(未示出)可以包括：垂直互连件，诸如传统的通孔或接触件；和水平互连件，诸如金属线。各个互连部件可以实施包括铜、钨和硅的各种导电材料。在一个实例中，使用镶嵌工艺形成涉及铜的多层互连结构。在另一实施例中，钨用于在接触孔中形成钨插塞。因此，可以使用传统的工艺步骤形成以上附加的部件，诸如层间介电、互连件等以完成半导体器件200的制造。
相应地，得到本发明实施例的示例性的半导体器件200。如图8和9所示，它至少包括：具有由多个隔离部件(例如，浅沟槽隔离(STI)部件)230限定的有源区域220的半导体衬底210；在整个有源区域220上方延伸并且延伸至隔离部件230的一部分上的栅极堆叠件，其中栅极堆叠件包括位于有源区域220和隔离部件230的一部分上的栅极介电层(高k(HK)介电材料)240、和位于高k(HK)介电材料240上的栅电极280；以及包括对栅极堆叠件(240+280)的侧壁加衬的垂直部分2601和延伸至隔离部件230的顶部表面上的水平部分2602的保护性密封件260，其中在顶视图中，水平部分2602围绕栅极堆叠件的位于有源区域220外部的部分，并且其中保护性密封件260暴露栅极堆叠件(240+280)的顶部表面。在一些实施例中，如图10所示，保护性密封件260的示例性的水平部分2602在顶视图中可以具有“工”形状或“ㄈ”形状。注意，图10省略了ILD层290以便给出保护性密封件260的清晰描述。
尽管已经详细地描述了本发明的实施例，本领域中的技术人员可以理解，在不背离本发明实施例的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。在一个实施例中，栅电极可以可选地或附加地包括其他合适的金属。
基于上述，可以看出本发明实施例是半导体器件及其制造方法以提供简单和具有成本效益的工艺流程，以实现保护性密封件以避免湿蚀刻消耗浅沟槽隔离(STI)部件并且然后渗透进入高k(HK)介电材料，从而防止高k(HK)介电材料受到蚀刻的损坏，以提高的产量。
一个实施例是半导体器件，包括：半导体器件，该半导体器件包括：具有由多个隔离部件限定的有源区域的半导体衬底；在整个有源区域上方延伸并且延伸至隔离部件的一部分上的栅极堆叠件，其中栅极堆叠件包括位于有源区域上并且位于隔离部件的一部分上的栅极介电层、和位于栅极介电层上的栅电极；以及包括对栅极堆叠件的侧壁加衬的垂直部分和延伸至隔离部件的顶部表面上的水平部分的保护性密封件，其中在顶视图中，水平部分围绕栅极堆叠件的位于有源区域外部的部分。
另一个实施例是用于制造半导体器件的方法，包括：在半导体衬底中提供有源区域和多个隔离部件；在有源区域上并且在隔离部件的一部分上形成栅极介电层；在栅极介电层上形成伪栅极；形成包括对栅极堆叠件的侧壁加衬的垂直部分和延伸至隔离部件的顶部表面上的水平部分的保护性密封件，其中在顶视图中，水平部分围绕栅极堆叠件的位于有源区域外部的部分；通过蚀刻去除伪栅极以形成栅极沟槽，其中保护性密封件在蚀刻期间保护栅极介电层不受损坏；以及以栅电极填充栅极沟槽。
又一实施例是半导体器件，包括：具有由多个浅沟槽隔离(STI)部件限定的有源区域的半导体衬底；在整个有源区域上方延伸并且延伸至浅沟槽隔离(STI)部件的一部分上的栅极堆叠件，其中栅极堆叠件包括位于有源区域上并且位于浅沟槽隔离(STI)部件的一部分上的高k(HK)介电材料、和位于高k(HK)介电材料上的栅电极；以及包括对栅极堆叠件的侧壁加衬的垂直部分和延伸至浅沟槽隔离(STI)部件的顶部表面上的水平部分的保护性密封件，其中在顶视图中，水平部分围绕栅极堆叠件的位于有源区域外部的部分，并且其中保护性密封件暴露栅极堆叠件的顶部表面。
本发明的实施例提供了一种半导体器件，包括：半导体衬底，具有由多个隔离部件限定的有源区域；栅极堆叠件，在整个所述有源区域上方延伸并且延伸至所述隔离部件的一部分上，其中，所述栅极堆叠件包括位于所述有源区域上并且位于所述隔离部件的所述部分上的栅极介电层、和位于所述栅极介电层上的栅电极；以及保护性密封件，包括对所述栅极堆叠件的侧壁加衬的垂直部分和延伸至所述隔离部件的顶部表面上的水平部分，其中，从上往下看，所述水平部分围绕所述栅极堆叠件的位于所述有源区域外部的部分。
根据本发明的一个实施例，其中，所述隔离部件是浅沟槽隔离(STI)部件。
根据本发明的一个实施例，其中，所述栅极介电层包括高k(HK)介电材料。
根据本发明的一个实施例，其中，所述栅极介电层选自由氧化铪、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金和它们的组合组成的组。
根据本发明的一个实施例，其中，所述栅电极是金属栅极。
根据本发明的一个实施例，其中，所述保护性密封件包括氮化硅、氮氧化硅或它们的组合。
根据本发明的一个实施例，其中，所述保护性密封件具有1nm至40nm的厚度。
本发明的实施例还提供了一种用于制造半导体器件的方法，包括：在半导体衬底中提供有源区域和多个隔离部件；在所述有源区域上并且在所述隔离部件的一部分上形成栅极介电层；在所述栅极介电层上形成伪栅极；形成保护性密封件，所述保护性密封件包括对所述栅极堆叠件的侧壁加衬的垂直部分和延伸至所述隔离部件的顶部表面上的水平部分，其中，从上往下看，所述水平部分围绕所述栅极堆叠件的位于所述有源区域外部的部分；通过蚀刻去除所述伪栅极以形成栅极沟槽，其中，所述保护性密封件在所述蚀刻期间保护所述栅极介电层不受损坏；以栅电极填充所述栅极沟槽。
根据本发明的一个实施例，其中，所述形成所述保护性密封件包括：共形沉积密封材料以覆盖所述栅极堆叠件并且覆盖所述隔离部件的所述顶部表面；形成蚀刻掩模以覆盖所述隔离部件的所述顶部表面上的所述密封材料，从上往下看，所述蚀刻掩模围绕所述栅极堆叠件的位于所述有源区域外部的部分，而暴露位于所述栅极堆叠件的顶部表面上的所述密封材料；对由所述蚀刻掩模暴露的所述密封材料执行蚀刻工艺，以获得所述保护性密封件；以及去除所述蚀刻掩模。
根据本发明的一个实施例，其中，所述伪栅极选自由多晶硅、非晶硅、微晶硅和它们的组合组成的组。
根据本发明的一个实施例，其中，所述蚀刻是采用包括稀释的HF(DHF)溶液、缓冲氧化物蚀刻(BOE)溶液、热磷酸或H2O2的溶液的湿蚀刻。
根据本发明的一个实施例，其中，所述隔离部件是浅沟槽隔离(STI)部件。
根据本发明的一个实施例，其中，所述栅极介电层包括高k(HK)介电材料。
根据本发明的一个实施例，其中，所述栅极介电层选自由氧化铪、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金和它们的组合组成的组。
根据本发明的一个实施例，其中，所述栅电极包括金属栅极。
根据本发明的一个实施例，其中，所述保护性密封件包括氮化硅、氮氧化硅或它们的组合。
根据本发明的一个实施例，其中，所述保护性密封件具有1nm至40nm的厚度。
本发明的实施例还提供了一种半导体器件，包括：半导体衬底，具有由多个浅沟槽隔离(STI)部件限定的有源区域；栅极堆叠件，在整个所述有源区域上方延伸并且延伸至所述浅沟槽隔离(STI)部件的一部分上，其中，所述栅极堆叠件包括位于所述有源区域上并且位于所述浅沟槽隔离(STI)部件的所述部分上的高k(HK)介电材料、和位于所述高k(HK)介电材料上的栅电极；以及保护性密封件，包括对所述栅极堆叠件的侧壁加衬的垂直部分和延伸至所述浅沟槽隔离(STI)部件的顶部表面上的水平部分，其中，从上往下看，所述水平部分围绕所述栅极堆叠件的位于所述有源区域外部的部分，并且其中，所述保护性密封件暴露所述栅极堆叠件的顶部表面。
根据本发明的一个实施例，其中，所述栅电极包括金属栅极。
根据本发明的一个实施例，其中，所述保护性密封件包括氮化硅、氮氧化硅或它们的组合。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的实施例。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明实施例的精神和范围，并且在不背离本发明实施例的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (1)

1.一种半导体器件，包括：
半导体衬底，具有由多个隔离部件限定的有源区域；
栅极堆叠件，在整个所述有源区域上方延伸并且延伸至所述隔离部件的一部分上，其中，所述栅极堆叠件包括位于所述有源区域上并且位于所述隔离部件的所述部分上的栅极介电层、和位于所述栅极介电层上的栅电极；以及
保护性密封件，包括对所述栅极堆叠件的侧壁加衬的垂直部分和延伸至所述隔离部件的顶部表面上的水平部分，其中，从上往下看，所述水平部分围绕所述栅极堆叠件的位于所述有源区域外部的部分。
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