US20230069421A1 - Semiconductor Device and Methods of Manufacture - Google Patents
Semiconductor Device and Methods of Manufacture Download PDFInfo
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- US20230069421A1 US20230069421A1 US17/461,139 US202117461139A US2023069421A1 US 20230069421 A1 US20230069421 A1 US 20230069421A1 US 202117461139 A US202117461139 A US 202117461139A US 2023069421 A1 US2023069421 A1 US 2023069421A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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Definitions
- Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- FIG. 1 illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments.
- nano-FET nanostructure field-effect transistor
- FIGS. 2 , 3 , 4 , 5 , 6 A, 6 B, 7 A, 7 B, 8 A, 8 B, 9 A, 9 B, 10 A, 10 B, 11 A, 11 B, 11 C, 12 A, 12 B, 12 C, 12 D , 13 A, 13 B, 13 C, 14 A, 14 B, 15 A, 15 B, 16 A, 16 B, 17 A, 17 B, 18 , 19 , 20 A, 20 B, 21 A, 21 B, 22 , 23 A, 23 B, 23 C, 24 A, 24 B, 24 C, 25 A, 25 B, and 25 C are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.
- FIGS. 26 A, 26 B, and 26 C are cross-sectional views of a nano-FET, in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Embodiments are described below in a particular context, a die comprising nano-FETs. Various embodiments may be applied, however, to dies comprising other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs.
- FinFETs fin field effect transistors
- planar transistors or the like
- FIG. 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view, in accordance with some embodiments.
- the nano-FETs comprise nanostructures 55 (e.g., nanosheets, nanowire, or the like) over fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 act as channel regions for the nano-FETs.
- the nanostructure 55 may include p-type nanostructures, n-type nanostructures, or a combination thereof.
- STI regions 68 are disposed between adjacent fins 66 , which may protrude above and from between neighboring STI regions 68 .
- the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins 66 are illustrated as being single, continuous materials with the substrate 50 , the bottom portion of the fins 66 and/or the substrate 50 may comprise a single material or a plurality of materials. In this context, the fins 66 refer to the portion extending between the neighboring STI regions 68 .
- Gate dielectric layers 100 are over top surfaces of the fins 66 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 55 .
- Gate electrodes 102 are over the gate dielectric layers 100 .
- Epitaxial source/drain regions 92 are disposed on the fins 66 on opposing sides of the gate dielectric layers 100 and the gate electrodes 102 .
- FIG. 1 further illustrates reference cross-sections that are used in later figures.
- Cross-section A-A′ is along a longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions 92 of a nano-FET.
- Cross-section B-B′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of a fin 66 of the nano-FET and in a direction of, for example, a current flow between the epitaxial source/drain regions 92 of the nano-FET.
- Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity.
- Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs).
- FIGS. 2 through 26 C are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.
- FIGS. 2 through 5 , 6 A, 13 A, 14 A, 15 A, 16 A, 17 A, 23 A, 24 A, 25 A, and 26 A illustrate reference cross-section A-A′ illustrated in FIG. 1 .
- FIGS. 18 , 19 , 20 A, 21 A, and 22 illustrate magnified views of a region highlighted in FIG. 17 A .
- FIGS. 20 B and 21 B illustrate graphs describing characteristics of certain features illustrated in FIGS. 20 A and 21 A , respectively.
- FIGS. 7 A, 8 A, 9 A, 10 A, 11 A, 12 A, 12 C, 13 C, 23 C, 24 C, 25 C, and 26 C illustrate reference cross-section C-C′ illustrated in FIG. 1 .
- a substrate 50 is provided.
- the substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped.
- the substrate 50 may be a wafer, such as a silicon wafer.
- SOI substrate is a layer of a semiconductor material formed on an insulator layer.
- the insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like.
- the insulator layer is provided on a substrate, typically a silicon or glass substrate.
- the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.
- the substrate 50 has an n-type region 50 N and a p-type region 50 P.
- the n-type region 50 N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs
- the p-type region 50 P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs.
- the n-type region 50 N may be physically separated from the p-type region 50 P (as illustrated by divider 20 ), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50 N and the p-type region 50 P.
- any number of the n-type regions 50 N and the p-type regions 50 P may be provided.
- a multi-layer stack 64 is formed over the substrate 50 .
- the multi-layer stack 64 includes alternating layers of first semiconductor layers 51 A-C (collectively referred to as first semiconductor layers 51 ) and second semiconductor layers 53 A-C (collectively referred to as second semiconductor layers 53 ).
- first semiconductor layers 51 first semiconductor layers 51
- second semiconductor layers 53 second semiconductor layers 53
- the second semiconductor layers 53 will be removed and the first semiconductor layers 51 will be patterned to form channel regions of nano-FETs in the p-type region 50 P.
- the first semiconductor layers 51 will be removed and the second semiconductor layers 53 will be patterned to form channel regions of nano-FETs in the n-type regions 50 N.
- the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nano-FETs in the n-type region 50 N, and the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in the p-type regions 50 P.
- the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nano-FETS in both the n-type region 50 N and the p-type region 50 P.
- the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of non-FETs in both the n-type region 50 N and the p-type region 50 P.
- the channel regions in both the n-type region 50 N and the p-type region 50 P may have a same material composition (e.g., silicon, or the another semiconductor material) and be formed simultaneously.
- FIGS. 26 A, 26 B, and 26 C illustrate a structure resulting from such embodiments where the channel regions in both the p-type region 50 P and the n-type region 50 N comprise silicon, for example.
- the multi-layer stack 64 is illustrated as including three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53 for illustrative purposes. In some embodiments, the multi-layer stack 64 may include any number of the first semiconductor layers 51 and the second semiconductor layers 53 . Each of the layers of the multi-layer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- VPE vapor phase epitaxy
- MBE molecular beam epitaxy
- the first semiconductor layers 51 may be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium, or the like
- the second semiconductor layers 53 may be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, or the like.
- the multi-layer stack 64 is illustrated as having a bottommost semiconductor layer suitable for p-type nano-FETs for illustrative purposes. In some embodiments, multi-layer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nano-FETs.
- the first semiconductor materials and the second semiconductor materials may be materials having a high-etch selectivity to one another.
- the first semiconductor layers 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layers 53 of the second semiconductor material in the n-type region 50 N, thereby allowing the second semiconductor layers 53 to be patterned to form channel regions of n-type NSFETS.
- the second semiconductor layers 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layers 51 of the first semiconductor material in the p-type region 50 P, thereby allowing the first semiconductor layers 51 to be patterned to form channel regions of p-type NSFETS.
- fins 66 are formed in the substrate 50 and nanostructures 55 are formed in the multi-layer stack 64 , in accordance with some embodiments.
- the nanostructures 55 and the fins 66 may be formed in the multi-layer stack 64 and the substrate 50 , respectively, by etching trenches in the multi-layer stack 64 and the substrate 50 .
- the etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof.
- RIE reactive ion etch
- NBE neutral beam etch
- the etching may be anisotropic.
- Forming the nanostructures 55 by etching the multi-layer stack 64 may further define first nanostructures 52 A-C (collectively referred to as the first nanostructures 52 ) from the first semiconductor layers 51 and define second nanostructures 54 A-C (collectively referred to as the second nanostructures 54 ) from the second semiconductor layers 53 .
- the first nanostructures 52 and the second nanostructures 54 may be collectively referred to as nanostructures 55 .
- the fins 66 and the nanostructures 55 may be patterned by any suitable method.
- the fins 66 and the nanostructures 55 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66 .
- FIG. 3 illustrates the fins 66 in the n-type region 50 N and the p-type region 50 P as having substantially equal widths for illustrative purposes.
- widths of the fins 66 in the n-type region 50 N may be greater or thinner than the fins 66 in the p-type region 50 P.
- each of the fins 66 and the nanostructures 55 are illustrated as having a consistent width throughout, in other embodiments, the fins 66 and/or the nanostructures 55 may have tapered sidewalls such that a width of each of the fins 66 and/or the nanostructures 55 continuously increases in a direction towards the substrate 50 . In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.
- shallow trench isolation (STI) regions 68 are formed adjacent the fins 66 .
- the STI regions 68 may be formed by depositing an insulation material over the substrate 50 , the fins 66 , and nanostructures 55 , and between adjacent fins 66 .
- the insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used.
- the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed.
- the insulation material is formed such that excess insulation material covers the nanostructures 55 .
- the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers.
- a liner (not separately illustrated) may first be formed along a surface of the substrate 50 , the fins 66 , and the nanostructures 55 . Thereafter, a fill material, such as those discussed above may be formed over the liner.
- a removal process is then applied to the insulation material to remove excess insulation material over the nanostructures 55 .
- a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized.
- CMP chemical mechanical polish
- the planarization process exposes the nanostructures 55 such that top surfaces of the nanostructures 55 and the insulation material are level after the planarization process is complete.
- the insulation material is then recessed to form the STI regions 68 .
- the insulation material is recessed such that upper portions of fins 66 in the n-type regions 50 N and the p-type region 50 P protrude from between neighboring STI regions 68 .
- the top surfaces of the STI regions 68 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof.
- the top surfaces of the STI regions 68 may be formed flat, convex, and/or concave by an appropriate etch.
- the STI regions 68 may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins 66 and the nanostructures 55 ).
- an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.
- the process described above with respect to FIGS. 2 through 4 is just one example of how the fins 66 and the nanostructures 55 may be formed.
- the fins 66 and/or the nanostructures 55 may be formed using a mask and an epitaxial growth process.
- a dielectric layer can be formed over a top surface of the substrate 50 , and trenches can be etched through the dielectric layer to expose the underlying substrate 50 .
- Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and/or the nanostructures 55 .
- the epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials.
- the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together.
- first semiconductor layers 51 and resulting first nanostructures 52
- second semiconductor layers 53 and resulting second nanostructures 54
- first semiconductor layers 51 and the second semiconductor layers 53 are illustrated and discussed herein as comprising the same materials in the p-type region 50 P and the n-type region 50 N for illustrative purposes only.
- one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may be different materials or formed in a different order in the p-type region 50 P and the n-type region 50 N.
- appropriate wells may be formed in the fins 66 , the nanostructures 55 , and/or the STI regions 68 .
- different implant steps for the n-type region 50 N and the p-type region 50 P may be achieved using a photoresist or other masks (not separately illustrated).
- a photoresist may be formed over the fins 66 and the STI regions 68 in the n-type region 50 N and the p-type region 50 P.
- the photoresist is patterned to expose the p-type region 50 P.
- the photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques.
- an n-type impurity implant is performed in the p-type region 50 P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50 N.
- the n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in a range from about 10 13 atoms/cm 3 to about 10 14 atoms/cm 3 .
- the photoresist is removed, such as by an acceptable ashing process.
- a photoresist or other masks is formed over the fins 66 , the nanostructures 55 , and the STI regions 68 in the p-type region 50 P and the n-type region 50 N.
- the photoresist is patterned to expose the n-type region 50 N.
- the photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques.
- a p-type impurity implant may be performed in the n-type region 50 N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50 P.
- the p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in a range from about 10 13 atoms/cm 3 to about 10 14 atoms/cm 3 .
- the photoresist may be removed, such as by an acceptable ashing process.
- an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted.
- the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.
- a dummy dielectric layer 70 is formed on the fins 66 and/or the nanostructures 55 .
- the dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques.
- a dummy gate layer 72 is formed over the dummy dielectric layer 70 , and a mask layer 74 is formed over the dummy gate layer 72 .
- the dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, such as by a CMP.
- the mask layer 74 may be deposited over the dummy gate layer 72 .
- the dummy gate layer 72 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals.
- the dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material.
- the dummy gate layer 72 may be made of other materials that have a high etching selectivity from the etching of isolation regions.
- the mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like.
- a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50 N and the p-type region 50 P.
- the dummy dielectric layer 70 is shown covering only the fins 66 and the nanostructures 55 for illustrative purposes only.
- the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI regions 68 , such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI regions 68 .
- FIGS. 6 A through 18 C illustrate various additional steps in the manufacturing of embodiment devices.
- FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, 11 A, 12 A, 12 C, 13 A, 13 C, 14 A and 15 A illustrate features in either the n-type regions 50 N or the p-type regions 50 P.
- the mask layer 74 (see FIG. 5 ) may be patterned using acceptable photolithography and etching techniques to form masks 78 .
- the pattern of the masks 78 then may be transferred to the dummy gate layer 72 and to the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71 , respectively.
- the dummy gates 76 cover respective channel regions of the fins 66 .
- the pattern of the masks 78 may be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76 .
- the dummy gates 76 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins 66 .
- a first spacer layer 80 and a second spacer layer 82 are formed over the structures illustrated in FIGS. 6 A and 6 B , respectively.
- the first spacer layer 80 and the second spacer layer 82 will be subsequently patterned to act as spacers for forming self-aligned source/drain regions.
- the first spacer layer 80 is formed on top surfaces of the STI regions 68 ; top surfaces and sidewalls of the fins 66 , the nanostructures 55 , and the masks 78 ; and sidewalls of the dummy gates 76 and the dummy gate dielectrics 71 .
- the second spacer layer 82 is deposited over the first spacer layer 80 .
- the first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like.
- the second spacer layer 82 may be formed of a material having a different etch rate than the material of the first spacer layer 80 , such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.
- LDD lightly doped source/drain
- a mask such as a photoresist, may be formed over the n-type region 50 N, while exposing the p-type region 50 P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50 P. The mask may then be removed.
- a mask such as a photoresist, may be formed over the p-type region 50 P while exposing the n-type region 50 N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50 N.
- appropriate type impurities e.g., n-type
- the mask may then be removed.
- the n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed.
- the lightly doped source/drain regions may have a concentration of impurities in a range from about 1 ⁇ 10 15 atoms/cm 3 to about 1 ⁇ 10 19 atoms/cm 3 .
- An anneal may be used to repair implant damage and to activate the implanted impurities.
- first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83 .
- first spacers 81 and the second spacers 83 act to self-aligned subsequently formed source drain regions, as well as to protect sidewalls of the fins 66 and/or nanostructure 55 during subsequent processing.
- the first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like.
- the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80 , such that the first spacer layer 80 may act as an etch stop layer when patterning the second spacer layer 82 and such that the second spacer layer 82 may act as a mask when patterning the first spacer layer 80 .
- the second spacer layer 82 may be etched using an anisotropic etch process wherein the first spacer layer 80 acts as an etch stop layer, wherein remaining portions of the second spacer layer 82 form second spacers 83 as illustrated in FIG. 8 A . Thereafter, the second spacers 83 acts as a mask while etching exposed portions of the first spacer layer 80 , thereby forming first spacers 81 as illustrated in FIG. 8 A .
- the first spacers 81 and the second spacers 83 are disposed on sidewalls of the fins 66 and/or nanostructures 55 .
- the second spacer layer 82 may be removed from over the first spacer layer 80 adjacent the masks 78 , the dummy gates 76 , and the dummy gate dielectrics 71 , and the first spacers 81 are disposed on sidewalls of the masks 78 , the dummy gates 76 , and the dummy dielectric layers 60 .
- a portion of the second spacer layer 82 may remain over the first spacer layer 80 adjacent the masks 78 , the dummy gates 76 , and the dummy gate dielectrics 71 .
- spacers and LDD regions generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers 81 may be patterned prior to depositing the second spacer layer 82 ), additional spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps.
- first recesses 86 are formed in the fins 66 , the nanostructures 55 , and the substrate 50 , in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the first recesses 86 .
- the first recesses 86 may extend through the first nanostructures 52 and the second nanostructures 54 , and into the substrate 50 .
- top surfaces of the STI regions 58 may be level with bottom surfaces of the first recesses 86 .
- the fins 66 may be etched such that bottom surfaces of the first recesses 86 are disposed below the top surfaces of the STI regions 68 ; or the like.
- the first recesses 86 may be formed by etching the fins 66 , the nanostructures 55 , and the substrate 50 using anisotropic etching processes, such as RIE, NBE, or the like.
- the first spacers 81 , the second spacers 83 , and the masks 78 mask portions of the fins 66 , the nanostructures 55 , and the substrate 50 during the etching processes used to form the first recesses 86 .
- a single etch process or multiple etch processes may be used to etch each layer of the nanostructures 55 and/or the fins 66 .
- Timed etch processes may be used to stop the etching of the first recesses 86 after the first recesses 86 reach a desired depth.
- portions of sidewalls of the layers of the multi-layer stack 64 formed of the first semiconductor materials (e.g., the first nanostructures 52 ) exposed by the first recesses 86 are etched to form sidewall recesses 88 in the n-type region 50 N
- portions of sidewalls of the layers of the multi-layer stack 56 formed of the second semiconductor materials (e.g., the second nanostructures 54 ) exposed by the first recesses 86 are etched to form the sidewall recesses 88 in the p-type region 50 P.
- sidewalls of the first nanostructures 52 and the second nanostructures 54 in the sidewall recesses 88 are illustrated as being straight in FIG.
- the sidewalls may be concave or convex.
- the sidewalls may be etched using isotropic etching processes, such as wet etching or the like.
- the p-type region 50 P may be protected using a mask (not shown) while etchants selective to the first semiconductor materials are used to etch the first nanostructures 52 such that the second nanostructures 54 and the substrate 50 remain relatively unetched as compared to the first nanostructures 52 in the n-type region 50 N.
- the n-type region 50 N may be protected using a mask (not shown) while etchants selective to the second semiconductor materials are used to etch the second nanostructures 54 such that the first nanostructures 52 and the substrate 50 remain relatively unetched as compared to the second nanostructures 54 in the p-type region 50 P.
- first nanostructures 52 include, e.g., SiGe
- second nanostructures 54 include, e.g., Si or SiC
- a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like may be used to etch sidewalls of the first nanostructures 52 in the n-type region 50 N
- a wet or dry etch process with hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch sidewalls of the second nanostructures 54 in the p-type region 50 P.
- first inner spacers 90 are formed in the sidewall recesses 88 .
- the first inner spacers 90 may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated in FIGS. 10 A and 10 B .
- the first inner spacers 90 act as isolation features between subsequently formed source/drain regions and a gate structure. As will be discussed in greater detail below, source/drain regions will be formed in the first recesses 86 , while the first nanostructures 52 in the n-type region 50 N and the second nanostructures 54 in the p-type region 50 P will be replaced with corresponding gate structures.
- the inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like.
- the inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized.
- the inner spacer layer may then be anisotropically etched to form the first inner spacers 90 .
- outer sidewalls of the first inner spacers 90 are illustrated as being flush with sidewalls of the second nanostructures 54 in the n-type region 50 N and flush with the sidewalls of the first nanostructures 52 in the p-type region 50 P, the outer sidewalls of the first inner spacers 90 may extend beyond or be recessed from sidewalls of the second nanostructures 54 and/or the first nanostructures 52 , respectively.
- FIG. 11 B illustrates an embodiment in which the outer sidewalls of the first inner spacers 90 are illustrated as being straight in FIG. 11 B , the outer sidewalls of the first inner spacers 90 may be concave or convex.
- FIG. 11 C illustrates an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers are recessed from sidewalls of the second nanostructures 54 in the n-type region 50 N.
- first inner spacers 90 may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions 92 , discussed below with respect to FIGS. 12 A- 12 C ) by subsequent etching processes, such as etching processes used to form gate structures.
- epitaxial source/drain regions 92 are formed in the first recesses 86 .
- the epitaxial source/drain regions 92 may exert stress on the second nanostructures 54 in the n-type region 50 N and on the first nanostructures 52 in the p-type region 50 P, thereby improving performance.
- the epitaxial source/drain regions 92 are formed in the first recesses 86 such that each dummy gate 76 is disposed between respective neighboring pairs of the epitaxial source/drain regions 92 .
- the first spacers 81 are used to separate the epitaxial source/drain regions 92 from the dummy gate layer 72 and the first inner spacers 90 are used to separate the epitaxial source/drain regions 92 from the nanostructures 55 by an appropriate lateral distance so that the epitaxial source/drain regions 92 do not short out with subsequently formed gates of the resulting nano-FETs.
- the epitaxial source/drain regions 92 in the n-type region 50 N may be formed by masking the p-type region 50 P, e.g., the PMOS region. Then, the epitaxial source/drain regions 92 are epitaxially grown in the first recesses 86 in the n-type region 50 N.
- the epitaxial source/drain regions 92 may include any acceptable material appropriate for n-type nano-FETs.
- the epitaxial source/drain regions 92 may include materials exerting a tensile strain on the second nanostructures 54 , such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like.
- the epitaxial source/drain regions 92 may have surfaces raised from respective upper surfaces of the nanostructures 55 and may have facets.
- the epitaxial source/drain regions 92 in the p-type region 50 P may be formed by masking the n-type region 50 N, e.g., the NMOS region. Then, the epitaxial source/drain regions 92 are epitaxially grown in the first recesses 86 in the p-type region 50 P.
- the epitaxial source/drain regions 92 may include any acceptable material appropriate for p-type nano-FETs.
- the epitaxial source/drain regions 92 may comprise materials exerting a compressive strain on the first nanostructures 52 , such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like.
- the epitaxial source/drain regions 92 may also have surfaces raised from respective surfaces of the multi-layer stack 56 and may have facets.
- the epitaxial source/drain regions 92 , the first nanostructures 52 , the second nanostructures 54 , and/or the substrate 50 may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal.
- the source/drain regions may have an impurity concentration of between about 1 ⁇ 10 19 atoms/cm 3 and about 1 ⁇ 10 21 atoms/cm 3 .
- the n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed.
- the epitaxial source/drain regions 92 may be in situ doped during growth.
- upper surfaces of the epitaxial source/drain regions 92 have facets which expand laterally outward beyond sidewalls of the nanostructures 55 .
- these facets cause growth of adjacent epitaxial source/drain regions 92 of a same NSFET to merge as illustrated by FIG. 12 A .
- adjacent epitaxial source/drain regions 92 remain separated after the epitaxy process is completed as illustrated by FIG. 12 C .
- the first spacers 81 may be formed to a top surface of the STI regions 68 thereby blocking the epitaxial growth. In some other embodiments, the first spacers 81 may cover portions of the sidewalls of the nanostructures 55 further blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 58 .
- the epitaxial source/drain regions 92 may comprise one or more semiconductor material layers.
- the epitaxial source/drain regions 92 may comprise a first semiconductor material layer 92 A, a second semiconductor material layer 92 B, and a third semiconductor material layer 92 C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions 92 .
- Each of the first semiconductor material layer 92 A, the second semiconductor material layer 92 B, and the third semiconductor material layer 92 C may be formed of different semiconductor materials and may be doped to different dopant concentrations.
- the first semiconductor material layer 92 A may have a dopant concentration less than the second semiconductor material layer 92 B and greater than the third semiconductor material layer 92 C.
- the first semiconductor material layer 92 A may be deposited
- the second semiconductor material layer 92 B may be deposited over the first semiconductor material layer 92 A
- the third semiconductor material layer 92 C may be deposited over the second semiconductor material layer 92 B.
- FIG. 12 D illustrates an embodiment in which sidewalls of the first nanostructures 52 in the n-type region 50 N and sidewalls of the second nanostructures 54 in the p-type region 50 P are concave, outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from sidewalls of the second nanostructures 54 and the first nanostructures 52 , respectively.
- the epitaxial source/drain regions 92 may be formed in contact with the first inner spacers 90 and may extend past sidewalls of the second nanostructures 54 in the n-type region 50 N and past sidewalls of the first nanostructures 52 in the p-type region 50 P.
- a first interlayer dielectric (ILD) 96 is deposited over the structure illustrated in FIGS. 6 A, 12 B, and 12 A (the processes of FIGS. 7 A- 12 D do not alter the cross-section illustrated in FIGS. 6 A ), respectively.
- the first ILD 96 may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD.
- Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like.
- a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source/drain regions 92 , the mask layer 74 , and the first spacers 81 .
- the CESL 94 may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the overlying material of the first ILD 96 .
- a planarization process such as a CMP, may be performed to level the top surface of the first ILD 96 with the top surfaces of the dummy gates 76 or the masks 78 .
- the planarization process may also remove the masks 78 on the dummy gates 76 , and portions of the first spacers 81 along sidewalls of the masks 78 .
- top surfaces of the dummy gates 76 , the first spacers 81 , and the first ILD 96 are level within process variations. Accordingly, the top surfaces of the dummy gate layer 72 are exposed through the first ILD 96 .
- the masks 78 may remain, in which case the planarization process levels the top surface of the first ILD 96 with top surface of the masks 78 and the first spacers 81 .
- the dummy gate layer 72 and the mask layer 74 are removed in one or more etching steps, so that second recesses 1501 are formed. Portions of the dummy dielectric layers 60 in the second recesses 1501 are also be removed.
- the dummy gate layer 72 and the dummy dielectric layers 60 are removed by an anisotropic dry etch process.
- the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gate layer 72 at a faster rate than the first ILD 96 or the first spacers 81 .
- Each second recess 1501 exposes and/or overlies portions of nanostructures 55 , which act as channel regions in subsequently completed nano-FETs. Portions of the nanostructures 55 which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions 92 .
- the dummy dielectric layers 60 may be used as etch stop layers when the dummy gate layer 72 are etched. The dummy dielectric layers 60 may then be removed after the removal of the dummy gate layer 72 .
- the first nanostructures 52 in the n-type region 50 N and the second nanostructures 54 in the p-type region 50 P are removed extending the second recesses 1501 .
- the first nanostructures 52 may be removed by forming a mask (not shown) over the p-type region 50 P and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures 52 , while the second nanostructures 54 , the substrate 50 , the STI regions 58 remain relatively unetched as compared to the first nanostructures 52 .
- first nanostructures 52 include, e.g., SiGe
- second nanostructures 54 A- 54 C include, e.g., Si or SiC
- TMAH tetramethylammonium hydroxide
- NH 4 OH ammonium hydroxide
- the second nanostructures 54 in the p-type region 50 P may be removed by forming a mask (not shown) over the n-type region 50 N and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the second nanostructures 54 , while the first nanostructures 52 , the substrate 50 , the STI regions 58 remain relatively unetched as compared to the second nanostructures 54 .
- the second nanostructures 54 include, e.g., SiGe
- the first nanostructures 52 include, e.g., Si or SiC
- hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the second nanostructures 54 in the p-type region 50 P.
- the channel regions in the n-type region 50 N and the p-type region 50 P may be formed simultaneously, for example by removing the first nanostructures 52 in both the n-type region 50 N and the p-type region 50 P or by removing the second nanostructures 54 in both the n-type region 50 N and the p-type region 50 P.
- channel regions of n-type NSFETs and p-type NSFETS may have a same material composition, such as silicon, silicon germanium, or the like.
- FIGS. 26 A, 26 B, and 26 C illustrate a structure resulting from such embodiments where the channel regions in both the p-type region 50 P and the n-type region 50 N are provided by the second nanostructures 54 and comprise silicon, for example.
- FIGS. 17 A, 17 B, and 18 - 22 illustrate formation of gate dielectric layers 100 and gate electrodes 102 , with FIGS. 17 A and 17 B illustrating a simplified end result (for clarity) of the structures illustrated in the process steps of FIGS. 18 - 22 .
- FIG. 17 A further highlights a region 1701 of the gate electrode 102 and the gate dielectric layers 100 formed over the second nanostructures 54 . Region 1701 will be referenced with the discussion of the following figures.
- FIG. 18 illustrates a formation of the gate dielectric layers 100 , according to some embodiments.
- FIG. 18 illustrates a formation of an interfacial layer 1801 over the second nanostructures 54 and a formation of a gate dielectric 1803 over the interfacial layer 1801 .
- the interfacial layer 1801 may be a material such as silicon dioxide (SiO 2 ) formed through a process such as in situ steam generation (ISSG) or a deposition process such as chemical vapor deposition or atomic layer deposition.
- the interfacial layer 1801 may be a high-k material such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta 2 O 5 , combinations of these, or the like, and has a thickness of between about 5 ⁇ acute over ( ⁇ ) ⁇ and about 20 ⁇ acute over ( ⁇ ) ⁇ , such as about 10 ⁇ acute over ( ⁇ ) ⁇ .
- the interfacial layer 1801 may be formed conformably, while in embodiments in which ISSG is utilized the interfacial layer 1801 may be formed along the bottom of the opening without extending along the sidewalls.
- the gate dielectric 1803 comprises a nitrogen doped oxide dielectric that is initially formed prior to forming a metal content high-K (e.g., K value>13) dielectric material.
- the gate dielectric 1803 may be deposited to a thickness of between about 1 nm and about 3 nm, such as about 15 ⁇ although any suitable material and thickness may be utilized.
- the gate dielectric 1803 wraps around the second nanostructures 54 , thus forming gate-all-around channels between the epitaxial source/drain regions 92 .
- the gate electrodes 102 are formed to surround the second nanostructures 54 and serve as gate-all-around electrodes of the embodiment device.
- the gate electrodes 102 are formed using multiple layers, each layer deposited sequentially adjacent to each other using a highly conformal deposition process such as atomic layer deposition, although any suitable deposition process may be utilized.
- the gate electrodes 102 may comprise a first p-metal work function layer 1901 , a second p-metal work function layer 2101 , a glue layer 2201 , and a fill material 2203 .
- FIG. 19 illustrates a formation of the first p-metal work function layer 1901 over the gate dielectric 1803 in the eventual formation of the gate electrodes 102 , according to some embodiments.
- the first p-metal work function layer 1901 may be formed adjacent the gate dielectric 1803 .
- the first p-metal work function layer 1901 may be formed of a material such as one or more layers of a metallic material such as TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like.
- the first p-metal work function layer 1901 may be formed to a first thickness Th 1 of about 10 ⁇ . However, any suitable thickness may be used.
- the first p-metal work function layer 1901 may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used. As such, a base structure 2001 of a metal gate stack with the interfacial layer 1801 , the gate dielectric 1803 , and the first p-metal work function layer 1901 formed to surround the second nanostructures 54 , according to some embodiments.
- FIG. 20 A illustrates an annealing process 2050 for annealing the base structure 2001 of the metal gate stack, according to some embodiments.
- the base structure 2001 of the metal gate stack can be annealed to increase the electrical work function of the first p-metal work function layer 1901 .
- the annealing process 2050 may be a low temperature annealing process (e.g., LMA process) that is performed at a temperature of between about 300° C. and about 500° C., for a duration in a range from about 10 seconds to about 30 minutes.
- the annealing process 2050 is performed at a chamber pressure of between about 0.5 torr and about 10 torr.
- any suitable temperature, duration, and chamber pressure may be used.
- FIG. 20 B is a graph illustrating the percentage by atomic weight of oxygen comprised in the base structure 2001 (e.g., the interfacial layer 1801 , the gate dielectric 1803 , and the first p-metal work function layer 1901 ) of the metal gate stack according to different process temperatures and a process time used for the annealing process 2050 .
- the graph illustrates that prior to the annealing process 2050 the composition of the base structure 2001 of the metal gate stack is less than 50% oxygen by atomic weight.
- the graph further illustrates that after the annealing process 2050 for a process time of about 30 minutes, the composition of the base structure 2001 of the metal gate stack is greater than 50% oxygen by atomic weight for example between about 49.99% to about 54% oxygen by atomic weight.
- the graph further illustrates that the percent oxygen by atomic weight composition for the base structure 2001 of the metal gate stack increases as the process temperature increases for the annealing process 2050 for example from about 300° C. to about 450° C. However, any suitable percentage and any suitable temperatures maybe used.
- residual chamber oxygen may be incorporated in the base structure 2001 during the anneal process 2050 .
- the oxygen in the gate dielectric 1803 may be driven (e.g., by diffusion) into the underlying materials of the base structure 2001 .
- the first p-metal work function layer 1901 e.g., titanium nitride
- the first p-metal work function layer 1901 is doped with oxygen to form pockets of oxygen within the first p-metal work function layer 1901 .
- oxygen diffuses from the gate dielectric 1803 (e.g., hafnium oxide) into the interfacial layer 1801 (e.g., silicon oxide) and into the second nanostructures 54 (e.g., silicon).
- the incorporation of oxygen by the annealing process 2050 increases an electrical work function (eWF) of the base structure 2001 of the metal gate stack and shifts the metal gate work function towards a P-band edge of the base structure 2001 of the metal gate stack.
- eWF electrical work function
- an interface between the first p-metal work function layer 1901 and the gate dielectric 1803 has an electrical work function differential.
- an electrical work function differential of at least +44.8 may be obtained.
- FIG. 21 A illustrates, after the annealing process 2050 has been performed, a formation of the second p-metal work function layer 2101 adjacent to the first p-metal work function layer 1901 according to some embodiments.
- the second p-metal work function layer 2101 may be formed from a metallic material such as TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like.
- the second p-metal work function layer 2101 may be formed to a second thickness, a ratio of the second thickness Th 2 to first thickness Th 1 may be a ratio between about 0.5:1 and about 3:1, such as about 2:1. According to some embodiments, the second thickness Th 2 may be a thickness of between about 5 ⁇ and about 30 ⁇ , such as about 20 ⁇ . However, any suitable thickness may be used.
- the metallic material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used. As such, the second p-metal work function layer 2101 is formed to surround the first p-metal work function layer 1901 , according to some embodiments.
- FIG. 21 B is a graph illustrating the electrical work function (eWF) voltage versus a capacitance equivalent thickness (CET) (nm) of a bilayer structure comprising the first p-metal work function layer 1901 and the second p-metal work function layer 2101 after the annealing process 2050 has been performed as compared to the eWF voltage of the bilayer structure without the annealing process 2050 having been performed.
- the graph illustrates that forming the bilayer structure using the annealing process 2050 increases the eWF of the bilayer structure as compared to forming the bilayer structure without the annealing process 2050 .
- the threshold voltage (P-Vt) of the bilayer structure is reduced.
- the graph further illustrates that the eWF of the bilayer structure increases as the CET (nm) increases.
- a bilayer structure comprising the first p-metal work function layer 1901 having a first thickness of about 10 A and the second p-metal work function layer 2101 having a second thickness of about 20 A
- the bilayer structure formed without the annealing process 2050 may have an eWF of about 5.00 V around 1.4 nm CET; whereas, the bilayer structure formed with the annealing process 2050 may have an eWF of about 5.02 V around 1.4 nm CET or an increase of about +20 mV around 1.4 nm CET.
- the glue layer 2201 may be formed in order to help adhere the overlying fill material 2203 with the underlying materials as well as provide a nucleation layer for the formation of the fill material 2203 .
- the glue layer 2201 may be a material such as titanium nitride (TiN) and may be formed using a similar process such as ALD to a thickness of between about 10 ⁇ acute over ( ⁇ ) ⁇ and about 100 ⁇ acute over ( ⁇ ) ⁇ , such as about 50 ⁇ acute over ( ⁇ ) ⁇ .
- TiN titanium nitride
- ALD atomic layer
- the fill material 2203 is deposited to fill a remainder of the opening.
- the fill material may be a material such as tungsten, Al, Cu, AlCu, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like, and may be formed using a deposition process such as plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable material may be utilized.
- the formation of the gate dielectric layers 100 in the n-type region 50 N and the p-type region 50 P may occur simultaneously such that the gate dielectric layers 100 in each region are formed from the same materials, and the formation of the gate electrodes 102 may occur simultaneously such that the gate electrodes 102 in each region are formed from the same materials. Additionally, in some other embodiments, the gate dielectric layers 100 in each region may be formed by distinct processes, such that the gate dielectric layers 100 may be different materials and/or have a different number of layers, and/or the gate electrodes 102 in each region may be formed by distinct processes, such that the gate electrodes 102 may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.
- a planarization process such as a CMP, may be performed to remove the excess portions of the gate dielectric layers 100 and the material of the gate electrodes 102 , which excess portions are over the top surface of the first ILD 96 .
- the remaining portions of material of the gate electrodes 102 and the gate dielectric layers 100 thus form replacement gate structures of the resulting nano-FETs.
- the gate electrodes 102 and the gate dielectric layers 100 may be collectively referred to as “gate structures.”
- the gate structure (including the gate dielectric layers 100 and the gate electrodes 102 ) is recessed, so that a recess is formed directly over the gate structure and between opposing portions of first spacers 81 .
- a gate mask 104 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96 .
- Subsequently formed gate contacts (such as the gate contacts 114 , discussed below with respect to FIGS. 23 A and 23 B ) penetrate through the gate mask 104 to contact the top surface of the recessed gate electrodes 102 .
- a second ILD 106 is deposited over the first ILD 96 and over the gate mask 104 .
- the second ILD 106 is a flowable film formed by FCVD.
- the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like.
- the second ILD 106 , the first ILD 96 , the CESL 94 , and the gate masks 104 are etched to form third recesses 108 exposing surfaces of the epitaxial source/drain regions 92 and/or the gate structure.
- the third recesses 108 may be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like.
- the third recesses 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process; may be etched through the gate masks 104 using a second etching process; and may then be etched through the CESL 94 using a third etching process.
- a mask such as a photoresist, may be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first etching process and the second etching process.
- the etching process may over-etch, and therefore, the third recesses 108 extend into the epitaxial source/drain regions 92 and/or the gate structure, and a bottom of the third recesses 108 may be level with (e.g., at a same level, or having a same distance from the substrate), or lower than (e.g., closer to the substrate) the epitaxial source/drain regions 92 and/or the gate structure.
- 19 B illustrate the third recesses 108 as exposing the epitaxial source/drain regions 92 and the gate structure in a same cross section, in various embodiments, the epitaxial source/drain regions 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts.
- silicide regions 110 are formed over the epitaxial source/drain regions 92 .
- the silicide regions 110 are formed by first depositing a metal (not shown) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions 92 (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys, over the exposed portions of the epitaxial source/drain regions 92 , then performing a thermal anneal process to form the silicide regions 110 .
- the un-reacted portions of the deposited metal are then removed, e.g., by an etching process.
- silicide regions 110 are referred to as silicide regions, silicide regions 110 may also be germanide regions, or silicon germanide regions (e.g., regions comprising silicide and germanide).
- the silicide region 110 comprises TiSi, and has a thickness in a range between about 2 nm and about 10 nm.
- source/drain contacts 112 and gate contacts 114 are formed in the third recesses 108 .
- the source/drain contacts 112 and the gate contacts 114 may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials.
- the source/drain contacts 112 and the gate contacts 114 each include a barrier layer and a conductive material, and is electrically coupled to the underlying conductive feature (e.g., gate electrodes 102 and/or silicide region 110 in the illustrated embodiment).
- the gate contacts 114 are electrically coupled to the gate electrodes 102 and may be referred to as gate contacts or gate plugs, and the source/drain contacts 112 are electrically coupled to the silicide regions 110 and may be referred to as source/drain contacts or source/drain plugs.
- the barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.
- the conductive material 118 may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like.
- a planarization process, such as a CMP may be performed to remove excess material from a surface of the second ILD 106 .
- FIGS. 26 A-C illustrate cross-sectional views of a device according to some alternative embodiments.
- FIG. 26 A illustrates reference cross-section A-A′ illustrated in FIG. 1 .
- FIG. 26 B illustrates reference cross-section B-B′ illustrated in FIG. 1 .
- FIG. 26 C illustrates reference cross-section C-C′ illustrated in FIG. 1 .
- like reference numerals indicate like elements formed by like processes as the structure of FIGS. 22 A-C .
- channel regions in the n-type region 50 N and the p-type region 50 P comprise a same material.
- the second nanostructures 54 which comprise silicon, provide channel regions for p-type NSFETs in the p-type region 50 P and for n-type NSFETs in the n-type region 50 N.
- the structure of FIGS. 26 A-C may be formed, for example, by removing the first nanostructures 52 from both the p-type region 50 P and the n-type region 50 N simultaneously; depositing the gate dielectric layers 100 and the gate electrodes 102 P (e.g., gate electrode suitable for a p-type NSFET) around the second nanostructures 54 in the p-type region 50 P; and depositing gate dielectric layers 100 and the gate electrodes 102 N (e.g., a gate electrode suitable for a n-type NSFET) around the second nanostructures 54 in the n-type region 50 N.
- materials of the epitaxial source/drain regions 92 may be different in the n-type region 50 N compared to the p-type region 50 P as explained above
- Embodiments may achieve advantages.
- the first p-metal work function layer 1901 of the base structure 2001 is doped with oxygen and oxygen is diffused from the gate dielectric 1803 into the interfacial layer 1801 and/or diffused into the second nanostructures 54 .
- the percentage of oxygen by atomic weight composition for the base structure 2001 is increased.
- the incorporation of oxygen by the annealing process 2050 increases an electrical work function (eWF) of the base structure 2001 of the metal gate stack and shifts the metal gate work function towards a P-band edge of the base structure 2001 of the metal gate stack.
- eWF electrical work function
- an interface between the first p-metal work function layer 1901 and the gate dielectric 1803 has an electrical work function differential of at least +44.8. Furthermore, according to some embodiments, the eWF of the bilayer structure is increased by using the annealing process 2050 and a P-Vt of the bilayer structure is reduced.
- a method includes forming nanostructures in a multilayer stack; forming a gate dielectric surrounding the nanostructures; forming a first p-metal work function layer surrounding the gate dielectric; after the forming the first p-metal work function layer, performing an anneal process; after performing the anneal process, forming a second p-metal work function layer; and depositing a conductive fill material over the second p-metal work function layer.
- the method includes diffusing oxygen into the interlayer dielectric.
- a base structure including the gate dielectric, the first p-metal work function layer, and an interfacial layer includes less than 50% oxygen by atomic weight and after performing the anneal process the base structure includes greater than 50% oxygen by atomic weight.
- the diffusing oxygen into the interlayer dielectric increases an electrical work function differential at an interface between the gate dielectric and the p-metal work function layer.
- the diffusing oxygen into the interlayer dielectric increases a combined electrical work function of the first p-metal work function layer and the second p-metal work function layer by at least 20 mV.
- the forming the first p-metal work function layer includes depositing a titanium nitride material.
- the performing the anneal process includes using a process temperature within a range of 300° C. and 500° C.
- the method includes: forming nanostructures in a multilayer stack; forming an interlayer dielectric surrounding the nanostructures; forming a gate dielectric surrounding the interlayer dielectric; forming a first work function layer surrounding the gate dielectric; diffusing oxygen from the gate dielectric into the interlayer dielectric; after the diffusing, forming a second work function layer adjacent the first work function layer; and forming a gate electrode stack by depositing a conductive fill material over the second work function layer.
- the diffusing includes performing an anneal process.
- the diffusing the oxygen into the interlayer dielectric increases an electrical work function at an interface between the gate dielectric and the first work function layer.
- the forming the interlayer dielectric includes forming silicon oxide.
- the forming the gate dielectric includes forming a hafnium oxide material.
- the forming the first work function layer includes forming a titanium nitride material.
- the anneal process is performed using a process temperature within a range of 300° C. and 500° C.
- a semiconductor device in yet another embodiment, includes: a nanostructure stack; a base structure of a gate stack, the base structure including: an interlayer dielectric surrounding each nanostructure of the nanostructure stack; a gate dielectric surrounding the interlayer dielectric; and a first p-metal work function layer, the base structure having a composition that is greater than 50% oxygen by atomic weight; and a top structure of the gate stack, the top structure including a second p-metal work function layer surrounding the first p-metal work function layer and a conductive fill material disposed over the second p-metal work function layer.
- the interlayer dielectric includes a silicon oxide material.
- the gate dielectric includes a hafnium oxide material.
- the first p-metal work function layer includes a titanium nitride material.
- an interface between the first p-metal work function layer and the gate dielectric has an electrical work function differential of at least +44.8.
- an electrical work function of the first p-metal work function layer is shifted towards a P-band edge.
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Abstract
Description
- Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments. -
FIGS. 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 12C, 12D , 13A, 13B, 13C, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18, 19, 20A, 20B, 21A, 21B, 22, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B, and 25C are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments. -
FIGS. 26A, 26B, and 26C are cross-sectional views of a nano-FET, in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Embodiments are described below in a particular context, a die comprising nano-FETs. Various embodiments may be applied, however, to dies comprising other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs.
-
FIG. 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view, in accordance with some embodiments. The nano-FETs comprise nanostructures 55 (e.g., nanosheets, nanowire, or the like) overfins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein thenanostructures 55 act as channel regions for the nano-FETs. Thenanostructure 55 may include p-type nanostructures, n-type nanostructures, or a combination thereof.STI regions 68 are disposed betweenadjacent fins 66, which may protrude above and from between neighboringSTI regions 68. Although theSTI regions 68 are described and/or illustrated as being separate from thesubstrate 50, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of thefins 66 are illustrated as being single, continuous materials with thesubstrate 50, the bottom portion of thefins 66 and/or thesubstrate 50 may comprise a single material or a plurality of materials. In this context, thefins 66 refer to the portion extending between the neighboringSTI regions 68. - Gate
dielectric layers 100 are over top surfaces of thefins 66 and along top surfaces, sidewalls, and bottom surfaces of thenanostructures 55.Gate electrodes 102 are over the gatedielectric layers 100. Epitaxial source/drain regions 92 are disposed on thefins 66 on opposing sides of the gatedielectric layers 100 and thegate electrodes 102. -
FIG. 1 further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of thegate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions 92 of a nano-FET. Cross-section B-B′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of afin 66 of the nano-FET and in a direction of, for example, a current flow between the epitaxial source/drain regions 92 of the nano-FET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity. - Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs).
-
FIGS. 2 through 26C are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.FIGS. 2 through 5, 6A, 13A, 14A, 15A, 16A, 17A, 23A, 24A, 25A, and 26A illustrate reference cross-section A-A′ illustrated inFIG. 1 .FIGS. 18, 19, 20A, 21A, and 22 illustrate magnified views of a region highlighted inFIG. 17A .FIGS. 20B and 21B illustrate graphs describing characteristics of certain features illustrated inFIGS. 20A and 21A , respectively.FIGS. 6B, 7B, 8B, 9B, 10B, 11B, 11C, 12B, 12D, 13B, 14B, 15B, 16B, 17B, 23B, 24B, 25B, and 26B illustrate reference cross-section B-B′ illustrated inFIG. 1 .FIGS. 7A, 8A, 9A, 10A, 11A, 12A, 12C, 13C, 23C, 24C, 25C, and 26C illustrate reference cross-section C-C′ illustrated inFIG. 1 . - In
FIG. 2 , asubstrate 50 is provided. Thesubstrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Thesubstrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of thesubstrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. - The
substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region 50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region 50N may be physically separated from the p-type region 50P (as illustrated by divider 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one of the n-type regions 50N and one of the p-type regions 50P are illustrated, any number of the n-type regions 50N and the p-type regions 50P may be provided. - Further in
FIG. 2 , amulti-layer stack 64 is formed over thesubstrate 50. Themulti-layer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For purposes of illustration and as discussed in greater detail below, the second semiconductor layers 53 will be removed and the first semiconductor layers 51 will be patterned to form channel regions of nano-FETs in the p-type region 50P. Also, the first semiconductor layers 51 will be removed and the second semiconductor layers 53 will be patterned to form channel regions of nano-FETs in the n-type regions 50N. Nevertheless, in some embodiments the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nano-FETs in the n-type region 50N, and the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in the p-type regions 50P. - In still other embodiments, the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nano-FETS in both the n-
type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of non-FETs in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have a same material composition (e.g., silicon, or the another semiconductor material) and be formed simultaneously.FIGS. 26A, 26B, and 26C illustrate a structure resulting from such embodiments where the channel regions in both the p-type region 50P and the n-type region 50N comprise silicon, for example. - The
multi-layer stack 64 is illustrated as including three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53 for illustrative purposes. In some embodiments, themulti-layer stack 64 may include any number of the first semiconductor layers 51 and the second semiconductor layers 53. Each of the layers of themulti-layer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layers 51 may be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium, or the like, and the second semiconductor layers 53 may be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, or the like. Themulti-layer stack 64 is illustrated as having a bottommost semiconductor layer suitable for p-type nano-FETs for illustrative purposes. In some embodiments,multi-layer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nano-FETs. - The first semiconductor materials and the second semiconductor materials may be materials having a high-etch selectivity to one another. As such, the first semiconductor layers 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layers 53 of the second semiconductor material in the n-
type region 50N, thereby allowing the second semiconductor layers 53 to be patterned to form channel regions of n-type NSFETS. Similarly, the second semiconductor layers 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layers 51 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layers 51 to be patterned to form channel regions of p-type NSFETS. - Referring now to
FIG. 3 ,fins 66 are formed in thesubstrate 50 andnanostructures 55 are formed in themulti-layer stack 64, in accordance with some embodiments. In some embodiments, thenanostructures 55 and thefins 66 may be formed in themulti-layer stack 64 and thesubstrate 50, respectively, by etching trenches in themulti-layer stack 64 and thesubstrate 50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming thenanostructures 55 by etching themulti-layer stack 64 may further definefirst nanostructures 52A-C (collectively referred to as the first nanostructures 52) from the first semiconductor layers 51 and definesecond nanostructures 54A-C (collectively referred to as the second nanostructures 54) from the second semiconductor layers 53. Thefirst nanostructures 52 and thesecond nanostructures 54 may be collectively referred to asnanostructures 55. - The
fins 66 and thenanostructures 55 may be patterned by any suitable method. For example, thefins 66 and thenanostructures 55 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern thefins 66. -
FIG. 3 illustrates thefins 66 in the n-type region 50N and the p-type region 50P as having substantially equal widths for illustrative purposes. In some embodiments, widths of thefins 66 in the n-type region 50N may be greater or thinner than thefins 66 in the p-type region 50P. Further, while each of thefins 66 and thenanostructures 55 are illustrated as having a consistent width throughout, in other embodiments, thefins 66 and/or thenanostructures 55 may have tapered sidewalls such that a width of each of thefins 66 and/or thenanostructures 55 continuously increases in a direction towards thesubstrate 50. In such embodiments, each of thenanostructures 55 may have a different width and be trapezoidal in shape. - In
FIG. 4 , shallow trench isolation (STI)regions 68 are formed adjacent thefins 66. TheSTI regions 68 may be formed by depositing an insulation material over thesubstrate 50, thefins 66, andnanostructures 55, and betweenadjacent fins 66. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers thenanostructures 55. Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along a surface of thesubstrate 50, thefins 66, and thenanostructures 55. Thereafter, a fill material, such as those discussed above may be formed over the liner. - A removal process is then applied to the insulation material to remove excess insulation material over the
nanostructures 55. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes thenanostructures 55 such that top surfaces of thenanostructures 55 and the insulation material are level after the planarization process is complete. - The insulation material is then recessed to form the
STI regions 68. The insulation material is recessed such that upper portions offins 66 in the n-type regions 50N and the p-type region 50P protrude from between neighboringSTI regions 68. Further, the top surfaces of theSTI regions 68 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of theSTI regions 68 may be formed flat, convex, and/or concave by an appropriate etch. TheSTI regions 68 may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of thefins 66 and the nanostructures 55). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. - The process described above with respect to
FIGS. 2 through 4 is just one example of how thefins 66 and thenanostructures 55 may be formed. In some embodiments, thefins 66 and/or thenanostructures 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of thesubstrate 50, and trenches can be etched through the dielectric layer to expose theunderlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form thefins 66 and/or thenanostructures 55. The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together. - Additionally, the first semiconductor layers 51 (and resulting first nanostructures 52) and the second semiconductor layers 53 (and resulting second nanostructures 54) are illustrated and discussed herein as comprising the same materials in the p-
type region 50P and the n-type region 50N for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may be different materials or formed in a different order in the p-type region 50P and the n-type region 50N. - Further in
FIG. 4 , appropriate wells (not separately illustrated) may be formed in thefins 66, thenanostructures 55, and/or theSTI regions 68. In embodiments with different well types, different implant steps for the n-type region 50N and the p-type region 50P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over thefins 66 and theSTI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in a range from about 1013 atoms/cm3 to about 1014 atoms/cm3. After the implant, the photoresist is removed, such as by an acceptable ashing process. - Following or prior to the implanting of the p-
type region 50P, a photoresist or other masks (not separately illustrated) is formed over thefins 66, thenanostructures 55, and theSTI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region 50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in a range from about 1013 atoms/cm3 to about 1014 atoms/cm3. After the implant, the photoresist may be removed, such as by an acceptable ashing process. - After the implants of the n-
type region 50N and the p-type region 50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. - In
FIG. 5 , adummy dielectric layer 70 is formed on thefins 66 and/or thenanostructures 55. Thedummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. Adummy gate layer 72 is formed over thedummy dielectric layer 70, and amask layer 74 is formed over thedummy gate layer 72. Thedummy gate layer 72 may be deposited over thedummy dielectric layer 70 and then planarized, such as by a CMP. Themask layer 74 may be deposited over thedummy gate layer 72. Thedummy gate layer 72 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. Thedummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. Thedummy gate layer 72 may be made of other materials that have a high etching selectivity from the etching of isolation regions. Themask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a singledummy gate layer 72 and asingle mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It is noted that thedummy dielectric layer 70 is shown covering only thefins 66 and thenanostructures 55 for illustrative purposes only. In some embodiments, thedummy dielectric layer 70 may be deposited such that thedummy dielectric layer 70 covers theSTI regions 68, such that thedummy dielectric layer 70 extends between thedummy gate layer 72 and theSTI regions 68. -
FIGS. 6A through 18C illustrate various additional steps in the manufacturing of embodiment devices.FIGS. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 12C, 13A, 13C, 14A and 15A illustrate features in either the n-type regions 50N or the p-type regions 50P. InFIGS. 6A and 6B , the mask layer 74 (seeFIG. 5 ) may be patterned using acceptable photolithography and etching techniques to form masks 78. The pattern of themasks 78 then may be transferred to thedummy gate layer 72 and to thedummy dielectric layer 70 to formdummy gates 76 anddummy gate dielectrics 71, respectively. Thedummy gates 76 cover respective channel regions of thefins 66. The pattern of themasks 78 may be used to physically separate each of thedummy gates 76 fromadjacent dummy gates 76. Thedummy gates 76 may also have a lengthwise direction substantially perpendicular to the lengthwise direction ofrespective fins 66. - In
FIGS. 7A and 7B , afirst spacer layer 80 and asecond spacer layer 82 are formed over the structures illustrated inFIGS. 6A and 6B , respectively. Thefirst spacer layer 80 and thesecond spacer layer 82 will be subsequently patterned to act as spacers for forming self-aligned source/drain regions. InFIGS. 7A and 7B , thefirst spacer layer 80 is formed on top surfaces of theSTI regions 68; top surfaces and sidewalls of thefins 66, thenanostructures 55, and themasks 78; and sidewalls of thedummy gates 76 and thedummy gate dielectrics 71. Thesecond spacer layer 82 is deposited over thefirst spacer layer 80. Thefirst spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like. Thesecond spacer layer 82 may be formed of a material having a different etch rate than the material of thefirst spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like. - After the
first spacer layer 80 is formed and prior to forming thesecond spacer layer 82, implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above inFIG. 4 , a mask, such as a photoresist, may be formed over the n-type region 50N, while exposing the p-type region 50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposedfins 66 andnanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposedfins 66 andnanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in a range from about 1×1015 atoms/cm3 to about 1×1019 atoms/cm3. An anneal may be used to repair implant damage and to activate the implanted impurities. - In
FIGS. 8A and 8B , thefirst spacer layer 80 and thesecond spacer layer 82 are etched to formfirst spacers 81 andsecond spacers 83. As will be discussed in greater detail below, thefirst spacers 81 and thesecond spacers 83 act to self-aligned subsequently formed source drain regions, as well as to protect sidewalls of thefins 66 and/ornanostructure 55 during subsequent processing. Thefirst spacer layer 80 and thesecond spacer layer 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of thesecond spacer layer 82 has a different etch rate than the material of thefirst spacer layer 80, such that thefirst spacer layer 80 may act as an etch stop layer when patterning thesecond spacer layer 82 and such that thesecond spacer layer 82 may act as a mask when patterning thefirst spacer layer 80. For example, thesecond spacer layer 82 may be etched using an anisotropic etch process wherein thefirst spacer layer 80 acts as an etch stop layer, wherein remaining portions of thesecond spacer layer 82 form second spacers 83 as illustrated inFIG. 8A . Thereafter, thesecond spacers 83 acts as a mask while etching exposed portions of thefirst spacer layer 80, thereby formingfirst spacers 81 as illustrated inFIG. 8A . - As illustrated in
FIG. 8A , thefirst spacers 81 and thesecond spacers 83 are disposed on sidewalls of thefins 66 and/ornanostructures 55. As illustrated inFIG. 8B , in some embodiments, thesecond spacer layer 82 may be removed from over thefirst spacer layer 80 adjacent themasks 78, thedummy gates 76, and thedummy gate dielectrics 71, and thefirst spacers 81 are disposed on sidewalls of themasks 78, thedummy gates 76, and the dummy dielectric layers 60. In other embodiments, a portion of thesecond spacer layer 82 may remain over thefirst spacer layer 80 adjacent themasks 78, thedummy gates 76, and thedummy gate dielectrics 71. - It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the
first spacers 81 may be patterned prior to depositing the second spacer layer 82), additional spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps. - In
FIGS. 9A and 9B , first recesses 86 are formed in thefins 66, thenanostructures 55, and thesubstrate 50, in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the first recesses 86. The first recesses 86 may extend through thefirst nanostructures 52 and thesecond nanostructures 54, and into thesubstrate 50. As illustrated inFIG. 9A , top surfaces of the STI regions 58 may be level with bottom surfaces of the first recesses 86. In various embodiments, thefins 66 may be etched such that bottom surfaces of thefirst recesses 86 are disposed below the top surfaces of theSTI regions 68; or the like. The first recesses 86 may be formed by etching thefins 66, thenanostructures 55, and thesubstrate 50 using anisotropic etching processes, such as RIE, NBE, or the like. Thefirst spacers 81, thesecond spacers 83, and themasks 78 mask portions of thefins 66, thenanostructures 55, and thesubstrate 50 during the etching processes used to form the first recesses 86. A single etch process or multiple etch processes may be used to etch each layer of thenanostructures 55 and/or thefins 66. Timed etch processes may be used to stop the etching of thefirst recesses 86 after thefirst recesses 86 reach a desired depth. - In
FIGS. 10A and 10B , portions of sidewalls of the layers of themulti-layer stack 64 formed of the first semiconductor materials (e.g., the first nanostructures 52) exposed by thefirst recesses 86 are etched to form sidewall recesses 88 in the n-type region 50N, and portions of sidewalls of the layers of the multi-layer stack 56 formed of the second semiconductor materials (e.g., the second nanostructures 54) exposed by thefirst recesses 86 are etched to form the sidewall recesses 88 in the p-type region 50P. Although sidewalls of thefirst nanostructures 52 and thesecond nanostructures 54 in the sidewall recesses 88 are illustrated as being straight inFIG. 10B , the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. The p-type region 50P may be protected using a mask (not shown) while etchants selective to the first semiconductor materials are used to etch thefirst nanostructures 52 such that thesecond nanostructures 54 and thesubstrate 50 remain relatively unetched as compared to thefirst nanostructures 52 in the n-type region 50N. Similarly, the n-type region 50N may be protected using a mask (not shown) while etchants selective to the second semiconductor materials are used to etch thesecond nanostructures 54 such that thefirst nanostructures 52 and thesubstrate 50 remain relatively unetched as compared to thesecond nanostructures 54 in the p-type region 50P. In an embodiment in which thefirst nanostructures 52 include, e.g., SiGe, and thesecond nanostructures 54 include, e.g., Si or SiC, a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch sidewalls of thefirst nanostructures 52 in the n-type region 50N, and a wet or dry etch process with hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch sidewalls of thesecond nanostructures 54 in the p-type region 50P. - In
FIGS. 11A-11C , firstinner spacers 90 are formed in the sidewall recesses 88. The firstinner spacers 90 may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated inFIGS. 10A and 10B . The firstinner spacers 90 act as isolation features between subsequently formed source/drain regions and a gate structure. As will be discussed in greater detail below, source/drain regions will be formed in thefirst recesses 86, while thefirst nanostructures 52 in the n-type region 50N and thesecond nanostructures 54 in the p-type region 50P will be replaced with corresponding gate structures. - The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the first
inner spacers 90. Although outer sidewalls of the firstinner spacers 90 are illustrated as being flush with sidewalls of thesecond nanostructures 54 in the n-type region 50N and flush with the sidewalls of thefirst nanostructures 52 in the p-type region 50P, the outer sidewalls of the firstinner spacers 90 may extend beyond or be recessed from sidewalls of thesecond nanostructures 54 and/or thefirst nanostructures 52, respectively. - Moreover, although the outer sidewalls of the first
inner spacers 90 are illustrated as being straight inFIG. 11B , the outer sidewalls of the firstinner spacers 90 may be concave or convex. As an example,FIG. 11C illustrates an embodiment in which sidewalls of thefirst nanostructures 52 are concave, outer sidewalls of the firstinner spacers 90 are concave, and the first inner spacers are recessed from sidewalls of thesecond nanostructures 54 in the n-type region 50N. Also illustrated are embodiments in which sidewalls of thesecond nanostructures 54 are concave, outer sidewalls of the firstinner spacers 90 are concave, and the first inner spacers are recessed from sidewalls of thefirst nanostructures 52 in the p-type region 50P. The inner spacer layer may be etched by an anisotropic etching process, such as RIE, NBE, or the like. The firstinner spacers 90 may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions 92, discussed below with respect toFIGS. 12A-12C ) by subsequent etching processes, such as etching processes used to form gate structures. - In
FIGS. 12A-12C , epitaxial source/drain regions 92 are formed in the first recesses 86. In some embodiments, the epitaxial source/drain regions 92 may exert stress on thesecond nanostructures 54 in the n-type region 50N and on thefirst nanostructures 52 in the p-type region 50P, thereby improving performance. As illustrated inFIG. 12B , the epitaxial source/drain regions 92 are formed in thefirst recesses 86 such that eachdummy gate 76 is disposed between respective neighboring pairs of the epitaxial source/drain regions 92. In some embodiments, thefirst spacers 81 are used to separate the epitaxial source/drain regions 92 from thedummy gate layer 72 and the firstinner spacers 90 are used to separate the epitaxial source/drain regions 92 from thenanostructures 55 by an appropriate lateral distance so that the epitaxial source/drain regions 92 do not short out with subsequently formed gates of the resulting nano-FETs. - The epitaxial source/
drain regions 92 in the n-type region 50N, e.g., the NMOS region, may be formed by masking the p-type region 50P, e.g., the PMOS region. Then, the epitaxial source/drain regions 92 are epitaxially grown in thefirst recesses 86 in the n-type region 50N. The epitaxial source/drain regions 92 may include any acceptable material appropriate for n-type nano-FETs. For example, if thesecond nanostructures 54 are silicon, the epitaxial source/drain regions 92 may include materials exerting a tensile strain on thesecond nanostructures 54, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions 92 may have surfaces raised from respective upper surfaces of thenanostructures 55 and may have facets. - The epitaxial source/
drain regions 92 in the p-type region 50P, e.g., the PMOS region, may be formed by masking the n-type region 50N, e.g., the NMOS region. Then, the epitaxial source/drain regions 92 are epitaxially grown in thefirst recesses 86 in the p-type region 50P. The epitaxial source/drain regions 92 may include any acceptable material appropriate for p-type nano-FETs. For example, if thefirst nanostructures 52 are silicon germanium, the epitaxial source/drain regions 92 may comprise materials exerting a compressive strain on thefirst nanostructures 52, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions 92 may also have surfaces raised from respective surfaces of the multi-layer stack 56 and may have facets. - The epitaxial source/
drain regions 92, thefirst nanostructures 52, thesecond nanostructures 54, and/or thesubstrate 50 may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×1019 atoms/cm3 and about 1×1021 atoms/cm3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions 92 may be in situ doped during growth. - As a result of the epitaxy processes used to form the epitaxial source/
drain regions 92 in the n-type region 50N and the p-type region 50P, upper surfaces of the epitaxial source/drain regions 92 have facets which expand laterally outward beyond sidewalls of thenanostructures 55. In some embodiments, these facets cause growth of adjacent epitaxial source/drain regions 92 of a same NSFET to merge as illustrated byFIG. 12A . In other embodiments, adjacent epitaxial source/drain regions 92 remain separated after the epitaxy process is completed as illustrated byFIG. 12C . In the embodiments illustrated inFIGS. 12A and 12C , thefirst spacers 81 may be formed to a top surface of theSTI regions 68 thereby blocking the epitaxial growth. In some other embodiments, thefirst spacers 81 may cover portions of the sidewalls of thenanostructures 55 further blocking the epitaxial growth. In some other embodiments, the spacer etch used to form thefirst spacers 81 may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 58. - The epitaxial source/
drain regions 92 may comprise one or more semiconductor material layers. For example, the epitaxial source/drain regions 92 may comprise a firstsemiconductor material layer 92A, a secondsemiconductor material layer 92B, and a thirdsemiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions 92. Each of the firstsemiconductor material layer 92A, the secondsemiconductor material layer 92B, and the thirdsemiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the firstsemiconductor material layer 92A may have a dopant concentration less than the secondsemiconductor material layer 92B and greater than the thirdsemiconductor material layer 92C. In embodiments in which the epitaxial source/drain regions 92 comprise three semiconductor material layers, the firstsemiconductor material layer 92A may be deposited, the secondsemiconductor material layer 92B may be deposited over the firstsemiconductor material layer 92A, and the thirdsemiconductor material layer 92C may be deposited over the secondsemiconductor material layer 92B. -
FIG. 12D illustrates an embodiment in which sidewalls of thefirst nanostructures 52 in the n-type region 50N and sidewalls of thesecond nanostructures 54 in the p-type region 50P are concave, outer sidewalls of the firstinner spacers 90 are concave, and the firstinner spacers 90 are recessed from sidewalls of thesecond nanostructures 54 and thefirst nanostructures 52, respectively. As illustrated inFIG. 12D , the epitaxial source/drain regions 92 may be formed in contact with the firstinner spacers 90 and may extend past sidewalls of thesecond nanostructures 54 in the n-type region 50N and past sidewalls of thefirst nanostructures 52 in the p-type region 50P. - In
FIGS. 13A-13C , a first interlayer dielectric (ILD) 96 is deposited over the structure illustrated inFIGS. 6A, 12B, and 12A (the processes ofFIGS. 7A-12D do not alter the cross-section illustrated inFIGS. 6A ), respectively. Thefirst ILD 96 may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between thefirst ILD 96 and the epitaxial source/drain regions 92, themask layer 74, and thefirst spacers 81. TheCESL 94 may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the overlying material of thefirst ILD 96. - In
FIGS. 14A and 14B , a planarization process, such as a CMP, may be performed to level the top surface of thefirst ILD 96 with the top surfaces of thedummy gates 76 or themasks 78. The planarization process may also remove themasks 78 on thedummy gates 76, and portions of thefirst spacers 81 along sidewalls of themasks 78. After the planarization process, top surfaces of thedummy gates 76, thefirst spacers 81, and thefirst ILD 96 are level within process variations. Accordingly, the top surfaces of thedummy gate layer 72 are exposed through thefirst ILD 96. In some embodiments, themasks 78 may remain, in which case the planarization process levels the top surface of thefirst ILD 96 with top surface of themasks 78 and thefirst spacers 81. - In
FIGS. 15A and 15B , thedummy gate layer 72 and themask layer 74, if present, are removed in one or more etching steps, so thatsecond recesses 1501 are formed. Portions of the dummy dielectric layers 60 in thesecond recesses 1501 are also be removed. In some embodiments, thedummy gate layer 72 and the dummy dielectric layers 60 are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch thedummy gate layer 72 at a faster rate than thefirst ILD 96 or thefirst spacers 81. Eachsecond recess 1501 exposes and/or overlies portions ofnanostructures 55, which act as channel regions in subsequently completed nano-FETs. Portions of thenanostructures 55 which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions 92. During the removal, the dummy dielectric layers 60 may be used as etch stop layers when thedummy gate layer 72 are etched. The dummy dielectric layers 60 may then be removed after the removal of thedummy gate layer 72. - In
FIGS. 16A and 16B , thefirst nanostructures 52 in the n-type region 50N and thesecond nanostructures 54 in the p-type region 50P are removed extending thesecond recesses 1501. Thefirst nanostructures 52 may be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of thefirst nanostructures 52, while thesecond nanostructures 54, thesubstrate 50, the STI regions 58 remain relatively unetched as compared to thefirst nanostructures 52. In embodiments in which thefirst nanostructures 52 include, e.g., SiGe, and thesecond nanostructures 54A-54C include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove thefirst nanostructures 52 in the n-type region 50N. - The
second nanostructures 54 in the p-type region 50P may be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of thesecond nanostructures 54, while thefirst nanostructures 52, thesubstrate 50, the STI regions 58 remain relatively unetched as compared to thesecond nanostructures 54. In embodiments in which thesecond nanostructures 54 include, e.g., SiGe, and thefirst nanostructures 52 include, e.g., Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove thesecond nanostructures 54 in the p-type region 50P. - In other embodiments, the channel regions in the n-
type region 50N and the p-type region 50P may be formed simultaneously, for example by removing thefirst nanostructures 52 in both the n-type region 50N and the p-type region 50P or by removing thesecond nanostructures 54 in both the n-type region 50N and the p-type region 50P. In such embodiments, channel regions of n-type NSFETs and p-type NSFETS may have a same material composition, such as silicon, silicon germanium, or the like.FIGS. 26A, 26B, and 26C illustrate a structure resulting from such embodiments where the channel regions in both the p-type region 50P and the n-type region 50N are provided by thesecond nanostructures 54 and comprise silicon, for example. - In
FIGS. 17A, 17B, and 18-22 illustrate formation of gatedielectric layers 100 andgate electrodes 102, withFIGS. 17A and 17B illustrating a simplified end result (for clarity) of the structures illustrated in the process steps ofFIGS. 18-22 .FIG. 17A further highlights aregion 1701 of thegate electrode 102 and the gate dielectric layers 100 formed over thesecond nanostructures 54.Region 1701 will be referenced with the discussion of the following figures. - Turning to
FIG. 18 and looking at theregion 1701 inFIG. 17A , this figure illustrates a formation of the gate dielectric layers 100, according to some embodiments. In particular,FIG. 18 illustrates a formation of aninterfacial layer 1801 over thesecond nanostructures 54 and a formation of a gate dielectric 1803 over theinterfacial layer 1801. In an embodiment theinterfacial layer 1801 may be a material such as silicon dioxide (SiO2) formed through a process such as in situ steam generation (ISSG) or a deposition process such as chemical vapor deposition or atomic layer deposition. In another embodiment theinterfacial layer 1801 may be a high-k material such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations of these, or the like, and has a thickness of between about 5 {acute over (Å)} and about 20 {acute over (Å)}, such as about 10 {acute over (Å)}. In embodiments which utilize a deposition process, theinterfacial layer 1801 may be formed conformably, while in embodiments in which ISSG is utilized theinterfacial layer 1801 may be formed along the bottom of the opening without extending along the sidewalls. - In an embodiment the
gate dielectric 1803 comprises a high-k material (e.g., K>=9) such as Ta2O5, Al2O3, Hf oxides, Ta oxides, Ti oxides, Zr oxides, Al oxides, La oxides (e.g., HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO), combinations of these, or the like, deposited through a process such as atomic layer deposition, chemical vapor deposition, or the like. In some embodiments, thegate dielectric 1803 comprises a nitrogen doped oxide dielectric that is initially formed prior to forming a metal content high-K (e.g., K value>13) dielectric material. Thegate dielectric 1803 may be deposited to a thickness of between about 1 nm and about 3 nm, such as about 15 Å although any suitable material and thickness may be utilized. As illustrated, the gate dielectric 1803 wraps around thesecond nanostructures 54, thus forming gate-all-around channels between the epitaxial source/drain regions 92. - Turning to
FIG. 19 , once thegate dielectric 1803 has been formed, thegate electrodes 102 are formed to surround thesecond nanostructures 54 and serve as gate-all-around electrodes of the embodiment device. In some embodiments, thegate electrodes 102 are formed using multiple layers, each layer deposited sequentially adjacent to each other using a highly conformal deposition process such as atomic layer deposition, although any suitable deposition process may be utilized. According to some embodiments, thegate electrodes 102 may comprise a first p-metalwork function layer 1901, a second p-metalwork function layer 2101, aglue layer 2201, and afill material 2203. -
FIG. 19 illustrates a formation of the first p-metalwork function layer 1901 over the gate dielectric 1803 in the eventual formation of thegate electrodes 102, according to some embodiments. The first p-metalwork function layer 1901 may be formed adjacent thegate dielectric 1803. For example, the first p-metalwork function layer 1901 may be formed of a material such as one or more layers of a metallic material such as TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. According to some embodiments, the first p-metalwork function layer 1901 may be formed to a first thickness Th1 of about 10 Å. However, any suitable thickness may be used. - The first p-metal
work function layer 1901 may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used. As such, abase structure 2001 of a metal gate stack with theinterfacial layer 1801, thegate dielectric 1803, and the first p-metalwork function layer 1901 formed to surround thesecond nanostructures 54, according to some embodiments. -
FIG. 20A illustrates anannealing process 2050 for annealing thebase structure 2001 of the metal gate stack, according to some embodiments. Thebase structure 2001 of the metal gate stack can be annealed to increase the electrical work function of the first p-metalwork function layer 1901. In some embodiments, theannealing process 2050 may be a low temperature annealing process (e.g., LMA process) that is performed at a temperature of between about 300° C. and about 500° C., for a duration in a range from about 10 seconds to about 30 minutes. According to some embodiments, theannealing process 2050 is performed at a chamber pressure of between about 0.5 torr and about 10 torr. However, any suitable temperature, duration, and chamber pressure may be used. -
FIG. 20B is a graph illustrating the percentage by atomic weight of oxygen comprised in the base structure 2001 (e.g., theinterfacial layer 1801, thegate dielectric 1803, and the first p-metal work function layer 1901) of the metal gate stack according to different process temperatures and a process time used for theannealing process 2050. In particular, the graph illustrates that prior to theannealing process 2050 the composition of thebase structure 2001 of the metal gate stack is less than 50% oxygen by atomic weight. The graph further illustrates that after theannealing process 2050 for a process time of about 30 minutes, the composition of thebase structure 2001 of the metal gate stack is greater than 50% oxygen by atomic weight for example between about 49.99% to about 54% oxygen by atomic weight. The graph further illustrates that the percent oxygen by atomic weight composition for thebase structure 2001 of the metal gate stack increases as the process temperature increases for theannealing process 2050 for example from about 300° C. to about 450° C. However, any suitable percentage and any suitable temperatures maybe used. According to some embodiments, residual chamber oxygen may be incorporated in thebase structure 2001 during theanneal process 2050. Furthermore, during theanneal process 2050, the oxygen in thegate dielectric 1803 may be driven (e.g., by diffusion) into the underlying materials of thebase structure 2001. - During the
annealing process 2050, the first p-metal work function layer 1901 (e.g., titanium nitride) is doped with oxygen to form pockets of oxygen within the first p-metalwork function layer 1901. In addition, oxygen diffuses from the gate dielectric 1803 (e.g., hafnium oxide) into the interfacial layer 1801 (e.g., silicon oxide) and into the second nanostructures 54 (e.g., silicon). The incorporation of oxygen by theannealing process 2050 increases an electrical work function (eWF) of thebase structure 2001 of the metal gate stack and shifts the metal gate work function towards a P-band edge of thebase structure 2001 of the metal gate stack. According to some embodiments, after performing theannealing process 2050, an interface between the first p-metalwork function layer 1901 and thegate dielectric 1803 has an electrical work function differential. According to DFT simulation data, an electrical work function differential of at least +44.8 may be obtained. -
FIG. 21A illustrates, after theannealing process 2050 has been performed, a formation of the second p-metalwork function layer 2101 adjacent to the first p-metalwork function layer 1901 according to some embodiments. The second p-metalwork function layer 2101 may be formed from a metallic material such as TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. According to some embodiments, the second p-metalwork function layer 2101 may be formed to a second thickness, a ratio of the second thickness Th2 to first thickness Th1 may be a ratio between about 0.5:1 and about 3:1, such as about 2:1. According to some embodiments, the second thickness Th2 may be a thickness of between about 5 Å and about 30 Å, such as about 20 Å. However, any suitable thickness may be used. The metallic material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used. As such, the second p-metalwork function layer 2101 is formed to surround the first p-metalwork function layer 1901, according to some embodiments. -
FIG. 21B is a graph illustrating the electrical work function (eWF) voltage versus a capacitance equivalent thickness (CET) (nm) of a bilayer structure comprising the first p-metalwork function layer 1901 and the second p-metalwork function layer 2101 after theannealing process 2050 has been performed as compared to the eWF voltage of the bilayer structure without theannealing process 2050 having been performed. In particular, the graph illustrates that forming the bilayer structure using theannealing process 2050 increases the eWF of the bilayer structure as compared to forming the bilayer structure without theannealing process 2050. As the eWF of the bilayer structure increases, the threshold voltage (P-Vt) of the bilayer structure is reduced. The graph further illustrates that the eWF of the bilayer structure increases as the CET (nm) increases. For example, a bilayer structure comprising the first p-metalwork function layer 1901 having a first thickness of about 10 A and the second p-metalwork function layer 2101 having a second thickness of about 20 A, the bilayer structure formed without theannealing process 2050 may have an eWF of about 5.00 V around 1.4 nm CET; whereas, the bilayer structure formed with theannealing process 2050 may have an eWF of about 5.02 V around 1.4 nm CET or an increase of about +20 mV around 1.4 nm CET. - Turning to
FIG. 22 , once the first p-metalwork function layer 1901 and the second p-metalwork function layer 2101 have been formed, theglue layer 2201 may be formed in order to help adhere theoverlying fill material 2203 with the underlying materials as well as provide a nucleation layer for the formation of thefill material 2203. In an embodiment theglue layer 2201 may be a material such as titanium nitride (TiN) and may be formed using a similar process such as ALD to a thickness of between about 10 {acute over (Å)} and about 100 {acute over (Å)}, such as about 50 {acute over (Å)}. However, any suitable materials and processes may be utilized. - Also shown in
FIG. 22 , a deposition of thefill material 2203 is illustrated according to some embodiments. Once theglue layer 2201 has been formed, thefill material 2203 is deposited to fill a remainder of the opening. In an embodiment the fill material may be a material such as tungsten, Al, Cu, AlCu, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like, and may be formed using a deposition process such as plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable material may be utilized. - The formation of the gate
dielectric layers 100 in the n-type region 50N and the p-type region 50P may occur simultaneously such that the gatedielectric layers 100 in each region are formed from the same materials, and the formation of thegate electrodes 102 may occur simultaneously such that thegate electrodes 102 in each region are formed from the same materials. Additionally, in some other embodiments, the gatedielectric layers 100 in each region may be formed by distinct processes, such that the gatedielectric layers 100 may be different materials and/or have a different number of layers, and/or thegate electrodes 102 in each region may be formed by distinct processes, such that thegate electrodes 102 may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. - After the filling of the
second recesses 1501, a planarization process, such as a CMP, may be performed to remove the excess portions of the gatedielectric layers 100 and the material of thegate electrodes 102, which excess portions are over the top surface of thefirst ILD 96. The remaining portions of material of thegate electrodes 102 and the gatedielectric layers 100 thus form replacement gate structures of the resulting nano-FETs. Thegate electrodes 102 and the gatedielectric layers 100 may be collectively referred to as “gate structures.” - In
FIGS. 23A-23C , the gate structure (including the gatedielectric layers 100 and the gate electrodes 102) is recessed, so that a recess is formed directly over the gate structure and between opposing portions offirst spacers 81. Agate mask 104 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over thefirst ILD 96. Subsequently formed gate contacts (such as thegate contacts 114, discussed below with respect toFIGS. 23A and 23B ) penetrate through thegate mask 104 to contact the top surface of the recessedgate electrodes 102. - As further illustrated by
FIGS. 23A-23C , asecond ILD 106 is deposited over thefirst ILD 96 and over thegate mask 104. In some embodiments, thesecond ILD 106 is a flowable film formed by FCVD. In some embodiments, thesecond ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. - In
FIGS. 24A-24C , thesecond ILD 106, thefirst ILD 96, theCESL 94, and the gate masks 104 are etched to formthird recesses 108 exposing surfaces of the epitaxial source/drain regions 92 and/or the gate structure. The third recesses 108 may be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, thethird recesses 108 may be etched through thesecond ILD 106 and thefirst ILD 96 using a first etching process; may be etched through the gate masks 104 using a second etching process; and may then be etched through theCESL 94 using a third etching process. A mask, such as a photoresist, may be formed and patterned over thesecond ILD 106 to mask portions of thesecond ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, thethird recesses 108 extend into the epitaxial source/drain regions 92 and/or the gate structure, and a bottom of thethird recesses 108 may be level with (e.g., at a same level, or having a same distance from the substrate), or lower than (e.g., closer to the substrate) the epitaxial source/drain regions 92 and/or the gate structure. AlthoughFIG. 19B illustrate thethird recesses 108 as exposing the epitaxial source/drain regions 92 and the gate structure in a same cross section, in various embodiments, the epitaxial source/drain regions 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts. After thethird recesses 108 are formed,silicide regions 110 are formed over the epitaxial source/drain regions 92. In some embodiments, thesilicide regions 110 are formed by first depositing a metal (not shown) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions 92 (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys, over the exposed portions of the epitaxial source/drain regions 92, then performing a thermal anneal process to form thesilicide regions 110. The un-reacted portions of the deposited metal are then removed, e.g., by an etching process. Althoughsilicide regions 110 are referred to as silicide regions,silicide regions 110 may also be germanide regions, or silicon germanide regions (e.g., regions comprising silicide and germanide). In an embodiment, thesilicide region 110 comprises TiSi, and has a thickness in a range between about 2 nm and about 10 nm. - Next, in
FIGS. 25A-C , source/drain contacts 112 and gate contacts 114 (may also be referred to as contact plugs) are formed in the third recesses 108. The source/drain contacts 112 and thegate contacts 114 may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, the source/drain contacts 112 and thegate contacts 114 each include a barrier layer and a conductive material, and is electrically coupled to the underlying conductive feature (e.g.,gate electrodes 102 and/orsilicide region 110 in the illustrated embodiment). Thegate contacts 114 are electrically coupled to thegate electrodes 102 and may be referred to as gate contacts or gate plugs, and the source/drain contacts 112 are electrically coupled to thesilicide regions 110 and may be referred to as source/drain contacts or source/drain plugs. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material 118 may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of thesecond ILD 106. -
FIGS. 26A-C illustrate cross-sectional views of a device according to some alternative embodiments.FIG. 26A illustrates reference cross-section A-A′ illustrated inFIG. 1 .FIG. 26B illustrates reference cross-section B-B′ illustrated inFIG. 1 .FIG. 26C illustrates reference cross-section C-C′ illustrated inFIG. 1 . InFIGS. 26A-C , like reference numerals indicate like elements formed by like processes as the structure ofFIGS. 22A-C . However, inFIGS. 26A-C , channel regions in the n-type region 50N and the p-type region 50P comprise a same material. For example, thesecond nanostructures 54, which comprise silicon, provide channel regions for p-type NSFETs in the p-type region 50P and for n-type NSFETs in the n-type region 50N. The structure ofFIGS. 26A-C may be formed, for example, by removing thefirst nanostructures 52 from both the p-type region 50P and the n-type region 50N simultaneously; depositing the gatedielectric layers 100 and thegate electrodes 102P (e.g., gate electrode suitable for a p-type NSFET) around thesecond nanostructures 54 in the p-type region 50P; and depositing gatedielectric layers 100 and thegate electrodes 102N (e.g., a gate electrode suitable for a n-type NSFET) around thesecond nanostructures 54 in the n-type region 50N. In such embodiments, materials of the epitaxial source/drain regions 92 may be different in the n-type region 50N compared to the p-type region 50P as explained above. - Embodiments may achieve advantages. For example, during the
annealing process 2050, the first p-metalwork function layer 1901 of thebase structure 2001 is doped with oxygen and oxygen is diffused from the gate dielectric 1803 into theinterfacial layer 1801 and/or diffused into thesecond nanostructures 54. As such, the percentage of oxygen by atomic weight composition for thebase structure 2001 is increased. The incorporation of oxygen by theannealing process 2050 increases an electrical work function (eWF) of thebase structure 2001 of the metal gate stack and shifts the metal gate work function towards a P-band edge of thebase structure 2001 of the metal gate stack. According to some embodiments, after performing theannealing process 2050, an interface between the first p-metalwork function layer 1901 and thegate dielectric 1803 has an electrical work function differential of at least +44.8. Furthermore, according to some embodiments, the eWF of the bilayer structure is increased by using theannealing process 2050 and a P-Vt of the bilayer structure is reduced. - In an embodiment, a method includes forming nanostructures in a multilayer stack; forming a gate dielectric surrounding the nanostructures; forming a first p-metal work function layer surrounding the gate dielectric; after the forming the first p-metal work function layer, performing an anneal process; after performing the anneal process, forming a second p-metal work function layer; and depositing a conductive fill material over the second p-metal work function layer. In an embodiment, the method includes diffusing oxygen into the interlayer dielectric. In an embodiment, prior to performing the anneal process a base structure including the gate dielectric, the first p-metal work function layer, and an interfacial layer includes less than 50% oxygen by atomic weight and after performing the anneal process the base structure includes greater than 50% oxygen by atomic weight. In an embodiment of the method, the diffusing oxygen into the interlayer dielectric increases an electrical work function differential at an interface between the gate dielectric and the p-metal work function layer. In an embodiment of the method, the diffusing oxygen into the interlayer dielectric increases a combined electrical work function of the first p-metal work function layer and the second p-metal work function layer by at least 20 mV. In an embodiment of the method, the forming the first p-metal work function layer includes depositing a titanium nitride material. In an embodiment of the method, the performing the anneal process includes using a process temperature within a range of 300° C. and 500° C.
- In another embodiment, the method includes: forming nanostructures in a multilayer stack; forming an interlayer dielectric surrounding the nanostructures; forming a gate dielectric surrounding the interlayer dielectric; forming a first work function layer surrounding the gate dielectric; diffusing oxygen from the gate dielectric into the interlayer dielectric; after the diffusing, forming a second work function layer adjacent the first work function layer; and forming a gate electrode stack by depositing a conductive fill material over the second work function layer. In an embodiment of the method, the diffusing includes performing an anneal process. In an embodiment of the method, the diffusing the oxygen into the interlayer dielectric increases an electrical work function at an interface between the gate dielectric and the first work function layer. In an embodiment of the method, the forming the interlayer dielectric includes forming silicon oxide. In an embodiment of the method, the forming the gate dielectric includes forming a hafnium oxide material. In an embodiment of the method, the forming the first work function layer includes forming a titanium nitride material. In an embodiment of the method, the anneal process is performed using a process temperature within a range of 300° C. and 500° C.
- In yet another embodiment, a semiconductor device includes: a nanostructure stack; a base structure of a gate stack, the base structure including: an interlayer dielectric surrounding each nanostructure of the nanostructure stack; a gate dielectric surrounding the interlayer dielectric; and a first p-metal work function layer, the base structure having a composition that is greater than 50% oxygen by atomic weight; and a top structure of the gate stack, the top structure including a second p-metal work function layer surrounding the first p-metal work function layer and a conductive fill material disposed over the second p-metal work function layer. In an embodiment of the semiconductor device, the interlayer dielectric includes a silicon oxide material. In an embodiment of the semiconductor device, the gate dielectric includes a hafnium oxide material. In an embodiment of the semiconductor device, the first p-metal work function layer includes a titanium nitride material. In an embodiment of the semiconductor device, an interface between the first p-metal work function layer and the gate dielectric has an electrical work function differential of at least +44.8. In an embodiment of the semiconductor device, an electrical work function of the first p-metal work function layer is shifted towards a P-band edge.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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