CN107039258A - 形成栅极的方法和finfet - Google Patents
形成栅极的方法和finfet Download PDFInfo
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- CN107039258A CN107039258A CN201610845869.5A CN201610845869A CN107039258A CN 107039258 A CN107039258 A CN 107039258A CN 201610845869 A CN201610845869 A CN 201610845869A CN 107039258 A CN107039258 A CN 107039258A
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- grid
- dopant
- dummy grid
- dummy
- interlayer dielectric
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
本发明提供了形成栅极的方法包括:形成伪栅极;横向邻近伪栅极形成层间电介质(ILD);将掺杂剂掺杂到伪栅极和ILD中,其中,伪栅极的表面掺杂剂浓度低于ILD的表面掺杂剂浓度;在将掺杂剂掺杂到伪栅极和ILD中之后,去除伪栅极以形成腔体;以及在腔体中形成栅极。本发明还提供了鳍式场效应晶体管。
Description
技术领域
本发明的实施例涉及半导体技术领域,更具体地,涉及形成栅极的方法和鳍式场效应晶体管。
背景技术
半导体集成电路(IC)工业已经经历了快速发展。在增长的过程中,随着器件部件尺寸或几何结构的减小,半导体器件的功能密度已经增大。这种按比例缩小工艺通常通过提高生产效率、降低成本、和/或改善器件性能来提供益处。然而,这种规模缩小也增加了IC制造工艺的复杂程度。
随着对IC的缩小的几何尺寸的需求,已经引入诸如鳍式场效应晶体管(FinFET)的三维晶体管来替代平面晶体管。然而,器件性能和这种FinFET的产量仍不能满足先进的技术应用的要求。因此,不断寻求形成具有更高的器件性能的FinFET的结构和方法的改进。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种形成栅极的方法,包括:形成伪栅极;横向邻近所述伪栅极形成层间电介质(ILD);将掺杂剂掺杂到所述伪栅极和所述ILD中,其中,所述伪栅极的表面掺杂剂浓度低于所述ILD的表面掺杂剂浓度;在将所述掺杂剂掺杂到所述伪栅极和所述ILD中之后,去除所述伪栅极以形成腔体;以及在所述腔体中形成所述栅极。
根据本发明的另一方面,提供了一种FinFET,包括:鳍结构;栅极,横跨在所述鳍结构上方;源极-漏极区域,位于所述鳍结构中;以及ILD,横向邻近所述栅极并且包括掺杂剂,其中,所述ILD的邻近所述栅极的掺杂剂浓度低于所述ILD的远离所述栅极的掺杂剂浓度。
根据本发明的又一方面,提供了一种FinFET,包括:鳍结构;栅极,横跨在所述鳍结构上方;源极-漏极区域,位于所述鳍结构中;ILD,横向邻近所述栅极并且包括掺杂剂;以及间隔件,横向介于所述栅极与所述ILD之间,其中,由所述间隔件限定的间隔不具有颈部。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减少。
图1是根据本发明的一些实施例的鳍结构和伪栅极的简化的顶视图。
图2A至图2I是根据本发明的一些实施例的沿着图1的截面线AA'截取的形成栅极的各个阶段的截面图。
图3A是根据本发明的一些实施例的图2D的阶段之后的阶段的截面图。
图3B是根据本发明的一些实施例的图3A的阶段之后的阶段的截面图。
具体实施方式
以下公开内容提供了许多不同实施例或实例,用于实现所提供主题的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然,这些仅是实例并且不意欲限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,也可以包括在第一部件和第二部件之间形成附加部件使得第一部件和第二部件不直接接触的实施例。而且,本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外,为了便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位),并且在本文中使用的空间关系描述符可以同样地作相应地解释。
如以上所述,这种FinFET的器件性能和产量仍不能满足先进的技术应用的要求。例如,伪栅极的小顶部关键尺寸(CD)是当前FinFET的成品率递减因子(yield killer)。具体地,在真实栅极替代伪栅极之后,去除真实栅极的一部分以形成开口,并且然后,在开口中并且在栅极上方形成保护层以在随后的孔形成期间保护栅极。孔配置为分别容纳接触塞以用于电连接至源极区域和漏极区域。然而,伪栅极的小顶部CD将导致真实栅极的小顶部CD。由于小CD的工艺限制,所以难以去除栅极的足够厚的部分。因此,形成的保护层可能太薄,并且因此不能在随后的孔形成期间保护栅极,从而导致当前FinFET的器件性能和产量降低。
因此,与当前FinFET的栅极相比,本发明提供形成具有大顶部CD的栅极的方法,其中通过在将掺杂剂掺杂到伪栅极和层间电介质(ILD)中期间控制掺杂浓度以获得伪栅极的合适的轮廓。伪栅极的合适的轮廓有助于进行以后的工艺,并且因此提高当前FinFET的器件性能和产量。下文将详细描述形成具有大顶部CD的栅极和包括该栅极的FinFET的方法的实施例。
本发明提供了形成具有大顶部CD的栅极的方法。图1是根据本发明一些实施例的鳍结构104和伪栅极DG的简化的顶视图。图2A至图2I是根据本发明的一些实施例的沿着图1的截面线AA'截取的形成栅极G的各个阶段的截面图。
首先提供衬底(未示出)。在一些实施例中,衬底包括:元素半导体,包括晶体硅或者晶体锗、多晶硅或多晶锗、和/或无定形结构的硅或无定形结构的锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;任何其他合适的材料和/或它们的组合。在一些实施例中,衬底是块状硅衬底。
在一些实施例中,如图1和图2A所示,通过选择性地蚀刻以上所述的衬底来形成鳍结构104。具体地,在实施例中,去除衬底的多部分以限定从衬底突出的鳍结构104。在一些实施例中,集成地形成衬底和鳍结构104;也就是说,衬底与鳍结构104之间不具有分界线。然而,用于制造鳍结构104的其他的技术是可能的。在一些实施例中,衬底和鳍结构104由相同的材料制成。
在一些实施例中,如图1和图2A所示,隔离结构106形成在鳍结构104之间,诸如浅沟槽隔离(STI)结构。隔离结构106配置为隔离两个鳍结构104。在一些实施例中,隔离结构106由介电材料制成,诸如氧化硅、氮化硅、氮氧化硅、掺氟的硅酸盐玻璃、低k介电材料、任何其他合适的介电材料或它们的组合。
然后,如图1和图2A所示,横跨在鳍结构104上方形成介电层108和伪栅极DG。稍后将去除伪栅极DG以形成腔体,并且然后,将在腔体中形成导电材料以形成真实栅极。在一些实施例中,使用溅射、物理汽相沉积(PVD)、化学汽相沉积(CVD)、金属有机物化学汽相沉积(MOCVD)、分子束外延(MBE)、本领域中已知的并且用于形成介电材料的任何其他的方法或它们的组合在鳍结构104上方形成介电材料(未示出)。在一些实施例中,介电材料由氧化硅、氮化硅、氮氧化硅、碳氮化硅、任何其他合适的介电材料或它们的组合制成。在一些实施例中,在形成介电材料之后,然后通过诸如PVD或CVD的沉积在介电材料上方形成伪栅极材料(未示出)。在一些实施例中,伪栅极材料由多晶硅、无定型硅、任何其他合适的材料或它们的组合制成。在一些实施例中,对伪栅极材料和其下方的介电材料执行诸如光刻和蚀刻工艺的图案化工艺以形成横跨在鳍结构104上方的伪栅极DG和介电层108。
仍参考图1和图2A,在形成伪栅极DG之后,横向邻近伪栅极DG形成间隔件110。在一些实施例中,沉积介电材料(未示出)以覆盖伪栅极DG,并且然后蚀刻介电材料以形成位于伪栅极DG的侧壁上方的间隔件110。在一些实施例中,间隔件110由氧化硅、氮化硅、氮氧化硅、碳氮化硅、任何其他合适的介电材料或它们的组合制成。
参考图2B,源极-漏极区域SDR形成在鳍结构104中。具体地,在形成间隔件110之后,去除鳍结构104的多部分以形成凹槽,并且然后,分别在凹槽中形成源极-漏极区域SDR。在一些实施例中,使用光刻和蚀刻工艺来去除鳍结构104的多部分,这可以包括:形成光刻胶层、图案化光刻胶层以暴露鳍结构104的多部分、以及根据光刻胶层蚀刻鳍结构104的多部分。在一些实施例中,在凹槽中分别外延(epi)生长源极-漏极区域SDR。在一些实施例中,每一个源极-漏极区域SDR都外延生长以从凹槽中突出并且具有比鳍结构104的上表面高的上表面。
参考图2C,在形成源极-漏极区域SDR之后,接触蚀刻停止层(CESL)112形成在源极-漏极区域SDR上方并且横向邻近伪栅极DG。在形成CESL112之后,ILD 114形成在CESL112上方并且横向邻近伪栅极DG。在一些实施例中,使用溅射、PVD、CVD、MOCVD或MBE形成CESL 112。然而,可以可选地使用用于制造CESL 112的其他方法。在一些实施例中,CESL112由氮化硅、氮氧化硅、碳氮化硅、任何其他合适的绝缘材料或它们的组合制成。在一些实施例中,使用溅射、PVD、CVD、MOCVD、MBE、本领域已知的并且用于形成ILD 114的其他方法或它们的组合来形成ILD114。在一些实施例中,ILD 114由氧化硅、氮氧化硅、任何其他合适的绝缘材料或它们的组合制成。
在一些实施例中,在相继形成CESL 112和ILD 114之后,执行平坦化工艺以形成图2C的结构。在一些实施例中,在执行平坦化工艺之后,伪栅极DG的上表面与CESL 112的上表面和ILD 114的上表面共面。在一些实施例中,平坦化工艺包括化学机械抛光(CMP)工艺、研磨工艺、蚀刻工艺或另一合适的材料去除工艺。
参考图2C和图2D,在邻近伪栅极DG形成ILD 114之后,执行第一退火工艺。在一些实施例中,如图2D所示,执行第一退火工艺包括对ILD114执行第一退火工艺以加宽伪栅极DG的上部宽度。这是因为ILD 114在第一退火工艺期间收缩以向伪栅极DG提供拉伸应力,并且因此,伪栅极DG的上部宽度变的更宽。在一些实施例中,如图2D所示,伪栅极DG的上部宽度大于伪栅极DG的下部宽度。本文使用“上部宽度”和“下部宽度”以相比较的方式分别指远离鳍结构104的宽度和靠近鳍结构104的宽度。在一些实施例中,伪栅极DG的上部宽度不小于伪栅极DG的下部宽度。在一些实施例中,在300℃至800℃下执行第一退火工艺。在一些实施例中,在400℃至700℃下执行第一退火工艺。在一些实施例中,执行第一退火工艺的持续时间为1小时至6小时。在一些实施例中,利用水蒸气执行第一退火工艺。在一些实施例中,利用氮执行第一退火工艺。
参考图2E,在执行第一退火工艺之后,执行掺杂工艺。在掺杂工艺中,掺杂剂(未示出)掺杂在伪栅极DG和ILD 114中,其中,伪栅极DG的表面掺杂剂浓度低于ILD 114的表面掺杂剂浓度。在一些实施例中,伪栅极DG的表面掺杂剂浓度为1013离子/立方厘米(ions/cm3)至1016离子/立方厘米。在一些实施例中,伪栅极DG的表面掺杂剂浓度为0。在一些实施例中,ILD 114的表面掺杂剂浓度为1014离子/立方厘米至1017离子/立方厘米。在一些实施例中,ILD 114的表面掺杂剂浓度至少比伪栅极DG的表面掺杂剂浓度大十倍。在一些实施例中,掺杂剂选自由IVA族元素(诸如碳(C)、硅(Si)、锗(Ge)、锡(Sn)或铅(Pb))、VIIIA族元素(诸如氦(He)、氖(Ne)、氩(Ar)、氪(Kr)、氙(Xe)或氡(Rn))和它们的组合构成的组。
仍参考图2E,在执行掺杂工艺之后,执行第二退火工艺以朝向鳍结构104驱动掺杂剂,从而向沟道区域(即,鳍结构104与伪栅极DG重叠的部分)提供压缩应力。压缩应力将影响沟道区域的有效宽度,并且因此提高最终形成的FinFET的器件性能和产量。在一些实施例中,在500℃至1300℃下执行第二退火工艺。在一些实施例中,在700℃至1200℃下执行第二退火工艺。在一些实施例中,执行第二退火工艺的持续时间小于或等于1秒。
在另一方面,在第二退火工艺期间,掺杂剂还可以向伪栅极DG提供压缩应力以使伪栅极DG的宽度变窄。因此,在掺杂工艺期间,伪栅极DG的表面掺杂剂浓度低于ILD 114的表面掺杂剂浓度以向伪栅极DG提供较少的压缩应力,并且因此,在执行第二退火工艺之前和之后,未显著改变伪栅极DG的轮廓。
在一些实施例中,在掺杂工艺期间,邻近伪栅极DG的ILD 114的表面掺杂剂浓度低于远离伪栅极DG的ILD 114的表面掺杂剂浓度以进一步减少对于伪栅极DG的压缩应力。在一些实施例中,在掺杂工艺期间,间隔件110的表面掺杂剂浓度低于邻近伪栅极DG的ILD114的表面掺杂剂浓度。在一些实施例中,在掺杂工艺期间,CESL 112的表面掺杂剂浓度低于邻近伪栅极DG的ILD 114的表面掺杂剂浓度。在一些实施例中,间隔件110的表面掺杂剂浓度低于或等于CESL 112的表面掺杂剂浓度。在一些实施例中,表面掺杂剂浓度从远离伪栅极DG的ILD 114朝向伪栅极DG逐渐减小或逐步减小,并且可以适当地调整该表面掺杂剂浓度以获得伪栅极DG的优化的轮廓。
参考图2E和图2F,在执行第二退火工艺之后,去除伪栅极DG以形成由间隔件110限定的腔体C。在一些实施例中,使用诸如干蚀刻工艺、湿蚀刻工艺、或它们的组合的蚀刻工艺去除伪栅极DG。在一些实施例中,使用氢氟酸、硫酸、臭氧、任何其他合适的化学物质或它们的组合去除伪栅极DG。在一些实施例中,形成的腔体C的上部宽度不小于腔体C的下部宽度。在一些实施例中,形成的腔体C不具有颈部。在一些实施例中,腔体C具有大顶部CD。
参考图2F和图2G,栅极G形成在图2F的腔体C中。在一些实施例中,使用溅射、PVD、CVD、原子层沉积(ALD)、任何其他合适的形成技术或它们的组合来形成栅极G。在一些实施例中,栅极G是单层结构或多层结构。在一些实施例中,栅极G包括钛(Ti)、钽(Ta)、钨(W)、铝(Al)、锆(Zr)、铪(Hf)、钛铝(TiAl)、钽铝(TaAl)、钨铝(WAl)、锆铝(ZrAl)、铪铝(HfAl)、氮化钛(TiN)、氮化钽(TaN)、氮化硅钛(TiSiN)、氮化硅钽(TaSiN)、氮化硅钨(WSiN)、碳化钛(TiC)、碳化钽(TaC)、碳化钛铝(TiAlC)、碳化钽铝(TaAlC)、氮化钛铝(TiAlN)、氮化钽铝(TaAlN)、任何其他合适的含金属材料或它们的组合。
参考图2H,去除栅极G的一部分以形成开口O。由于腔体C具有大顶部CD,所以易于去除栅极G的一部分。在一些实施例中,使用诸如干蚀刻工艺、湿蚀刻工艺、或它们的组合的蚀刻工艺去除栅极G的一部分。
参考图2H和图2I,在开口O中形成保护层116。保护层116配置为在随后的孔形成期间保护栅极G,孔配置为分别容纳接触塞以用于电连接至源极-漏极区域SDR。在一些实施例中,保护层116称为自对准接触件(SAC)。在一些实施例中,使用诸如PVD或CVD的沉积、其他合适的工艺或它们的组合来形成保护层116。在一些实施例中,保护层116由诸如氧化硅、氮化硅、氮氧化硅、碳氮化硅、任何其他合适的介电材料或它们的组合的绝缘材料制成。
值得注意的是,在掺杂工艺期间,如果伪栅极DG的表面掺杂剂浓度等于ILD 114的表面掺杂剂浓度,那么在执行第二退火工艺之前和之后,将显著改变伪栅极DG的轮廓。
图3A是根据本发明的一些实施例的图2D的阶段之后的阶段的截面图。如图2D和图3A所示,在执行第一退火工艺之后,对图2D的结构执行具有基本相同或相同的表面掺杂剂浓度的掺杂工艺,并且然后,执行第二退火工艺。如图3A所示,由于对于伪栅极DG的较大的压缩应力,所以热驱动掺杂剂改变了图2D的伪栅极DG的轮廓以形成颈部。伪栅极DG的颈部不利于进行以后的工艺。
图3B是根据本发明的一些实施例的图3A的阶段之后的阶段的截面图。如图3A和图3B所示,在执行第二退火工艺之后,由栅极G来代替图3A的伪栅极DG,并且然后,去除栅极G的一部分。然而,由于栅极G的颈部,所以难以去除栅极G的足够厚的部分。因此,如图3B所示,形成的开口O具有比图2H的开口O的深度小得多的深度。随后形成的保护层(未示出)可能太薄,并且不能在形成孔期间保护栅极G。
本发明还提供了包括具有大顶部CD的栅极的FinFET。参考图2I,FinFET包括鳍结构104、栅极G、源极-漏极区域SDR和ILD 114,其中邻近栅极G的ILD 114的掺杂剂浓度低于远离栅极G的ILD 114的掺杂剂浓度。
在一些实施例中,鳍结构104是衬底(未示出)的一部分。在一些实施例中,衬底包括:元素半导体,包括晶体硅或晶体锗、多晶硅或多晶锗、和/或无定形结构的硅或无定形结构的锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;任何其他合适的材料和/或它们的组合。在一些实施例中,衬底是块状硅衬底。在一些实施例中,衬底和鳍结构104由相同的材料制成。
栅极G横跨在鳍结构104上方。在一些实施例中,栅极G是单层结构或多层结构。在一些实施例中,栅极G包括Ti、Ta、W、Al、Zr、Hf、TiAl、TaAl、WAl、ZrAl、HfAl、TiN、TaN、TiSiN、TaSiN、WSiN、TiC、TaC、TiAlC、TaAlC、TiAlN、TaAlN、任何其他合适的材料或它们的组合。
源极-漏极区域SDR位于鳍结构104中。在一些实施例中,源极-漏极区域SDR是外延结构。在一些实施例中,对于n型FinFET而言,源极-漏极区域SDR包括诸如磷(P)、砷(As)、锑(Sb)、铋(Bi)、硒(Se)、碲(Te)的n型掺杂剂、另一合适的n型掺杂剂或它们的组合。在一些实施例中,对于n型FinFET而言,源极-漏极区域SDR包括硅磷(SiP)。在一些实施例中,对于p型FinFET而言,源极-漏极区域SDR包括诸如硼、二氟化硼的p型掺杂剂、另一合适的p型掺杂剂或它们的组合。在一些实施例中,对于p型FinFET而言,源极-漏极区域SDR包括硅锗(SiGe)。
ILD 114横向邻近栅极G并且包括掺杂剂,其中,邻近栅极G的ILD 114的掺杂剂浓度低于远离栅极G的ILD 114的掺杂剂浓度。在一些实施例中,ILD 114的邻近栅极G的部分的掺杂剂浓度低于ILD 114的具有与ILD 114的该部分相同深度并且远离栅极G的另一部分的掺杂剂浓度。在一些实施例中,掺杂剂选自由IVA族元素(诸如C、Si、Ge、Sn或Pb)、VIIIA族元素(诸如He、Ne、Ar、Kr、Xe或Rn)和它们的组合构成的组。在一些实施例中,ILD 114由氧化硅、氮化硅、氮氧化硅、碳氮化硅、任何其他合适的介电材料或它们的组合制成。
在一些实施例中,FinFET还包括介于鳍结构104与栅极G之间并且用作栅极介电层的介电层108。在一些实施例中,介电层108包括氧化硅、氮化硅、氮氧化硅、碳氮化硅、任何其他合适的介电材料或它们的组合。
在一些实施例中,FinFET还包括位于源极-漏极区域SDR上方并且横向介于栅极G与ILD 114之间的CESL 112。在一些实施例中,CESL 112的掺杂剂浓度低于邻近栅极G的ILD114的掺杂剂浓度。在一些实施例中,CESL 112的一部分的掺杂剂浓度低于ILD 114的具有与CESL 112的该部分相同深度并且邻近栅极G的部分的掺杂剂浓度。在一些实施例中,CESL112由氧化硅、氮化硅、氮氧化硅、碳氮化硅、任何其他合适的介电材料或它们的组合制成。
在一些实施例中,FinFET还包括横向介于栅极G与CESL 112之间的间隔件110。在一些实施例中,间隔件110的掺杂剂浓度低于邻近栅极G的ILD 114的掺杂剂浓度。在一些实施例中,间隔件110的一部分的掺杂剂浓度低于ILD 114的具有与间隔件110的该部分相同深度并且邻近栅极G的部分的掺杂剂浓度。在一些实施例中,间隔件110的掺杂剂浓度低于或等于CESL 112的掺杂剂浓度。在一些实施例中,间隔件110的一部分的掺杂剂浓度低于或等于CESL 112的具有与间隔件110的该部分相同深度的部分的掺杂剂浓度。在一些实施例中,间隔件110由氧化硅、氮化硅、氮氧化硅、碳氮化硅、任何其他合适的介电材料或它们的组合制成。
在一些实施例中,由间隔件110限定的间隔(space,又称空隙或空间)S不具有颈部。在一些实施例中,沿着间隔S的侧壁共形地形成栅极G的多层结构的每一层(未示出)。在一些实施例中,由间隔件110限定的间隔S的上部宽度不小于间隔S的下部宽度。
在一些实施例中,FinFET还包括位于栅极G上方的保护层116。在一些实施例中,保护层116由诸如氧化硅、氮化硅、氮氧化硅、碳氮化硅、任何其他合适的介电材料或它们的组合的绝缘材料制成。
本发明还提供了包括具有大顶部CD的栅极的FinFET。参考图2I,FinFET包括鳍结构104、栅极G、源极-漏极区域SDR、ILD 114和间隔件110,其中,由间隔件110限定的间隔S不具有颈部。鳍结构104、栅极G、源极-漏极区域SDR、ILD 114和间隔件110的实施例可以与以上示出的那些实施例相同,并且因此本文中不再重复。
在一些实施例中,间隔S包括上部(未标记)和位于上部下方的下部(未标记),并且上部具有远离鳍结构104增大的宽度。在一些实施例中,ILD 114和间隔件110包括掺杂剂,并且间隔件110的掺杂剂浓度低于ILD114的掺杂剂浓度。在一些实施例中,间隔件110的一部分的掺杂剂浓度低于ILD 114的具有与间隔件110的该部分相同深度的部分的掺杂剂浓度。在一些实施例中,掺杂剂选自由IVA族元素(诸如C、Si、Ge、Sn或Pb)、VIIIA族元素(诸如He、Ne、Ar、Kr、Xe或Rn)和它们的组合所构成的组。
根据一些实施例,形成栅极的方法包括:形成伪栅极;横向邻近伪栅极形成ILD;将掺杂剂掺杂到伪栅极和ILD中,其中,伪栅极的表面掺杂剂浓度低于ILD的表面掺杂剂浓度;在将掺杂剂掺杂进伪栅极和ILD中之后,去除伪栅极以形成腔体;以及在腔体中形成栅极。
优选地,ILD的邻近所述伪栅极的表面掺杂剂浓度低于ILD的远离所述伪栅极的表面掺杂剂浓度。
优选地,形成栅极的方法,还包括:在横向邻近所述伪栅极形成所述ILD之后并且在将所述掺杂剂掺杂到所述伪栅极和所述ILD中之前,执行第一退火工艺。
优选地,执行所述第一退火工艺包括:对所述ILD执行所述第一退火工艺以加宽所述伪栅极的上部宽度。
优选地,形成栅极的方法,还包括:在将所述掺杂剂掺杂到所述伪栅极和所述ILD中之后并且在去除所述伪栅极之前,执行第二退火工艺。
优选地,形成栅极的方法,还包括:在横向邻近所述伪栅极形成所述ILD之前,横向邻近所述伪栅极形成接触蚀刻停止层(CESL)。
优选地,形成栅极的方法,还包括:在横向邻近所述伪栅极形成所述CESL之前,横向邻近所述伪栅极形成间隔件。
优选地,所述腔体的上部宽度不小于所述腔体的下部宽度。
优选地,所述腔体不具有颈部。
优选地,所述掺杂剂选自由IVA族元素、VIIIA族元素和它们的组合所构成的组。
优选地,形成栅极的方法还包括:去除所述栅极的一部分以形成开口;以及在所述开口中形成保护层。
根据一些实施例,FinFET包括鳍结构、栅极、源极-漏极区域和ILD。栅极横跨在鳍结构上方。源极-漏极区域位于鳍结构中。ILD横向邻近栅极并且包括掺杂剂,其中,邻近栅极的ILD的掺杂剂浓度低于远离栅极的ILD的掺杂剂浓度。
优选地,FinFET还包括横向介于所述栅极与所述ILD之间的CESL。
优选地,所述CESL的掺杂剂浓度低于所述ILD的邻近所述栅极的掺杂剂浓度。
优选地,FinFET还包括横向介于所述栅极与所述CESL之间的间隔件。
优选地,所述间隔件的掺杂剂浓度低于所述ILD的邻近所述栅极的掺杂剂浓度。
优选地,由所述间隔件限定的间隔不具有颈部。
根据一些实施例,FinFET包括鳍结构、栅极、源极-漏极区域、ILD和间隔件。栅极横跨在鳍结构上方。源极-漏极区域位于鳍结构中。ILD横向邻近栅极并且包括掺杂剂。间隔件横向介于栅极与ILD之间,其中,由间隔件限定的间隔不具有颈部。
优选地,所述间隔件包括掺杂剂,并且所述间隔件的掺杂剂浓度低于所述ILD的掺杂剂浓度。
优选地,所述掺杂剂选自由IVA族元素、VIIIA族元素和它们的组合所构成的组。
以上论述了若干实施例的部件,使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种形成栅极的方法,包括:
形成伪栅极;
横向邻近所述伪栅极形成层间电介质(ILD);
将掺杂剂掺杂到所述伪栅极和所述层间电介质中,其中,所述伪栅极的表面掺杂剂浓度低于所述层间电介质的表面掺杂剂浓度;
在将所述掺杂剂掺杂到所述伪栅极和所述层间电介质中之后,去除所述伪栅极以形成腔体;以及
在所述腔体中形成所述栅极。
2.根据权利要求1所述的形成栅极的方法,其中,层间电介质的邻近所述伪栅极的表面掺杂剂浓度低于层间电介质的远离所述伪栅极的表面掺杂剂浓度。
3.根据权利要求1所述的形成栅极的方法,还包括:在横向邻近所述伪栅极形成所述层间电介质之后并且在将所述掺杂剂掺杂到所述伪栅极和所述层间电介质中之前,执行第一退火工艺。
4.根据权利要求3所述的形成栅极的方法,其中,执行所述第一退火工艺包括:对所述层间电介质执行所述第一退火工艺以加宽所述伪栅极的上部宽度。
5.根据权利要求3所述的形成栅极的方法,还包括:在将所述掺杂剂掺杂到所述伪栅极和所述层间电介质中之后并且在去除所述伪栅极之前,执行第二退火工艺。
6.根据权利要求1所述的形成栅极的方法,还包括:在横向邻近所述伪栅极形成所述层间电介质之前,横向邻近所述伪栅极形成接触蚀刻停止层(CESL)。
7.根据权利要求6所述的形成栅极的方法,还包括:在横向邻近所述伪栅极形成所述接触蚀刻停止层之前,横向邻近所述伪栅极形成间隔件。
8.根据权利要求1所述的形成栅极的方法,其中,所述腔体的上部宽度不小于所述腔体的下部宽度。
9.一种鳍式场效应晶体管,包括:
鳍结构;
栅极,横跨在所述鳍结构上方;
源极-漏极区域,位于所述鳍结构中;以及
层间电介质,横向邻近所述栅极并且包括掺杂剂,其中,所述层间电介质的邻近所述栅极的掺杂剂浓度低于所述层间电介质的远离所述栅极的掺杂剂浓度。
10.一种鳍式场效应晶体管,包括:
鳍结构;
栅极,横跨在所述鳍结构上方;
源极-漏极区域,位于所述鳍结构中;
层间电介质,横向邻近所述栅极并且包括掺杂剂;以及
间隔件,横向介于所述栅极与所述层间电介质之间,其中,由所述间隔件限定的间隔不具有颈部。
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CN113745218A (zh) * | 2020-08-14 | 2021-12-03 | 台湾积体电路制造股份有限公司 | 半导体器件和形成半导体器件的方法 |
CN113745218B (zh) * | 2020-08-14 | 2023-09-19 | 台湾积体电路制造股份有限公司 | 半导体器件和形成半导体器件的方法 |
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US20170133509A1 (en) | 2017-05-11 |
US10062787B2 (en) | 2018-08-28 |
TW201721726A (zh) | 2017-06-16 |
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