CN104269358A - 半导体器件的制备方法 - Google Patents
半导体器件的制备方法 Download PDFInfo
- Publication number
- CN104269358A CN104269358A CN201410472750.9A CN201410472750A CN104269358A CN 104269358 A CN104269358 A CN 104269358A CN 201410472750 A CN201410472750 A CN 201410472750A CN 104269358 A CN104269358 A CN 104269358A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- source
- dielectric layer
- preparation
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims description 54
- 150000002500 ions Chemical class 0.000 claims description 53
- 238000000137 annealing Methods 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 34
- 230000015572 biosynthetic process Effects 0.000 claims description 33
- 239000011229 interlayer Substances 0.000 claims description 31
- 238000002347 injection Methods 0.000 claims description 26
- 239000007924 injection Substances 0.000 claims description 26
- 230000005764 inhibitory process Effects 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 230000000694 effects Effects 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 7
- 230000007423 decrease Effects 0.000 abstract description 2
- 230000001629 suppression Effects 0.000 abstract 1
- 229940090044 injection Drugs 0.000 description 19
- 239000000463 material Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical class [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明提出了一种半导体器件的制备方法,在半导体衬底内形成非晶化区,然后将半导体器件中的源漏区形成在非晶化区内,非晶化区能够抑制源漏区末端缺陷的生成,从而能够很好的降低半导体器件源漏区和半导体衬底之间的漏电;此外,在去除虚拟栅结构之后,在沟道区内形成短沟道抑制区,能够抑制半导体器件的短沟道效应,满足器件特征尺寸不断减小的需求。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种半导体器件的制备方法。
背景技术
随着半导体工业的进步以及摩尔定律的发展,MOS(金属氧化物半导体)器件的特征尺寸和深度不断缩小,特别是进入到65纳米及以下节点,MOS器件沟道越来越短,短沟道效应(SCE)越来越严重,源/漏的DIBL(感应势垒降低)漏电严重。
由于特征尺寸和深度不断缩小,会要求源/漏区以及源/漏极延伸区(Source/Drain Extension)均相应地变浅,结深低于100nm的掺杂结通常被称为超浅结(USJ),超浅结可以更好的改善器件的短沟道效应。因此,随着器件特征尺寸越来越小,对超浅结的需求越来越大。为了形成超浅结,需要进行预注入,进行非晶化。
具体的,现有技术中,通常以栅极结构为掩膜,用硼(或BF2)、砷等离子依次垂直或一定角度注入到半导体衬底中形成超浅掺杂源/漏区(LDD)及源/漏极延伸区,达到MOS器件的超浅结的目的。这种LDD离子注入技术利用硼(或BF2)、砷等离子超低能注入。这种注入会使得衬底由晶体变为非晶体,并且在非晶体/晶体界面之间产生大量严重的缺陷(一般成为末端区缺陷,EORDefects)。在随后的退火处理和半导体器件的激活期间,EOR缺陷很难被退火修复,进而引发严重的问题:一方面,这种EOR缺陷会使先前注入的锗、硼(或BF2)离子的扩散增强,增大短沟道效应,不利于超浅结的形成;另一方面,形成的非结晶层再结晶,EOR缺陷会溶解向器件结构表面有效迁移的半导体间隙原子,易引发瞬时增强扩散效应(TED),造成短沟道器件特性退化和结漏电更大。
因此,随着器件尺寸及性能的进一步提高,结漏电现象以及短沟道效应是超浅结技术越来越需要解决的问题。
发明内容
本发明的目的在于提供一种半导体器件的制备方法,能够在降低短沟道效应的同时,也降低结漏电。
为了实现上述目的,本发明提出了一种半导体器件的制备方法,所述方法包括步骤:
提供半导体衬底,所述半导体衬底内形成有非晶化区,所述半导体衬底上形成有虚拟栅极结构和源漏区,所述源漏区形成于所述非晶化区内;
刻蚀去除所述虚拟栅极结构,暴露出所述半导体衬底的沟道区;
在所述半导体衬底的沟道区内形成短沟道抑制区;
在所述半导体衬底的沟道区上形成栅极结构。
与现有技术相比,本发明的实施方式在半导体衬底内形成非晶化区,然后将半导体器件中的源漏区形成在非晶化区内,非晶化区的形成可以使得源漏区在低温环境下外延生长并实现掺杂的激活,低温能够抑制源漏区内注入离子的扩散,从而能够很好的降低半导体器件源漏区和半导体衬底之间的漏电;此外,在去除虚拟栅结构之后,在沟道区内形成短沟道抑制区,能够抑制半导体器件的短沟道效应,满足器件特征尺寸不断减小的需求。
进一步的,所述非晶化区采用离子注入形成,注入的离子为非电活性离子。
进一步的,所述源漏区采用离子注入形成,注入的离子与衬底掺杂的离子互为反型离子,且所述源漏区的注入深度小于所述非晶化区的注入深度。
进一步的,所述短沟道抑制区采用离子注入形成,注入的离子与衬底掺杂的离子为同型离子,且所述短沟道抑制区的注入深度小于所述非晶化区的注入深度。
与现有技术相比,本发明的实施方式形成的短沟道抑制区与源漏区的注入离子互为反型离子,短沟道抑制区作为阻碍区能够很好的抑制形成在非晶化区内的源漏极之间发生短沟道效应。
进一步的,在形成短沟道抑制区后,形成栅极结构之前进行退火处理,所述退火处理温度不超过600℃。
本发明的实施方式采用温度不超过600℃的低温进行退火处理,可以防止温度过高导致源漏区内的离子大幅扩散,从而避免形成的半导体器件出现源漏区漏电现象,进而提高形成的半导体器件的性能。
进一步的,形成所述虚拟栅极结构的步骤包括:
在所述半导体衬底上依次形成虚拟栅介质层及虚拟栅极;
在所述虚拟栅介质层及虚拟栅极的两侧形成源漏延伸区;
在所述虚拟栅介质层及虚拟栅极的两侧壁形成侧墙。
进一步的,在形成源漏区之后,刻蚀去除虚拟栅极结构之前,在所述侧墙两侧及半导体衬底表面形成第一层间介质层。
进一步的,在形成栅极结构后,在所述第一层间介质层和栅极结构的表面形成第二层间介质层。
进一步的,形成所述侧墙、第一层间介质层及第二层间介质层的温度均不超过500℃。
同样的,本发明的实施方式采用温度不超过500℃的低温形成侧墙、第一层间介质层及第二层间介质层,也是为了防止温度过高致使源漏区内的离子大幅扩散,从而避免形成的半导体器件会出现源漏区漏电现象,进而提高形成的半导体器件的性能。
进一步的,在形成所述第二层间介质层后,进行退火处理,所述退火处理温度不超过600℃。
进一步的,刻蚀所述第二层间介质层和第一层间介质层,形成通孔,所述通孔暴露出所述源漏区和栅极的表面。
进一步的,在所述通孔内暴露出的源漏区和栅极表面形成自对准硅化物。
进一步的,在形成所述自对准硅化物后采用退火处理,所述退火处理温度不超过600℃。
本发明的实施方式在形成自对准硅化物后仅采用一次退火处理便能够在激活源漏区延伸区、源漏区及短沟道抑制区的离子的同时,还能够使自对准硅化物在退火后获得更加稳定的性能,同样的,退火处理采用的温度不超过600℃,可以避免形成的半导体器件出现源漏区漏电现象,进而提高形成的半导体器件的性能。
附图说明
图1为本发明一实施例中半导体器件的制备方法的流程图;
图2至图14为本发明一实施例中半导体器件制备过程中的剖面示意图。
具体实施方式
下面将结合示意图对本发明的半导体器件的制备方法进行更详细的描述,其中表示了本发明的优选实施例,应该理解本领域技术人员可以修改在此描述的本发明,而仍然实现本发明的有利效果。因此,下列描述应当被理解为对于本领域技术人员的广泛知道,而并不作为对本发明的限制。
为了清楚,不描述实际实施例的全部特征。在下列描述中,不详细描述公知的功能和结构,因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中,必须做出大量实施细节以实现开发者的特定目标,例如按照有关系统或有关商业的限制,由一个实施例改变为另一个实施例。另外,应当认为这种开发工作可能是复杂和耗费时间的,但是对于本领域技术人员来说仅仅是常规工作。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明的第一实施方式涉及一种半导体器件的制备方法。具体流程如图1所示,包括步骤:
S100:提供半导体衬底,半导体衬底内形成有非晶化区,半导体衬底上形成有虚拟栅极结构和源漏区,源漏区形成于非晶化区内;
具体的,请参考图2至图7,在步骤S100中,形成虚拟栅极结构的步骤包括:
提供半导体衬底10,在半导体衬底10内形成非晶化区20,其中,半导体衬底10可以为单晶硅、多晶硅、绝缘体上硅、Ge(锗)或者III-V族等常见的半导体材料,在半导体衬底10内设有多个浅沟槽隔离11,浅沟槽隔离11可以为二氧化硅,用于隔离不同半导体器件,如图2所示;非晶化区20采用离子注入方式形成,注入的离子为非电活性离子,例如注入的离子为Ge或者Si(硅)等;且非晶化区20的深度大于后续形成的所有离子的深度,包括源漏区的深度,如图3所示;
在半导体衬底10上依次形成虚拟栅介质层31及虚拟栅极32,其中,虚拟栅介质层31的材质为二氧化硅或氮化硅,可以采用化学气相沉积方式形成,确保沉积温度小于等于500度,且虚拟栅介质层31的材质与后续形成的侧墙的材质不同,有利于刻蚀工艺,虚拟栅极32的材质为多晶硅或其它导电材料,如图4所示;
在虚拟栅介质层31及虚拟栅极32的两侧形成源漏延伸区41,源漏延伸区41位于半导体衬底10内,也位于非晶化区20内,如图5所示;源漏延伸区41采用离子注入方式形成,对于N型衬底,注入的离子为B(硼)或BF2(氟化硼),对于P型衬底,注入的离子为As(砷)或P(磷),源漏延伸区41的注入深度通常较浅,因此注入离子的能量一般也较小,通常可以根据不同的需要来选择注入离子的能量;
在虚拟栅介质层31及虚拟栅极32的两侧壁形成侧墙33,如图6所示;侧墙33的材质为二氧化硅、氮化硅或两者组合(例如ONO组合),为了后续刻蚀需要,保证侧墙33的材质与虚拟栅介质层31材质具有较大的刻蚀选择比,两者材质应不同,同样的,可以采用化学气相沉积形成侧墙33,确保沉积过程中的温度不高于500度;
在虚拟栅介质层31及虚拟栅极32的两侧形成源漏区42,如图7所示;源漏区42也采用离子注入方式形成,对于N型衬底,注入的离子为B或BF2,对于P型衬底,注入的离子为As或P,即其注入的类型和源漏延伸区41的离子注入一致,不同的是源漏区42的深度比源漏延伸区41要深,但是浅于非晶化区20,因此,源漏区42相比于源漏延伸区41的离子注入仅仅是注入剂量和能量不同。将源漏延伸区41、源漏区42均形成于非晶化区20内,能够抑制源漏延伸区41、源漏区42注入离子的扩散,从而能够很好的降低半导体器件源漏区及半导体衬底的漏电。
S200:刻蚀去除虚拟栅极结构,暴露出半导体衬底10的沟道区;
请参考图8,在步骤S200中,在形成源漏区42之后,刻蚀去除虚拟栅极结构之前,在侧墙33两侧及半导体衬底10的表面形成第一层间介质层51,用于保护后续刻蚀不伤害半导体衬底10的表面以及侧墙33。形成第一层间介质层51的步骤包括:在半导体衬底10的浅沟槽隔离11、侧墙33和虚拟栅极32的表面形成第一层间介质层51;接着,采用化学机械研磨(CMP)去除部分第一层间介质层51,直至暴露出虚拟栅极32的表面。第一层间介质层51的材质可以为二氧化硅或者氮化硅等绝缘材料,采用化学气相沉积方式形成,同样的,确保形成过程中温度不高于500度,防止离子扩散。
接着,以第一层间介质层51为掩模,采用干法刻蚀依次去除虚拟栅极32及虚拟栅介质层31,暴露出半导体衬底10内的沟道区,即位于原虚拟栅介质层31下方的半导体衬底10。
S300:在半导体衬底10的沟道区内形成短沟道抑制区60;
请参考图10,在步骤S300中,在半导体衬底10的沟道区内形成短沟道抑制区60,短沟道抑制区60采用离子注入形成,注入的离子与源漏区42注入的离子互为反型离子,若注入源漏区42的离子为III族离子,则注入短沟道抑制区60的离子为V族离子,反之亦然。短沟道抑制区60的注入深度远小于非晶化区20的深度,形成的短沟道抑制区60能够很好的抑制短沟道效应(SCE),确保形成的半导体器件的性能,可以满足特征尺寸不断减小的需求,注入离子的能量和剂量均可以根据制备不同尺寸的半导体器件进行选择,在此不做限定。
例如,在本实施例中,源漏区42注入的离子为P,短沟道抑制区60的注入离子为BF2,剂量可以为1E15cm-2,能量可以为1keV。为了保证非晶化区20深度远大于源漏区42,非晶化区20注入的离子为Ge,计量可以为1E15cm-2,能量可以为50keV。
在本实施例中,在形成短沟道抑制区60后,进行退火处理,退火处理用于激活注入在源漏延伸区41、源漏区42及短沟道抑制区60内的离子;此外,退火处理的温度不超过600℃,可以采用低温微波退火等低温退火方式实现,可以防止温度过高导致源漏区内的离子大幅扩散,从而避免形成的半导体器件出现源漏区漏电现象,进而提高形成的半导体器件的性能。
S400:在半导体衬底10的沟道区上形成栅极结构;
请参考图11,在步骤S400中,重新形成的栅极结构包括依次形成于半导体衬底10的沟道区上的栅介质层34和栅极35,栅介质层34的材质为SiO2(二氧化硅)、Si3N4(氮化硅)或HfO2(二氧化铪)等材料,栅极35的材质为多晶硅、TiN(氮化钛)或TaN(氮化钽)等导电材料,同样的,在形成栅介质层34和栅极35过程中的温度不高于500度。
请参考图12,在本实施例中,在形成栅极结构后,在第一层间介质层51和栅极35表面形成第二层间介质层52,形成第二层间介质层52的温度不超过500℃,其材质与第一层间介质层51一致。
请参考图13,依次刻蚀第二层间介质层52和第一层间介质层51,形成通孔70,通孔70暴露出源漏区42和栅极35的表面,用于后续形成通孔连线与半导体器件进行导通。
请参考图14,为了使后续形成的通孔连线与源漏区42和栅极35具有良好的接触,因此需要在源漏区42和栅极35的表面均形成一层自对准硅化物71,形成自对准硅化物71所需要沉积的金属材质为Ti(钛)、Ni(镍)或Co(钴)等。
本发明的第二实施方式涉及一种半导体器件的制备方法。第二实施方式与第一实施方式大致相同,主要区别之处在于:在第一实施方式中,在形成短沟道抑制区后,进行退火处理。而在本发明第二实施方式中,退火处理在形成第二层间介质层之后再进行,用于激活所有注入的元素,同样的,退火处理可以采用低温微波退火等低温退火方式实现。
另外,在本实施例中,源漏区42注入的离子为P,短沟道抑制区60的注入离子为BF2,剂量可以为1E15cm-2,能量可以为1keV。为了保证非晶化区20深度远大于源漏区42,非晶化区20注入的离子为Ge,计量可以为1E15cm-2,能量可以为50keV。
本发明的第二实施方式涉及一种半导体器件的制备方法。第三实施方式与第一实施方式大致相同,主要区别之处在于:在第一实施方式中,在形成短沟道抑制区后,进行退火处理。而在本发明第三实施方式中,在形成自对准硅化物后采用退火处理,同样的,退火处理可以采用低温微波退火等低温退火方式实现。
在本实施例中,为了使形成的自对准硅化物71更加稳定,可以在形成后对其进行退火处理,同样的确保退火处理温度不高于600度,在形成自对准硅化物71后只需进行一次退火处理即可在将自对准硅化物71变得更加稳定的同时,还能够一次性将半导体器件内所有注入的元素激活,减少了工艺步骤,达到节省成本的目的。
综上,在本发明实施例提供的半导体器件的制备方法中,在半导体衬底内形成非晶化区,然后将半导体器件中的源漏区形成在非晶化区内,非晶化区能够抑制源漏区内注入离子的扩散,从而能够很好的降低半导体器件源漏区和半导体衬底之间的漏电;此外,在去除虚拟栅结构之后,在沟道区内形成短沟道抑制区,能够抑制半导体器件的短沟道效应,满足器件特征尺寸不断减小的需求。进一步的,采用温度不超过600℃的低温进行退火处理,可以防止温度过高导致源漏区内的离子大幅扩散,从而避免形成的半导体器件出现源漏区漏电现象,进而提高形成的半导体器件的性能。此外,采用温度不超过500℃的低温形成侧墙、第一层间介质层及第二层间介质层,也是为了防止温度过高致使源漏区内的离子大幅扩散,从而避免形成的半导体器件会出现源漏区漏电现象,进而提高形成的半导体器件的性能。
上述仅为本发明的优选实施例而已,并不对本发明起到任何限制作用。任何所属技术领域的技术人员,在不脱离本发明的技术方案的范围内,对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动,均属未脱离本发明的技术方案的内容,仍属于本发明的保护范围之内。
Claims (13)
1.一种半导体器件的制备方法,其特征在于,包括步骤:
提供半导体衬底,所述半导体衬底内形成有非晶化区,所述半导体衬底上形成有虚拟栅极结构和源漏区,所述源漏区形成于所述非晶化区内;
刻蚀去除所述虚拟栅极结构,暴露出所述半导体衬底的沟道区;
在所述半导体衬底的沟道区内形成短沟道抑制区;
在所述半导体衬底的沟道区上形成栅极结构。
2.如权利要求1所述的半导体器件制备方法,其特征在于,所述非晶化区采用离子注入形成,注入的离子为非电活性离子。
3.如权利要求1所述的半导体器件制备方法,其特征在于,所述源漏区采用离子注入形成,注入的离子与衬底掺杂的离子互为反型离子,且所述源漏区的注入深度小于所述非晶化区的深度。
4.如权利要求1所述的半导体器件的制备方法,其特征在于,所述短沟道抑制区采用离子注入形成,注入的离子与衬底掺杂的离子为同型离子,且所述短沟道抑制区的注入深度小于所述非晶化区的深度。
5.如权利要求1所述的半导体器件的制备方法,其特征在于,在形成短沟道抑制区后,形成栅极结构之前,进行退火处理,所述退火处理温度不超过600℃。
6.如权利要求1所述的半导体器件的制备方法,其特征在于,形成所述虚拟栅极结构的步骤包括:
在所述半导体衬底上依次形成虚拟栅介质层及虚拟栅极;
在所述虚拟栅介质层及虚拟栅极的两侧形成源漏延伸区;
在所述虚拟栅介质层及虚拟栅极的两侧壁形成侧墙。
7.如权利要求6所述的半导体器件的制备方法,其特征在于,在形成源漏区之后,刻蚀去除虚拟栅极结构之前,在所述侧墙两侧及半导体衬底表面形成第一层间介质层。
8.如权利要求7所述的半导体器件的制备方法,其特征在于,在形成栅极结构后,在所述第一层间介质层和栅极结构的表面形成第二层间介质层。
9.如权利要求8所述的半导体器件的制备方法,其特征在于,形成所述侧墙、第一层间介质层及第二层间介质层的温度均不超过500℃。
10.如权利要求9所述的半导体器件的制备方法,其特征在于,在形成所述第二层间介质层后,进行退火处理,所述退火处理温度不超过600℃。
11.如权利要求7所述的半导体器件的制备方法,其特征在于,刻蚀所述第二层间介质层和第一层间介质层,形成通孔,所述通孔暴露出所述源漏区和栅极的表面。
12.如权利要求11所述的半导体器件的制备方法,其特征在于,在所述通孔内暴露出的源漏区和栅极表面形成自对准硅化物。
13.如权利要求12所述的半导体器件的制备方法,其特征在于,在形成所述自对准硅化物后采用退火处理,所述退火处理温度不超过600℃。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410472750.9A CN104269358A (zh) | 2014-09-16 | 2014-09-16 | 半导体器件的制备方法 |
US14/854,763 US20160079389A1 (en) | 2014-09-16 | 2015-09-15 | Preparation method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410472750.9A CN104269358A (zh) | 2014-09-16 | 2014-09-16 | 半导体器件的制备方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104269358A true CN104269358A (zh) | 2015-01-07 |
Family
ID=52160869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410472750.9A Pending CN104269358A (zh) | 2014-09-16 | 2014-09-16 | 半导体器件的制备方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20160079389A1 (zh) |
CN (1) | CN104269358A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105390447A (zh) * | 2015-10-26 | 2016-03-09 | 上海华力微电子有限公司 | 一种用于虚拟栅极的氮化硅制备方法 |
CN106340440A (zh) * | 2015-07-08 | 2017-01-18 | 力晶科技股份有限公司 | 半导体元件的制造方法 |
CN106935490A (zh) * | 2015-12-31 | 2017-07-07 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法、电子装置 |
CN112420752A (zh) * | 2019-08-20 | 2021-02-26 | 复旦大学 | 基于半导体衬底的新型单晶体管像素传感器及制备方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9577102B1 (en) * | 2015-09-25 | 2017-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming gate and finFET |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060220114A1 (en) * | 2005-03-30 | 2006-10-05 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
WO2011075991A1 (zh) * | 2009-12-23 | 2011-06-30 | 中国科学院微电子研究所 | 高性能半导体器件及其形成方法 |
CN102386095A (zh) * | 2010-08-31 | 2012-03-21 | 中国科学院微电子研究所 | 半导体结构的制造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6184112B1 (en) * | 1998-12-02 | 2001-02-06 | Advanced Micro Devices, Inc. | Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile |
US6214654B1 (en) * | 1999-01-27 | 2001-04-10 | Advanced Micro Devices, Inc. | Method for forming super-steep retrograded channel (SSRC) for CMOS transistor using rapid laser annealing to reduce thermal budget |
JP4501965B2 (ja) * | 2006-10-16 | 2010-07-14 | ソニー株式会社 | 半導体装置の製造方法 |
US7960282B2 (en) * | 2009-05-21 | 2011-06-14 | Globalfoundries Singapore Pte. Ltd. | Method of manufacture an integrated circuit system with through silicon via |
US9577079B2 (en) * | 2009-12-17 | 2017-02-21 | Infineon Technologies Ag | Tunnel field effect transistors |
US20130175579A1 (en) * | 2012-01-10 | 2013-07-11 | International Business Machines Corporation | Transistor with recessed channel and raised source/drain |
CN103383962B (zh) * | 2012-05-03 | 2016-06-29 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
US20150048452A1 (en) * | 2013-08-16 | 2015-02-19 | Macronix International Co., Ltd. | Ultra-high voltage semiconductor having an isolated structure for high side operation and method of manufacture |
US9324830B2 (en) * | 2014-03-27 | 2016-04-26 | International Business Machines Corporation | Self-aligned contact process enabled by low temperature |
US20150372100A1 (en) * | 2014-06-19 | 2015-12-24 | GlobalFoundries, Inc. | Integrated circuits having improved contacts and methods for fabricating same |
-
2014
- 2014-09-16 CN CN201410472750.9A patent/CN104269358A/zh active Pending
-
2015
- 2015-09-15 US US14/854,763 patent/US20160079389A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060220114A1 (en) * | 2005-03-30 | 2006-10-05 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
WO2011075991A1 (zh) * | 2009-12-23 | 2011-06-30 | 中国科学院微电子研究所 | 高性能半导体器件及其形成方法 |
CN102386095A (zh) * | 2010-08-31 | 2012-03-21 | 中国科学院微电子研究所 | 半导体结构的制造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106340440A (zh) * | 2015-07-08 | 2017-01-18 | 力晶科技股份有限公司 | 半导体元件的制造方法 |
CN105390447A (zh) * | 2015-10-26 | 2016-03-09 | 上海华力微电子有限公司 | 一种用于虚拟栅极的氮化硅制备方法 |
CN105390447B (zh) * | 2015-10-26 | 2018-09-04 | 上海华力微电子有限公司 | 一种用于虚拟栅极的氮化硅制备方法 |
CN106935490A (zh) * | 2015-12-31 | 2017-07-07 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法、电子装置 |
CN106935490B (zh) * | 2015-12-31 | 2020-07-07 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法、电子装置 |
CN112420752A (zh) * | 2019-08-20 | 2021-02-26 | 复旦大学 | 基于半导体衬底的新型单晶体管像素传感器及制备方法 |
CN112420752B (zh) * | 2019-08-20 | 2022-12-02 | 复旦大学 | 基于半导体衬底的新型单晶体管像素传感器及制备方法 |
Also Published As
Publication number | Publication date |
---|---|
US20160079389A1 (en) | 2016-03-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103545213B (zh) | 半导体器件及其制造方法 | |
US8716090B2 (en) | Semiconductor device manufacturing method | |
CN104347518B (zh) | 分裂栅非易失性存储器单元 | |
CN103426769B (zh) | 半导体器件制造方法 | |
CN102623341B (zh) | 一种mos晶体管的制造方法 | |
CN104269358A (zh) | 半导体器件的制备方法 | |
CN110034067A (zh) | 半导体器件及其形成方法 | |
EP3288071A1 (en) | Semiconductor structure and fabricating method thereof | |
CN105702582A (zh) | 晶体管的形成方法 | |
CN110047754A (zh) | 半导体器件及其制造方法 | |
CN106206719A (zh) | Mos晶体管及其形成方法 | |
CN108074973A (zh) | 半导体结构及其形成方法 | |
CN102938375B (zh) | 一种场效应晶体管及形成方法 | |
CN102184961A (zh) | 一种非对称栅mos器件及其制备方法 | |
US9269807B2 (en) | Semiconductor device and method of making the same | |
CN101930922B (zh) | Mos晶体管的制作方法 | |
US20170229540A1 (en) | Non-volatile memory device having reduced drain and read disturbances | |
CN106158657B (zh) | Mos晶体管的形成方法 | |
CN101572235B (zh) | N型轻掺杂区域的形成方法及半导体器件的制造方法 | |
CN108281485A (zh) | 半导体结构及其形成方法 | |
CN102867755A (zh) | 一种形成具有低gidl电流的nmos器件的方法 | |
US8409975B1 (en) | Method for decreasing polysilicon gate resistance in a carbon co-implantation process | |
CN105742166A (zh) | 一种降低器件漏电流的方法 | |
CN108807268B (zh) | 半导体结构及其形成方法 | |
CN101930924B (zh) | Mos晶体管的制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150107 |
|
RJ01 | Rejection of invention patent application after publication |