CN103545213B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103545213B
CN103545213B CN201210246830.3A CN201210246830A CN103545213B CN 103545213 B CN103545213 B CN 103545213B CN 201210246830 A CN201210246830 A CN 201210246830A CN 103545213 B CN103545213 B CN 103545213B
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秦长亮
殷华湘
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Institute of Microelectronics of CAS
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Abstract

本发明提供了一种具有外延LDD和Halo区域的晶体管器件及其制造方法。采用了外延与自对准各向异性刻蚀相结合的工艺，避免了现有的采用的离子注入以及退火工艺形成Halo和LDD区域制造方法中的问题，在不增加光刻掩膜数量和复杂性的基础上，彻底消除了离子注入造成的源漏区域凹槽表面处晶体结构的破坏，从而避免影响到后续源漏材料外的延生长，同时，本发明也不会因常规的离子注入而导致外延源漏的应力释放，从而保持了源漏应力及其抑制SCE和DIBL效应的效果。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法领域，特别地，涉及一种具有外延LDD和Halo区域的晶体管器件及其制造方法。
背景技术
半导体集成电路技术在进入到90nm特征尺寸的技术节点后，维持或提高晶体管性能越来越具有挑战性。目前，应变硅技术成为一种通过抑制短沟道效应、提升载流子迁移率来提高MOSFET器件性能的基本技术。对于PMOS而言，人们采用在源漏区形成沟槽后外延生长硅锗的方法，提供压应力以挤压晶体管的沟道区，从而提高PMOS的性能。同时，对于NMOS而言，为了实现同样目的，在源漏区外延硅碳的方法也逐渐被采用。具体地，STI(浅沟槽隔离)、SPT(应力接近技术)、源漏硅锗/硅碳嵌入、金属栅应力、刻蚀停止层(CESL)等应力技术被提出。同时，在小尺寸的器件中通常采用LDD、Halo工艺分别抑制热载流子效应以及防止源漏穿通，而LDD与Halo主要是通过离子注入然后退火来实现。
然而，传统LDD和Halo工艺中的的离子注入以及退火会带来一些问题。如果是源漏外延前进行离子注入，注入可能会导致源漏凹槽表面处晶体结构遭到破坏，从而影响到后续源漏外延生长硅锗；如果是源漏外延后进行注入，注入将导致外延层的应力释放，降低源漏应力，从而减弱源漏应力抑制SCE和DIBL效应的效果。退火过程的高温可能会使预非晶化形成的非晶化层晶化。另外，还有可能产生TED(Transient Enhanced Diffusion，瞬态增强扩散)效应，以及掺杂元素不能实现比较高的激活状态。
因此，需要提供一种新的、晶体管及其制造方法，以解决上述问题，从而更好地确保晶体管性能。
发明内容
本发明提供一种具有外延形成的LDD和Halo区域的半导体器件及其制造方法，其避免了现有的Halo和LDD区域制造方法中的离子注入以及退火带来的问题。
根据本发明的一个方面，本发明提供一种半导体器件制造方法，用于制造具有外延LDD和Halo区域的晶体管，其包括如下步骤：
提供半导体衬底，在该半导体衬底上形成STI结构，并进行阱区注入；形成栅极绝缘层、栅极，定义栅极图形；形成栅极间隙壁，其覆盖在所述栅极的顶部以及所述栅极和所述栅极绝缘层的侧壁上；形成源漏区域凹槽；在所述源漏区域凹槽内外延Halo材料层，所述Halo材料层具有第一掺杂元素；外延源漏区域，其向晶体管沟道区域提供应力，所述源漏区域具有第二掺杂元素，且第二掺杂元素的类型与第一掺杂元素的类型相反；各向同性刻蚀所述源漏区域，去除部分所述源漏区域材料，同时，去除位于所述栅极间隙壁正下方的部分Halo材料层并向晶体管沟道区域延伸一定的距离，剩余的Halo材料层形成了晶体管的Halo区域；外延LDD材料层，形成晶体管的LDD区域；形成源漏接触。
在本发明的方法中，所述Halo区域的厚度为1nm到100nm，优选为1nm到10nm。
在本发明的方法中，对于PMOS，所述Halo区域的材料为硅或硅锗，第一掺杂元素为N型掺杂元素，优选为磷；对于NMOS，所述Halo区域的材料为硅或硅碳，第一掺杂元素为N型掺杂元素，优选为硼。
在本发明的方法中，所述Halo区域的掺杂浓度为1e13-1e21cm-3，优选为1e13-1e15cm-3。
在本发明的方法中，所述LDD材料层的掺杂剂量小于所述源漏区域的掺杂剂量；所述LDD区域的掺杂浓度为1e13-1e15cm-3，所述源漏区域的掺杂浓度为1e15-1e20cm-3。
在本发明的方法中，对于PMOS，所述LDD区域的材料为硅或硅锗，掺杂元素为P型掺杂元素，优选为硼；对于NMOS，所述LDD区域的材料为硅或硅碳，掺杂元素为N型掺杂元素，优选为磷。
在本发明的方法中，形成晶体管的LDD区域具体包括：在外延LDD材料层之后，自对准各向异性刻蚀暴露出的LDD材料层，仅使得位于所述栅极间隙壁正下方的源漏区域凹槽内的部分LDD材料层保留，从而形成晶体管的LDD区域，之后，再次外延源漏区域的材料，以弥补所述源漏区域在刻蚀中的损失。
在本发明的方法中，形成晶体管的LDD区域具体包括：在外延LDD材料层之后，不进行自对准各向异性刻蚀，之后，再次外延源漏区域的材料以抬升源漏区域。
在本发明的方法中，在形成栅极绝缘层、栅极的步骤中，所述栅极的材料为多晶硅，并且，采用后栅工艺，即，在形成所述金属硅化物之后，去除多晶硅材料的所述栅极，形成栅极空洞，在该栅极空洞中填充金属，从而形成金属栅极。或者，在本发明的方法中，在形成栅极绝缘层、栅极的步骤中，采用先栅工艺，即，所述栅极的材料为金属。本发明的半导体器件制造方法适用于高k/金属栅先栅或后栅集成工艺。
根据本发明的一个方面，本发明提供一种半导体器件，包括具有外延LDD和Halo区域的晶体管，其包括：
半导体衬底，位于该半导体衬底上的STI结构和阱区；栅极绝缘层和栅极组成的栅极堆栈；栅极间隙壁，其覆盖在所述栅极的顶部以及所述栅极和所述栅极绝缘层的侧壁上；源漏区域凹槽；外延形成的Halo区域，其位于所述源漏区域凹槽内，并具有第一掺杂元素；外延形成的源漏区域，其向晶体管沟道区域提供应力，所述源漏区域具有第二掺杂元素，且第二掺杂元素的类型与第一掺杂元素的类型相反；外延形成的LDD区域，其部分或者全部位于栅极间隙壁正下方的源漏区域凹槽内，所述LDD区域的掺杂剂量小于所述源漏区域的掺杂剂量，掺杂类型与所述源漏区域的掺杂类型相同；以及源漏接触。
在本发明的器件中，所述Halo区域的厚度为1nm到100nm，优选为1nm到10nm。
在本发明的器件中，对于PMOS，所述Halo区域的材料为硅或硅锗，第一掺杂元素为N型掺杂元素，优选为磷；对于NMOS，所述Halo区域的材料为硅或硅碳，第一掺杂元素为N型掺杂元素，优选为硼。
在本发明的器件中，所述Halo区域的掺杂浓度为1e13-1e21cm-3，优选为1e13-1e15em-3。
在本发明的器件中，所述LDD区域的掺杂浓度为1e13-1e15em-3，所述源漏区域的掺杂浓度为1e15-1e20cm-3。
在本发明的器件中，对于PMOS，所述LDD区域的材料为硅或硅锗，掺杂元素为P型掺杂元素，优选为硼；对于NMOS，所述LDD区域的材料为硅或硅碳，掺杂元素为N型掺杂元素，优选为磷。
本发明的优点在于：采用了外延与自对准各向异性刻蚀相结合的工艺，避免了现有技术中离子注入以及退火工艺形成Halo和LDD区域制造方法中的问题，在不增加光刻掩膜数量和复杂性的基础上，彻底消除了离子注入造成的源漏区域凹槽表面处晶体结构的破坏，从而避免影响到后续源漏材料外的延生长，同时，本发明也不会因常规的离子注入而导致外延源漏的应力释放，从而保持了源漏应力及其抑制SCE和DIBL效应的效果。另外，在本发明中，由于取消了离子注入之后的退火，晶体管掺杂元素能够实现比较高的激活状态，并且，避免了可能会造成的预非晶化形成的非晶化层晶化以及TED效应。
附图说明
图1-7本发明提供的具有外延LDD和Halo区域的晶体管制造方法流程示意图以及晶体管结构示意图。
具体实施方式
以下，通过附图中示出的具体实施例来描述本发明。但是应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
本发明提供一种半导体器件及其制造方法，特别地涉及到涉及一种具有通过外延生长方式形成LDD和Halo的CMOS晶体管器件及其制造方法，其结构和制造流程参见附图1-7。
参见附图7，为本发明提供的半导体器件结构示意图。
本发明提供的半导体器件包括半导体衬底10，以及位于半导体衬底10上的STI结构11和阱区(未图示)；栅极绝缘层12和栅极13组成的栅极堆栈；栅极间隙壁14，其覆盖在栅极13的顶部以及栅极13和栅极绝缘层12的侧壁上；源漏区域凹槽；外延形成的Halo区域15’位于源漏区域凹槽内，并具有第一掺杂元素；外延形成的源漏区域16，其向晶体管沟道区域提供应力，源漏区域16具有第二掺杂元素，且第二掺杂元素的类型与第一掺杂元素的类型相反；外延形成的LDD区域18，其部分或者全部位于栅极间隙壁14正下方的源漏区域凹槽内，LDD区域18的掺杂剂量小于所述源漏区域的掺杂剂量，掺杂类型与所述源漏区域的掺杂类型相同；以及源漏接触19。
下面将要详细描述本发明提供的半导体器件制造方法。
首先，参见附图1，在半导体衬底10上形成有STI(Shallow trench isolation，浅沟槽隔离)结构11，以及栅极绝缘层12、栅极13和栅极间隙壁14。具体而言，提供半导体衬底10，本实施例中采用了单晶硅衬底，可选地，也可采用锗衬底或者其他合适的半导体衬底。在半导体衬底10上形成STI结构11的方法具体包括，首先在半导体衬底10上涂布光刻胶，接着光刻出STI结构11图形，并对半导体衬底10进行各向异性的刻蚀获得浅沟槽，在该浅沟槽中填充介电材料，常见的如SiO2，从而形成STI。在形成STI结构11之后，进行阱区注入(未在图中示出)。PMOS阱区注入杂质为N型杂质，而NMOS阱区注入杂质为P型杂质。为了形成包括栅极绝缘层12和栅极13的栅极堆栈，先在衬底10表面沉积一层高K栅极绝缘材料薄膜。高K栅极绝缘材料具有比SiO2更大的介电常数，对晶体管器件性能更为有利。高K栅极绝缘材料包括一些金属氧化物、金属铝酸盐等，例如HfO2、ZrO2、LaAlO3等。栅极绝缘层12既要实现其栅绝缘特性，又要具有尽可能薄的厚度，其厚度优选为0.5-10nm，沉积工艺例如为CVD。在形成栅极绝缘层12之后，沉积栅极13的材料。栅极13为多晶硅、金属或金属硅化物等材料，其中，在先栅工艺(gate first)中，栅极13材料通常为金属或金属硅化物，而在后栅工艺(gate last)中，栅极13材料为多晶硅，在完成晶体管其它部件后，将会去除多晶硅栅极，然后形成金属或金属硅化物栅极。在沉积栅极材料后，进行光刻胶涂布，光刻，定义出栅极图形，对栅极13以及栅极绝缘层12顺序刻蚀，从而形成栅极图形。接着，形成栅极间隙壁14包括在衬底10上沉积间隙壁材料层，例如SiO2、Si3N4等等，采用保形性良好的沉积工艺，使其以期望的厚度覆盖栅极13和栅极绝缘层12。接着，去除衬底10表面的间隙壁材料层，使间隙壁材料层仅留存在栅极13的顶部以及栅极13和栅极绝缘层12的侧壁上，也即栅极间隙壁14包围整个栅极堆栈。栅极间隙壁14的厚度为1nm-100nm，优选为5nm-50nm。之后，利用STI结构11、栅极13和栅极间隙壁14为掩膜，对半导体衬底10进行各向异性的自对准刻蚀，形成源漏区域凹槽。
接着，参见附图2，在源漏区域凹槽内外延Halo材料层15，Halo材料层15具有第一掺杂元素。Halo材料层15的材料可选地为硅或硅锗(对于PMOS)，或者，硅或硅碳(对于NMOS)，其掺杂浓度为1e13-1e21cm-3，优选为1e13-1e15cm-3。
接着，选择性地外延生长源漏区域16，参见附图3。源漏区域16材料可选地为硅或硅锗(对于PMOS)，或者，硅或硅碳(对于NMOS)，用以向MOS沟道区域提供应力，从而提高载流子迁移率。在外延的同时，可以进行原位掺杂，例如硼(PMOS)或者磷(NMOS)，用以形成器件源漏区域的掺杂。对于PMOS，源漏区域16提供压应力，对于NMOS，源漏区域16提供张应力。源漏区域16具有第二掺杂元素，其中，第二掺杂元素的类型与第一掺杂元素的类型相反，即若源漏区域16掺杂为P型杂质(PMOS)，则Halo材料层15掺杂为N型杂质，例如磷，若源漏区域16掺杂为N型杂质(NMOS)，则Halo材料层15掺杂为P型杂质，例如硼。
接着，参见附图4，各项同性地刻蚀去除部分源漏区域16，同时，将处在SDE区(Source drain extension，源漏扩展区)(附图中虚线圈住的源漏凹槽部分)的Halo材料层刻蚀掉，也即向栅极下方的沟道方向钻蚀，去除位于栅极间隙壁14正下方的部分Halo材料层并向晶体管沟道区域延伸一定的距离。在这里，刻蚀掉SDE区的Halo材料层，可以避免SDE区的串联电阻太大。被部分刻蚀后剩余的Halo材料层形成了晶体管的Halo区域15’，其厚度为1nm到100nm，优选为1nm到10nm。
接着，参见附图5，外延LDD材料层17，形成晶体管的LDD区域。其中，LDD材料层17具有与源漏区域16相同的第二掺杂元素，例如，对于PMOS，LDD区域的的材料为硅或硅锗，掺杂元素为硼；对于NMOS，LDD区域的的材料为硅或硅碳，掺杂元素为磷。但是，LDD材料层17的掺杂剂量小于源漏区域16的掺杂剂量，例如，源漏区域16的掺杂剂量为1e15-1e20cm-3，而LDD材料层17的掺杂剂量为1e13-1e15cm-3。在形成晶体管LDD区域的过程中，可以通过在源漏区域凹槽中外延LDD材料层17直接形成，即在外延LDD材料层之后，不进行自对准各向异性刻蚀，之后，再次外延源漏区域的材料以抬升源漏区域，降低接触电阻。这样，LDD区域至少部分是位于栅极间隙壁14正下方的源漏区域凹槽内(参见附图5的情形)，另外，也可通过如下步骤形成：参见附图6，在外延LDD材料层17之后，自对准地各向异性刻蚀暴露出的LDD材料层17，由于栅极间隙壁14的保护，位于栅极间隙壁14正下方的源漏区域凹槽内的部分LDD材料层得以保留，这部分残留的LDD材料层形成了晶体管的LDD区域18，之后，在源漏区域凹槽中再次外延源漏区域的材料，以弥补所述源漏区域在刻蚀中的损失，这样，LDD区域全部是位于栅极间隙壁14正下方的源漏区域凹槽内。
至此，通过外延形成的Halo和LDD区域已经实现。由于采用了外延与自对准各向异性刻蚀相结合的工艺，本发明中的Halo和LDD的形成方法避免了现有的采用的离子注入以及退火工艺形成Halo和LDD区域制造方法中的问题，在不增加光刻掩膜数量和复杂性的基础上，彻底消除了离子注入造成的源漏区域凹槽表面处晶体结构的破坏，从而避免影响到后续源漏材料外的延生长，同时，本发明也不会因常规的离子注入而导致外延源漏的应力释放，从而保持了源漏应力及其抑制SCE和DIBL效应的效果。另外，本发明中，由于取消了离子注入之后的退火，晶体管掺杂元素能够实现比较高的激活状态，并且，避免了可能会造成的预非晶化形成的非晶化层晶化以及TED(Transient Enhanced Diffusion，瞬态增强扩散)效应。
接下来，进行常规的晶体管制造工艺。参见附图7，形成金属硅化物作为源漏接触19，金属硅化物的材料例如是NiSi、NiSiGe、TiSi、TiSiGe。
若采用先栅工艺，则可以进行互连线的制备工艺。若采用后栅工艺，则可以去除之前形成的多晶硅栅极，并形成金属或金属硅化物栅极，完成栅极制备，之后再进行互连线制备。
以上参照本发明的实施例对本发明予以了说明。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围，本领域技术人员可以做出多种替换和修改，这些替换和修改都应落在本发明的范围之内。

Claims (16)

1.一种半导体器件制造方法，用于制造具有外延LDD和Halo区域的晶体管，其特征在于包括如下步骤：
提供半导体衬底，在该半导体衬底上形成STI结构，并进行阱区注入；
形成栅极绝缘层、栅极，定义栅极图形；
形成栅极间隙壁，其覆盖在所述栅极的顶部以及所述栅极和所述栅极绝缘层的侧壁上；
形成源漏区域凹槽；
在所述源漏区域凹槽内外延Halo材料层，所述Halo材料层具有第一掺杂元素；
外延源漏区域，其向晶体管沟道区域提供应力，所述源漏区域具有第二掺杂元素，且第二掺杂元素的类型与第一掺杂元素的类型相反；
各向同性刻蚀所述源漏区域，去除部分所述源漏区域材料，同时，去除位于所述栅极间隙壁正下方的部分Halo材料层并向晶体管沟道区域延伸一定的距离，剩余的Halo材料层形成了晶体管的Halo区域；
外延LDD材料层，形成晶体管的LDD区域；
形成源漏接触。
2.根据权利要求1所述的方法，其特征在于，所述Halo区域的厚度为1nm到100nm。
3.根据权利要求1所述的方法，其特征在于，所述Halo区域的厚度为1nm到10nm。
4.根据权利要求1所述的方法，其特征在于，对于PMOS，所述Halo区域的材料为硅或硅锗，第一掺杂元素为N型掺杂元素；对于NMOS，所述Halo区域的材料为硅或硅碳，第一掺杂元素为P型掺杂元素。
5.根据权利要求4所述的方法，其特征在于，对于PMOS，第一掺杂元素为磷；对于NMOS，第一掺杂元素为硼。
6.根据权利要求1所述的方法，其特征在于，所述Halo区域的掺杂浓度为1e13-1e21cm-3。
7.根据权利要求1所述的方法，其特征在于，所述Halo区域的掺杂浓度为1e13-1e15cm-3。
8.根据权利要求1所述的方法，其特征在于，所述LDD材料层的掺杂剂量小于所述源漏区域的掺杂剂量。
9.根据权利要求8所述的方法，其特征在于，所述LDD区域的掺杂浓度为1e13-1e15cm-3，所述源漏区域的掺杂浓度为1e15-1e20cm-3。
10.根据权利要求1所述的方法，其特征在于，对于PMOS，所述LDD区域的材料为硅或硅锗，掺杂元素为P型掺杂元素；对于NMOS，所述LDD区域的材料为硅或硅碳，掺杂元素为N型掺杂元素。
11.根据权利要求10所述的方法，其特征在于，对于PMOS，掺杂元素为硼；对于NMOS，掺杂元素为磷。
12.根据权利要求1所述的方法，其特征在于，形成晶体管的LDD区域具体包括：在外延LDD材料层之后，自对准各向异性刻蚀暴露出的LDD材料层，仅使得位于所述栅极间隙壁正下方的源漏区域凹槽内的部分LDD材料层保留，从而形成晶体管的LDD区域，之后，再次外延源漏区域的材料，以弥补所述源漏区域在刻蚀中的损失。
13.根据权利要求1所述的方法，其特征在于，形成晶体管的LDD区域具体包括：在外延LDD材料层之后，不进行自对准各向异性刻蚀，之后，再次外延源漏区域的材料以抬升源漏区域。
14.根据权利要求1所述的方法，其特征在于，在形成栅极绝缘层、栅极的步骤中，所述栅极的材料为多晶硅，并且，采用后栅工艺，即，在形成所述源漏接触之后，去除多晶硅材料的所述栅极，形成栅极空洞，在该栅极空洞中填充金属，从而形成金属栅极。
15.根据权利要求1所述的方法，其特征在于，在形成栅极绝缘层、栅极的步骤中，采用先栅工艺，即，所述栅极的材料为金属。
16.根据权利要求14或15所述的方法，其特征在于，所述半导体器件制造方法适用于高k/金属栅先栅或后栅集成工艺。
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