CN102184961A - 一种非对称栅mos器件及其制备方法 - Google Patents

一种非对称栅mos器件及其制备方法 Download PDF

Info

Publication number
CN102184961A
CN102184961A CN2011101062961A CN201110106296A CN102184961A CN 102184961 A CN102184961 A CN 102184961A CN 2011101062961 A CN2011101062961 A CN 2011101062961A CN 201110106296 A CN201110106296 A CN 201110106296A CN 102184961 A CN102184961 A CN 102184961A
Authority
CN
China
Prior art keywords
mos device
metal
asymmetric
preparation
nano line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011101062961A
Other languages
English (en)
Other versions
CN102184961B (zh
Inventor
吴东平
胡成
朱伦
朱志炜
张世理
张卫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fudan University
Original Assignee
Fudan University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fudan University filed Critical Fudan University
Priority to CN201110106296.1A priority Critical patent/CN102184961B/zh
Publication of CN102184961A publication Critical patent/CN102184961A/zh
Priority to US13/635,071 priority patent/US20140034956A1/en
Priority to PCT/CN2011/081571 priority patent/WO2012146019A1/zh
Priority to US14/113,705 priority patent/US9209029B2/en
Priority to PCT/CN2011/084808 priority patent/WO2012146044A1/zh
Application granted granted Critical
Publication of CN102184961B publication Critical patent/CN102184961B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种非对称栅MOS器件，其栅极为金属栅，且所述金属栅的功函数在所述MOS器件的源端与漏端不同，从而使得MOS器件的整体性能参数更加优化；同时，还公开了一种非对称栅MOS器件的制备方法，该方法通过对MOS器件的栅极进行离子注入掺杂，使所述栅极的功函数在所述MOS器件的源端与漏端不同，从而使得MOS器件的整体性能参数更加优化，该方法简单方便。

Description

一种非对称栅MOS器件及其制备方法
技术领域
本发明涉及半导体工艺技术领域，尤其涉及一种非对称栅MOS器件及其制备方法。
背景技术
自从第一个晶体管发明以来，经过几十年的飞速发展，晶体管的横向和纵向尺寸都迅速缩小。据国际半导体技术蓝图(ITRS，International TechnologyRoadmap for Semiconductors)在2004年的预测，到2018年晶体管的特征尺寸将达到7nm。尺寸的持续缩小使晶体管的性能(速度)不断提高，也使得我们能够在相同面积的芯片上集成更多的器件，集成电路的功能越来越强，同时也降低了单位功能成本。
然而器件特征尺寸的不断减小也带来了一系列的挑战。当器件的特征尺寸进入到深亚微米以后，器件的短沟道效应(SCE，Short Channel Effect)、漏致势垒降低效应(DIBL，Drain Induced Barrier Lower Effect)、热载流子效应(HCE，Hot Carrier Effect)等日趋严重，从而使器件的性能退化。现有技术主要通过沟道工程来解决这些问题。沟道工程是通过沟道内的非均匀掺杂来提高器件的性能，所得到的沟道电场分布是连续的。
在沟道工程中，人们提出了许多新的沟道结构器件，如轻掺杂漏(LDD，Lightly Doped Drain)、Pocket和Halo结构等。轻掺杂漏结构可以有效地吸收漏端的电力线，降低器件的漏端电场，抑制热载流子效应。Pocket和Halo结构器件可以通过对源端进行局部重掺杂，抬高源端势垒，削弱漏端电场对源端势垒的影响，很好地抑制器件的阈值电压漂移、源漏穿通以及器件的DIBL效应。
但是上述LDD结构增加了器件源漏区的串联电阻，会使器件的驱动电流降低；Pocket结构中，当Pocket的注入剂量/能量增加时，器件的阈值电压升高，也使器件的饱和驱动电流降低，这都影响了器件的工作速度。
为了解决上述问题，目前提出了一种非对称栅场效应晶体管，所谓非对称栅场效应晶体管是指晶体管的源区与漏区的栅结构等不完全相同，进而使得载流子发射区(源区)与载流子收集区(漏区)产生电学和物理性能上的不对称性，从而可以使得晶体管的整体性能参数更加优化，对未来极小尺寸晶体管的优化设计有着特别重要的作用。
现有的制备非对称栅场效应晶体管的方法通常是在晶体管的源端与漏端形成厚度不一致的栅氧化层，通过调节源端与漏端的栅氧化层的厚度来调节沟道的电场分布，从而提高晶体管的综合性能。
然而，上述通过在晶体管的源端与漏端形成厚度不一致的栅氧化层来制备非对称栅场效应晶体管的方法在工艺上具有一定的难度，很难实现较好的控制。
因此，如何方便有效地制备出非对称栅纳米MOS器件，已成为目前业界亟需解决的技术问题。
发明内容
本发明的目的在于提供一种非对称栅MOS器件及其制备方法，以提高MOS器件的性能。
为解决上述问题，本发明提出一种非对称栅MOS器件，所述MOS器件的栅极为金属栅，且所述金属栅的功函数在所述MOS器件的源端与漏端不同。
可选的，所述金属栅为金属半导体化合物纳米线。
可选的，该MOS器件具体包括：
半导体衬底；
栅氧化层，形成于所述半导体衬底上；
栅极，形成于所述栅氧化层上，并且所述栅极的两侧形成有侧墙；以及
源漏区，形成于所述栅极两侧的所述半导体衬底内。
可选的，所述金属栅的长度为2～11nm。
可选的，所述半导体衬底为硅或绝缘层上硅，所述金属半导体化合物纳米线为金属硅化物纳米线。
可选的，所述半导体衬底为锗或绝缘层上锗，所述金属半导体化合物纳米线为金属锗化物纳米线。
同时，为解决上述问题，本发明还提出一种上述非对称栅MOS器件的制备方法，该方法包括如下步骤：
提供半导体衬底；
在所述半导体衬底上制备栅氧化层；
在所述栅氧化层上制备栅极，并对所述栅极进行离子注入掺杂，使所述栅极两侧的功函数不同；
在所述栅极的两侧形成侧墙；
进行源漏注入，在所述半导体衬底内形成源漏区。
可选的，在所述栅氧化层上制备栅极具体包括如下步骤：
在所述栅氧化层上依次形成多晶半导体层以及绝缘层；
依次对所述绝缘层以及所述多晶半导体层进行刻蚀，去掉两侧的绝缘层以及多晶半导体层；
在所述多晶半导体层两侧的侧壁上沉积金属薄膜，所述金属薄膜中的金属向所述多晶半导体层扩散；
去除所述多晶半导体层侧壁表面剩余的金属薄膜；
对所述多晶半导体层进行退火，在所述多晶半导体层的侧壁表面形成金属半导体化合物纳米线；
去除所述绝缘层及所述多晶半导体层；
以所述金属半导体化合物纳米线为掩模，对所述栅氧化层进行刻蚀；以及
对所述金属半导体化合物纳米线进行离子注入掺杂，使所述金属半导体化合物纳米线两侧的功函数不同。
可选的，所述对金属半导体化合物纳米线进行离子注入掺杂所采用的离子为P离子、As离子或B离子中的任一种或其组合。
可选的，所述对金属半导体化合物纳米线进行离子注入掺杂，使所述金属半导体化合物纳米线两侧的功函数不同，是通过对所述金属半导体化合物纳米线进行单边离子注入实现的。
可选的，所述对金属半导体化合物纳米线进行离子注入掺杂，使所述金属半导体化合物纳米线两侧的功函数不同，是通过对所述金属半导体化合物纳米线进行双边离子注入实现的。
可选的，所述金属薄膜是通过PVD法沉积在所述多晶半导体层两侧的侧壁上的。
可选的，在所述PVD法沉积金属薄膜的过程中，将靶材部分离化成离子状态，使其产生金属离子，并在所述多晶半导体层上加第一偏压。
可选的，所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压实现的。
可选的，所述第一偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
可选的，所述第二偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
可选的，所述半导体衬底为硅或绝缘层上硅，所述多晶半导体层为多晶硅层，所述金属半导体化合物纳米线为金属硅化物纳米线。
可选的，所述半导体衬底为锗或绝缘层上锗，所述多晶半导体层为多晶锗层，所述金属半导体化合物纳米线为金属锗化物纳米线。
可选的，所述金属半导体化合物纳米线由金属与所述多晶半导体层反应生成，其中，所述金属为镍、钴、钛、镱中的任一种，或镍、钴、钛、镱中的任一种并掺入铂。
可选的，所述金属中还掺入了钨和/或钼。
可选的，在所述多晶半导体层两侧的侧壁上沉积金属薄膜时的衬底温度为0～300℃。
可选的，所述退火的温度为200～900℃。
与现有技术相比，本发明提供的非对称栅MOS器件，其栅极为金属栅，且所述金属栅的功函数在所述MOS器件的源端与漏端不同，从而使得MOS器件的整体性能参数更加优化。
与现有技术相比，本发明提供的非对称栅MOS器件的制备方法通过对MOS器件的栅极进行离子注入掺杂，使所述栅极的功函数在所述MOS器件的源端与漏端不同，从而使得MOS器件的整体性能参数更加优化，该方法简单方便。
附图说明
图1为本发明实施例提供的非对称栅MOS器件的剖面图；
图2为本发明实施例提供的非对称栅MOS器件的制备方法的流程图；
图3A至图3K为本发明实施例提供的非对称栅MOS器件的制备方法的各步骤对应的器件剖面图。
具体实施方式
以下结合附图和具体实施例对本发明提出的非对称栅MOS器件及其制备方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用于方便、明晰地辅助说明本发明实施例的目的。
本发明的核心思想在于，提供一种非对称栅MOS器件，其栅极为金属栅，且所述金属栅的功函数在所述MOS器件的源端与漏端不同，从而使得MOS器件的整体性能参数更加优化；同时，还提供一种非对称栅MOS器件的制备方法，该方法通过对MOS器件的栅极进行离子注入掺杂，使所述栅极的功函数在所述MOS器件的源端与漏端不同，从而使得MOS器件的整体性能参数更加优化，该方法简单方便。
请参考图1，图1为本发明实施例提供的非对称栅MOS器件的剖面图，如图1所示，本发明实施例提供的非对称栅MOS器件100的栅极为金属栅，且所述金属栅的功函数在所述MOS器件100的源端与漏端不同。具体地，本发明实施例提供的非对称栅MOS器件100包括：
半导体衬底101；
栅氧化层102，形成于所述半导体衬底101上；其中，所述栅氧化层102为高K介质层；
栅极，形成于所述栅氧化层102上，并且所述栅极的两侧形成有侧墙104；其中，所述栅极为金属栅，所述金属栅两侧的功函数不同；在本发明的一个具体实施例中，所述金属栅为金属半导体化合物纳米线103；以及
源漏区，形成于所述栅极两侧的所述半导体衬底101内；具体地，包括形成于所述栅极两侧的所述半导体衬底101内的源区105以及漏区106；所述金属栅在所述源区105与漏区106的功函数不同。
进一步地，所述金属栅的长度为2～11nm，即本发明实施例提供的MOS器件100的特征尺寸为2～11nm。
进一步地，所述半导体衬底101为硅或绝缘层上硅，所述金属半导体化合物纳米线103为金属硅化物纳米线。
进一步地，所述半导体衬底101为锗或绝缘层上锗，所述金属半导体化合物纳米线103为金属锗化物纳米线。
请继续参考图2，以及图3A至图3K，其中，图2为本发明实施例提供的非对称栅MOS器件的制备方法的流程图，图3A至图3K为本发明实施例提供的非对称栅MOS器件的制备方法的各步骤对应的器件剖面图。结合图2，以及图3A至图3K，本发明实施例提供的非对称栅MOS器件100的制备方法包括如下步骤：
S101、提供半导体衬底101；
S102、在所述半导体衬底101上制备栅氧化层102；其中，所述栅氧化层102为高K介质层；
S103、在所述栅氧化层102上制备栅极，并对所述栅极进行离子注入掺杂，使所述栅极两侧的功函数不同；其中，所述栅极为金属栅；在本发明的一个具体实施例中，所述金属栅为金属半导体化合物纳米线103；具体地，在所述栅氧化层102上制备栅极又包括以下步骤：
在所述栅氧化层102上依次形成多晶半导体层110以及绝缘层120，如图3A所示；
依次对所述绝缘层120以及所述多晶半导体层110进行刻蚀，去掉两侧的绝缘层120以及多晶半导体层110，如图3B所示；
在所述多晶半导体层110两侧的侧壁上沉积金属薄膜130，如图3C所示；所述金属薄膜130中的金属向所述多晶半导体层110扩散；
去除所述多晶半导体层110侧壁表面剩余的金属薄膜130，如图3D所示，所述金属扩散至所述多晶半导体层110表面后，在所述多晶半导体层110的表面形成含有金属的半导体薄层140；
对所述多晶半导体层110进行退火，在所述多晶半导体层110的侧壁表面形成金属半导体化合物纳米线103，如图3E所示；
去除所述绝缘层120及所述多晶半导体层110，如图3F所示；
以所述金属半导体化合物纳米线103为掩模，对所述栅氧化层102进行刻蚀；刻蚀后的器件剖面图如图3G所示；以及
对所述金属半导体化合物纳米线103进行离子注入掺杂，使所述金属半导体化合物纳米线103两侧的功函数不同；其中，所述对金属半导体化合物纳米线103进行离子注入掺杂所采用的离子为P离子、As离子或B离子中的任一种或其组合。并且该离子注入掺杂可通过对所述金属半导体化合物纳米线103进行单边离子注入实现，如图3H所示，即对所述金属半导体化合物纳米线103的一边侧壁进行离子注入掺杂，使得所述金属半导体化合物纳米线103两侧的离子掺杂不同；也可以通过对所述金属半导体化合物纳米线103进行双边离子注入实现，如图3I所示，即对所述金属半导体化合物纳米线103的两边侧壁均进行离子注入掺杂，此时可选择两边注入的离子剂量不同，或者两边注入的离子种类不同，使得所述金属半导体化合物纳米线103两侧的离子掺杂不同。
由于注入的离子会聚集到所述金属半导体化合物纳米线103与所述栅氧化层102的界面，从而改变所述金属半导体化合物纳米线103与所述栅氧化层102之间的功函数，而栅极的功函数决定了器件的阈值电压，因此，通过调节栅在源区与漏区的功函数，使其不同，进而使得源区与漏区产生电学和物理性能上的不对称性，从而可以使得晶体管的整体性能参数更加优化。
S104、在所述栅极的两侧形成侧墙104，如图3J所示；
S105、进行源漏注入，在所述半导体衬底101内形成源漏区；具体地，在所述栅极两侧的半导体衬底101内形成源区106以及漏区107，完成非对称栅MOS器件100的制备，如图3K所示。
进一步地，所述金属薄膜130是通过PVD法沉积在所述多晶半导体层110两侧的侧壁上的。并且，在所述PVD法沉积金属薄膜130的过程中，还可以选择将靶材部分离化成离子状态，使其产生金属离子，并在所述多晶半导体层110上加第一偏压；其中，所述将靶材部分离化成离子状态可通过在所述靶材上加第二偏压实现；并且，所述第一偏压为直流偏压、交流偏压或脉冲偏压中的任一种，所述第二偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
通过将靶材部分离化成离子状态，使其产生金属离子，并在所述多晶半导体层110上加第一偏压，使得所述金属离子加速向所述多晶半导体层110的侧壁运动，并进入所述多晶半导体层110的侧壁，从而使得扩散至所述多晶半导体层110的侧壁的金属离子更多，扩散深度更深，因而最终形成的金属半导体化合物纳米线103的宽度加宽，从而使得本发明实施例提供的非对称栅MOS器件100的栅极长度加长，特征尺寸加大；因此本发明实施例提供的非对称栅MOS器件100的栅极长度是可调的。具体地，所述非对称栅MOS器件100的栅极长度可为2～11nm。
需要说明的是，在本发明的一个具体实施例中，所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压实现的，然而本发明并不以此为限，任何使得靶材的一部分离化成离子状态的方式都在本发明的保护范围之内。
进一步地，所述半导体衬底101为硅或绝缘层上硅，所述多晶半导体层110为多晶硅层，所述金属半导体化合物纳米线103为金属硅化物纳米线。
进一步地，所述半导体衬底101为锗或绝缘层上锗，所述多晶半导体层110为多晶锗层，所述金属半导体化合物纳米线103为金属锗化物纳米线。
需要说明的是，在本发明的一个具体实施例中，所述半导体衬底101可为硅或绝缘层上硅、以及锗或绝缘层上锗，然而应该认识到，本发明并不以此为限，所述半导体衬底101还可为其它类型的半导体衬底，如砷化镓等三五族半导体衬底。
进一步地，所述金属半导体化合物纳米线103由金属与所述多晶半导体层110反应生成，其中，所述金属为镍、钴、钛、镱中的任一种，或镍、钴、钛、镱中的任一种并掺入铂；掺入铂是因为纯的一硅化镍在高温条件下稳定性差，或出现薄膜厚度变得不均匀并结块，或生成电阻率高的二硅化镍NiSi2，严重影响器件的性能，因此，为了减慢硅化镍的生长速度以及防止硅化镍薄层遇到高温时发生结块或形成二硅化镍，可以在镍中掺入一定比例的铂；其它金属中掺铂作类似解释。
进一步地，所述金属中还掺入了钨和/或钼；以进一步控制硅化镍或掺铂硅化镍的生长和镍/铂的扩散，并增加硅化镍或掺铂硅化镍的稳定性；其它金属中掺钨和/或钼作类似解释。
进一步地，在所述多晶半导体层110两侧的侧壁上沉积金属薄膜130时的衬底温度为0～300℃；这是因为对金属镍来说，沉积温度超过300℃会造成在超量的镍扩散的同时镍会和多晶半导体层110(例如多晶硅)直接反应形成硅化镍，导致厚度控制的失败；在该特定温度下，镍会经多晶硅侧壁表面向多晶硅侧壁进行扩散，这种扩散具有自饱和特性：镍向多晶硅侧壁进行扩散仅在硅的表面薄层中发生，形成一定硅/镍原子比例的薄层镍，该薄层镍的厚度和淀积时的衬底温度有关，温度越高，该薄层镍的厚度也越大，在室温下，该薄层镍的等效镍厚度为2纳米左右。
进一步地，所述退火的温度为200～900℃。
由于本发明实施例提供的金属半导体化合物纳米线103是通过在多晶半导体层110两侧的侧壁表面沉积金属薄膜130，所述金属薄膜130中的金属向所述多晶半导体层110的侧壁表面扩散，经过退火后，在所述多晶半导体层110的侧壁表面形成金属半导体化合物纳米线103(即金属栅)，而不需要利用高分辨率的光刻技术来形成金属半导体化合物纳米线103，因而大大节约了成本。
综上所述，本发明提供了一种非对称栅MOS器件，其栅极为金属栅，且所述金属栅的功函数在所述MOS器件的源端与漏端不同，从而使得MOS器件的整体性能参数更加优化；同时，还提供了一种非对称栅MOS器件的制备方法，该方法通过对MOS器件的栅极进行离子注入掺杂，使所述栅极的功函数在所述MOS器件的源端与漏端不同，从而使得MOS器件的整体性能参数更加优化，该方法简单方便。
显然，本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (22)

1.一种非对称栅MOS器件，其特征在于，所述MOS器件的栅极为金属栅，且所述金属栅的功函数在所述MOS器件的源端与漏端不同。
2.如权利要求1所述的非对称栅MOS器件，其特征在于，所述金属栅为金属半导体化合物纳米线。
3.如权利要求2所述的非对称栅MOS器件，其特征在于，该MOS器件具体包括：
半导体衬底；
栅氧化层，形成于所述半导体衬底上；
栅极，形成于所述栅氧化层上，并且所述栅极的两侧形成有侧墙；以及
源漏区，形成于所述栅极两侧的所述半导体衬底内。
4.如权利要求3所述的非对称栅MOS器件，其特征在于，所述金属栅的长度为2～11nm。
5.如权利要求4所述的非对称栅MOS器件，其特征在于，所述半导体衬底为硅或绝缘层上硅，所述金属半导体化合物纳米线为金属硅化物纳米线。
6.如权利要求4所述的非对称栅MOS器件，其特征在于，所述半导体衬底为锗或绝缘层上锗，所述金属半导体化合物纳米线为金属锗化物纳米线。
7.一种如权利要求3所述的非对称栅MOS器件的制备方法，其特征在于，包括如下步骤：
提供半导体衬底；
在所述半导体衬底上制备栅氧化层；
在所述栅氧化层上制备栅极，并对所述栅极进行离子注入掺杂，使所述栅极两侧的功函数不同；
在所述栅极的两侧形成侧墙；
进行源漏注入，在所述半导体衬底内形成源漏区。
8.如权利要求7所述的非对称栅MOS器件的制备方法，其特征在于，在所述栅氧化层上制备栅极具体包括如下步骤：
在所述栅氧化层上依次形成多晶半导体层以及绝缘层；
依次对所述绝缘层以及所述多晶半导体层进行刻蚀，去掉两侧的绝缘层以及多晶半导体层；
在所述多晶半导体层两侧的侧壁上沉积金属薄膜，所述金属薄膜中的金属向所述多晶半导体层扩散；
去除所述多晶半导体层侧壁表面剩余的金属薄膜；
对所述多晶半导体层进行退火，在所述多晶半导体层的侧壁表面形成金属半导体化合物纳米线；
去除所述绝缘层及所述多晶半导体层；
以所述金属半导体化合物纳米线为掩模，对所述栅氧化层进行刻蚀；以及
对所述金属半导体化合物纳米线进行离子注入掺杂，使所述金属半导体化合物纳米线两侧的功函数不同。
9.如权利要求8所述的非对称栅MOS器件的制备方法，其特征在于，所述对金属半导体化合物纳米线进行离子注入掺杂所采用的离子为P离子、As离子或B离子中的任一种或其组合。
10.如权利要求9所述的非对称栅MOS器件的制备方法，其特征在于，所述对金属半导体化合物纳米线进行离子注入掺杂，使所述金属半导体化合物纳米线两侧的功函数不同，是通过对所述金属半导体化合物纳米线进行单边离子注入实现的。
11.如权利要求9所述的非对称栅MOS器件的制备方法，其特征在于，所述对金属半导体化合物纳米线进行离子注入掺杂，使所述金属半导体化合物纳米线两侧的功函数不同，是通过对所述金属半导体化合物纳米线进行双边离子注入实现的。
12.如权利要求8所述的非对称栅MOS器件的制备方法，其特征在于，所述金属薄膜是通过PVD法沉积在所述多晶半导体层两侧的侧壁上的。
13.如权利要求12所述的非对称栅MOS器件的制备方法，其特征在于，在所述PVD法沉积金属薄膜的过程中，将靶材部分离化成离子状态，使其产生金属离子，并在所述多晶半导体层上加第一偏压。
14.如权利要求13所述的非对称栅MOS器件的制备方法，其特征在于，所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压实现的。
15.如权利要求14所述的非对称栅MOS器件的制备方法，其特征在于，所述第一偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
16.如权利要求14所述的非对称栅MOS器件的制备方法，其特征在于，所述第二偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
17.如权利要求8所述的非对称栅MOS器件的制备方法，其特征在于，所述半导体衬底为硅或绝缘层上硅，所述多晶半导体层为多晶硅层，所述金属半导体化合物纳米线为金属硅化物纳米线。
18.如权利要求8所述的非对称栅MOS器件的制备方法，其特征在于，所述半导体衬底为锗或绝缘层上锗，所述多晶半导体层为多晶锗层，所述金属半导体化合物纳米线为金属锗化物纳米线。
19.如权利要求17或18所述的非对称栅MOS器件的制备方法，其特征在于，所述金属半导体化合物纳米线由金属与所述多晶半导体层反应生成，其中，所述金属为镍、钴、钛、镱中的任一种，或镍、钴、钛、镱中的任一种并掺入铂。
20.如权利要求19所述的非对称栅MOS器件的制备方法，其特征在于，所述金属中还掺入了钨和/或钼。
21.如权利要求8所述的非对称栅MOS器件的制备方法，其特征在于，在所述多晶半导体层两侧的侧壁上沉积金属薄膜时的衬底温度为0～300℃。
22.如权利要求8所述的非对称栅MOS器件的制备方法，其特征在于，所述退火的温度为200～900℃。
CN201110106296.1A 2011-04-26 2011-04-26 一种非对称栅mos器件及其制备方法 Expired - Fee Related CN102184961B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201110106296.1A CN102184961B (zh) 2011-04-26 2011-04-26 一种非对称栅mos器件及其制备方法
US13/635,071 US20140034956A1 (en) 2011-04-26 2011-10-31 Asymmetric Gate MOS Device and Method of Making
PCT/CN2011/081571 WO2012146019A1 (zh) 2011-04-26 2011-10-31 纳米mos器件制备方法及纳米mos器件
US14/113,705 US9209029B2 (en) 2011-04-26 2011-12-28 Asymmetrical gate MOS device and method of making
PCT/CN2011/084808 WO2012146044A1 (zh) 2011-04-26 2011-12-28 一种非对称栅mos器件及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110106296.1A CN102184961B (zh) 2011-04-26 2011-04-26 一种非对称栅mos器件及其制备方法

Publications (2)

Publication Number Publication Date
CN102184961A true CN102184961A (zh) 2011-09-14
CN102184961B CN102184961B (zh) 2017-04-12

Family

ID=44571101

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110106296.1A Expired - Fee Related CN102184961B (zh) 2011-04-26 2011-04-26 一种非对称栅mos器件及其制备方法

Country Status (3)

Country Link
US (2) US20140034956A1 (zh)
CN (1) CN102184961B (zh)
WO (2) WO2012146019A1 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012146044A1 (zh) * 2011-04-26 2012-11-01 复旦大学 一种非对称栅mos器件及其制备方法
CN103731125A (zh) * 2013-12-20 2014-04-16 北京时代民芯科技有限公司 一种非对称高压mos器件的双端应用方法
CN103578993B (zh) * 2012-07-26 2016-06-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的形成方法
US10815561B2 (en) 2018-03-10 2020-10-27 Applied Materials, Inc. Method and apparatus for asymmetric selective physical vapor deposition
US10927450B2 (en) 2018-12-19 2021-02-23 Applied Materials, Inc. Methods and apparatus for patterning substrates using asymmetric physical vapor deposition
US10950448B2 (en) 2018-04-06 2021-03-16 Applied Materials, Inc. Film quality control in a linear scan physical vapor deposition process

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014009256A1 (de) * 2014-06-20 2015-12-24 Audi Ag Router und Verfahren zum Empfangen und Verteilen von Daten

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004200287A (ja) * 2002-12-17 2004-07-15 New Japan Radio Co Ltd 半導体装置用電極の形成方法
CN1979828A (zh) * 2005-12-07 2007-06-13 中国科学院物理研究所 金属硅化物纳米线及其制作方法
CN101452956A (zh) * 2007-12-06 2009-06-10 上海华虹Nec电子有限公司 高压pmos器件及制造方法
CN101740627A (zh) * 2008-11-26 2010-06-16 阿尔特拉公司 非对称金属-氧化物-半导体晶体管

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2616576B1 (fr) * 1987-06-12 1992-09-18 Commissariat Energie Atomique Cellule de memoire eprom et son procede de fabrication
JPH10214964A (ja) * 1997-01-30 1998-08-11 Oki Electric Ind Co Ltd Ｍｏｓｆｅｔ及びその製造方法
US6194768B1 (en) * 1998-10-23 2001-02-27 Advanced Micro Devices, Inc. High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure
US6133129A (en) * 1999-05-07 2000-10-17 Advanced Micro Devices, Inc. Method for fabricating a metal structure with reduced length that is beyond photolithography limitations
US6337274B1 (en) * 1999-12-06 2002-01-08 Micron Technology, Inc. Methods of forming buried bit line memory circuitry
US6989323B2 (en) * 2004-04-28 2006-01-24 International Business Machines Corporation Method for forming narrow gate structures on sidewalls of a lithographically defined sacrificial material
KR100680291B1 (ko) * 2005-04-22 2007-02-07 한국과학기술원 Ｈ자형 이중 게이트 구조를 갖는 다중비트 비휘발성 메모리소자와 이의 제조 방법 및 다중비트 동작을 위한 동작방법
JP5015446B2 (ja) * 2005-05-16 2012-08-29 アイメック 二重の完全ケイ化ゲートを形成する方法と前記方法によって得られたデバイス
US7425491B2 (en) * 2006-04-04 2008-09-16 Micron Technology, Inc. Nanowire transistor with surrounding gate
CN101536153B (zh) * 2006-11-06 2011-07-20 Nxp股份有限公司 制造fet栅极的方法
US7790611B2 (en) * 2007-05-17 2010-09-07 International Business Machines Corporation Method for FEOL and BEOL wiring
US8110465B2 (en) * 2007-07-30 2012-02-07 International Business Machines Corporation Field effect transistor having an asymmetric gate electrode
US7781274B2 (en) * 2008-03-27 2010-08-24 Kabushiki Kaisha Toshiba Multi-gate field effect transistor and method for manufacturing the same
CN102184961B (zh) * 2011-04-26 2017-04-12 复旦大学 一种非对称栅mos器件及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004200287A (ja) * 2002-12-17 2004-07-15 New Japan Radio Co Ltd 半導体装置用電極の形成方法
CN1979828A (zh) * 2005-12-07 2007-06-13 中国科学院物理研究所 金属硅化物纳米线及其制作方法
CN101452956A (zh) * 2007-12-06 2009-06-10 上海华虹Nec电子有限公司 高压pmos器件及制造方法
CN101740627A (zh) * 2008-11-26 2010-06-16 阿尔特拉公司 非对称金属-氧化物-半导体晶体管

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WOERLEE, P. H. ET AL.: "Novel method of producing ultrasmall platinum silicide gate electrodes", 《APPLIED PHYSICS LETTERS》 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012146044A1 (zh) * 2011-04-26 2012-11-01 复旦大学 一种非对称栅mos器件及其制备方法
WO2012146019A1 (zh) * 2011-04-26 2012-11-01 复旦大学 纳米mos器件制备方法及纳米mos器件
CN103578993B (zh) * 2012-07-26 2016-06-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的形成方法
CN103731125A (zh) * 2013-12-20 2014-04-16 北京时代民芯科技有限公司 一种非对称高压mos器件的双端应用方法
CN103731125B (zh) * 2013-12-20 2016-09-07 北京时代民芯科技有限公司 一种非对称高压mos器件的双端应用方法
US10815561B2 (en) 2018-03-10 2020-10-27 Applied Materials, Inc. Method and apparatus for asymmetric selective physical vapor deposition
US10950448B2 (en) 2018-04-06 2021-03-16 Applied Materials, Inc. Film quality control in a linear scan physical vapor deposition process
US10927450B2 (en) 2018-12-19 2021-02-23 Applied Materials, Inc. Methods and apparatus for patterning substrates using asymmetric physical vapor deposition

Also Published As

Publication number Publication date
WO2012146044A1 (zh) 2012-11-01
US20140034956A1 (en) 2014-02-06
CN102184961B (zh) 2017-04-12
US9209029B2 (en) 2015-12-08
US20140048875A1 (en) 2014-02-20
WO2012146019A1 (zh) 2012-11-01

Similar Documents

Publication Publication Date Title
RU2245589C2 (ru) Устройство полевого моп-транзистора и способ его изготовления
CN102184961A (zh) 一种非对称栅mos器件及其制备方法
CN100552974C (zh) 半导体元件及其形成方法
CN103426769B (zh) 半导体器件制造方法
CN102104006A (zh) 一种场效应晶体管的制备方法
CN106206692B (zh) N型鳍式场效应晶体管的形成方法
CN102938375B (zh) 一种场效应晶体管及形成方法
CN102487009B (zh) 一种nmos器件源极和漏极的制作方法
CN104269358A (zh) 半导体器件的制备方法
CN101930922B (zh) Mos晶体管的制作方法
CN102194868B (zh) 一种抗辐照的Halo结构MOS器件
US20080242031A1 (en) Method for fabricating p-channel field-effect transistor (fet)
CN102044438A (zh) Mos晶体管及其制造方法
CN115732556A (zh) 一种nmos器件、其制备方法及集成电路
CN102201343A (zh) 纳米mos器件制备方法及纳米mos器件
CN102867755A (zh) 一种形成具有低gidl电流的nmos器件的方法
CN102446769B (zh) 一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法
CN105742166A (zh) 一种降低器件漏电流的方法
CN101930924B (zh) Mos晶体管的制作方法
CN106206303B (zh) N型鳍式场效应晶体管的形成方法
CN103021827A (zh) 鳍式场效应管、cmos鳍式场效应管的形成方法
KR100699462B1 (ko) 쇼트키 장벽 관통 트랜지스터 및 그 제조방법
TW200812081A (en) High voltage device and manufacturing method thereof
CN104810291A (zh) Mos晶体管及其形成方法
CN104867974A (zh) Ldmos器件及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170412

Termination date: 20210426

CF01 Termination of patent right due to non-payment of annual fee