US20140034956A1 - Asymmetric Gate MOS Device and Method of Making - Google Patents

Asymmetric Gate MOS Device and Method of Making Download PDF

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US20140034956A1
US20140034956A1 US13/635,071 US201113635071A US2014034956A1 US 20140034956 A1 US20140034956 A1 US 20140034956A1 US 201113635071 A US201113635071 A US 201113635071A US 2014034956 A1 US2014034956 A1 US 2014034956A1
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metal
mos device
gate
semiconductor
making
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Dongping Wu
Cheng Hu
Lun Zhu
Zhiwei Zhu
Shili Zhang
Wei Zhang
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Fudan University
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Fudan University
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Definitions

  • the present invention is related to semiconductor processing technologies, and more particularly to an asymmetrical gate MOS device and method of making
  • LDD lightly doped drain
  • pocket and halo architectures can effectively absorb the electric flux line on the drain side, reduce the device electric field on the drain side, and suppress hot carrier effect.
  • pocket and halo architecture can raise the potential barrier on the source side, weaken the effect of the drain side electric field on the potential barrier on the source side, effectively suppress the shifting of the device threshold voltage, source-drain punch through and device DIBL effect.
  • the LDD architecture discussed above can increase the device source-drain serial resistance, and reduce the device drive current.
  • the device threshold voltage may increase when the implant dosage/energy for the pockets increases, causing reduction of the saturated drive current, and reducing the device operation speed.
  • asymmetric gate field effect transistors refers to a transistor in which the gate structure is different at the source region from that at the drain region, causing asymmetry in the electrical and physical properties at the carrier emitting side (source) and the carrier collecting side (drain), so that the overall performance of the transistor is more optimized. This is especially important in the design and optimization of future very small-scale transistors.
  • a gate oxide layer having different thicknesses on the source side and the drain side is typically formed.
  • channel electric field distribution can be adjusted, and the overall performance of the transistors is enhanced.
  • the purpose of this invention is to provide an asymmetrical gate MOS device and its method of making, in order to improve the performance of MOS devices.
  • the present invention provides an asymmetrical gate MOS device.
  • the gate of the MOS device is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device.
  • the metal gate includes a metal-semiconductor-compound nanowire.
  • the MOS device comprises, specifically:
  • a gate formed over the gate oxide layer, wherein the gate has sidewalls formed on its two sides;
  • the length of the metal gate is about 2-11 nm.
  • the semiconductor substrate includes silicon or silicon on insulator, and the metal-semiconductor-compound nanowire is a metal silicide nanowire.
  • the semiconductor substrate includes germanium or germanium on insulator, and the metal-semiconductor-compound nanowire is a metal germanide nanowire.
  • the present invention also provides a method of making an asymmetric gate MOS device.
  • the method comprises:
  • fabricating the gate over the gate oxide layer further comprises:
  • dopant ions implanted into the metal-semiconductor-compound nanowires are any of phosphorous (P) ions, arsenide (As) ions, boron (B) ions or any combination thereof
  • implanting dopant ions into the metal-semiconductor-compound nanowires to cause a respective metal-semiconductor-compound nanowire to have different work functions on its two sides is performed using single-sided ion implant on the metal-semiconductor-compound nanowire.
  • implanting dopant ions into the metal-semiconductor-compound nanowires to cause a respective metal-semiconductor-compound nanowire to have different work functions on its two sides is performed using double-sided ion implant on the metal-semiconductor-compound nanowire.
  • the metal films are deposited onto sidewalls on two sides of the polysilicon layer using a PVD process.
  • a target material is partially ionized into an ionic state, to cause it to produce metal ions, and a first bias voltage is applied to the polycrystalline semiconductor layer.
  • a second bias voltage is applied to the target material to partially ionize the target material into an ionic state.
  • the first bias voltage is any of a direct current bias voltage, an alternating current bias voltage and a pulsed bias voltage.
  • the second bias voltage is any of a direct current bias voltage, an alternating current bias voltage and a pulsed bias voltage.
  • the semiconductor substrate is silicon or silicon-on-insulator
  • the polycrystalline semiconductor layer is a polysilicon layer
  • the metal-semiconductor-compound nanowires are metal silicide nanowires.
  • the semiconductor substrate is germanium or germanium-on-insulator
  • the polycrystalline semiconductor layer is a polycrystalline germanium layer
  • the metal-semiconductor-compound nanowires are metal germanide nanowires.
  • the metal-semiconductor-compound nanowires are formed from chemical reaction between metal and the polycrystalline semiconductor layer, wherein, the metal can be any of nickel, cobalt, titanium, and ytterbium, or any of nickel, cobalt, titanium, and ytterbium incorporated with platinum.
  • the metal is further incorporated with tungsten and/or molybdenum.
  • the substrate is at a temperature of 0 ⁇ 300° C. during the deposition of the metal film on the sidewalls on two sides of the polycrystalline semiconductor layer.
  • the annealing temperature is about 200 ⁇ 900° C.
  • the asymmetric gate MOS device provided by the present invention has a metal gate.
  • the metal gate has different work functions on the source side and on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized.
  • the method of making an asymmetric gate MOS device causes the gate work function to be different on the source side from that on the drain side of the MOS device by implanting dopant ions into the gate of the MOS device, so that the overall performance parameters of the MOS device are more optimized.
  • the method can be easily implemented.
  • FIG. 1 is a cross-sectional diagram illustrating an asymmetric gate MOS device according to embodiments of the present invention.
  • FIG. 2 is a flowchart illustrating a method of making an asymmetric gate MOS device, as provided by embodiments of the present invention.
  • FIGS. 3A to 3K are device cross-sectional diagrams illustrating various steps in the method of making an asymmetric gate MOS device, as provided by embodiments of the present invention.
  • an asymmetric gate MOS device which has a metal gate.
  • the metal gate has different work functions on the source side and on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized.
  • a method of making the asymmetric gate MOS device is also provided. By implanting dopant ions into the gate of the MOS device, the method causes the gate to have different work functions on the source side and on the drain side of the MOS device, so that the overall performance parameters of the MOS device are further optimized. The method is easy to implement.
  • FIG. 1 is a cross-sectional diagram illustrating an asymmetric gate MOS device, as provided by embodiments of the present invention.
  • the asymmetrical gate MOS device 100 provided by the present invention has a metal gate, and the metal gate has a different work functions on the source side and on the drain side of the MOS device 100 .
  • the asymmetric gate MOS device 100 provided by embodiments of the present invention comprises:
  • a gate oxide layer 102 formed over the semiconductor substrate 101 , wherein the gate oxide layer 102 is a high-K dielectric layer;
  • a gate formed over the gate oxide layer 102 , wherein sidewalls 104 are formed on two sides of the gate, wherein the gate is a metal gate that has different work functions on its two sides, and wherein, in one specific embodiment, the gate is a metal-semiconductor-compound nanowire 103 ;
  • source/drain regions formed in the semiconductor substrate 101 on two sides of the gate including, specifically, a source region 105 and a drain region 106 formed in the semiconductor substrate 101 on two sides of the gate, wherein the metal gate has different work functions with respect to the source region 105 and the drain regions 106 .
  • the length of the metal gate is about 2-11 nm, meaning that the MOS device 100 provided by embodiments of the preset invention has a feature size of about 2-11 nm.
  • the semiconductor substrate 101 includes silicon or silicon on insulator, and the metal-semiconductor-compound nanowire 103 is a metal silicide nanowire.
  • the semiconductor substrate 101 includes germanium or germanium on insulator, and the metal-semiconductor-compound nanowire 103 is a metal germanide nanowire.
  • FIG. 2 is a flowchart illustrating a method of making an asymmetric gate MOS device, as provided by embodiments of the present invention
  • FIGS. 3A to 3K are device cross-sectional diagrams illustrating various steps in the method of making an asymmetric gate MOS device, as provided by embodiments of the present invention.
  • a method of making an asymmetric gate MOS device 100 comprises steps S 101 through S 105 , as discussed below.
  • a gate oxide layer 102 is fabricated on the semiconductor substrate 101 , wherein the gate oxide layer 102 is a high-K dielectric layer.
  • fabricating the gate over the gate oxide layer 102 further comprises:
  • FIG. 3D wherein a thin metal-containing semiconductor layer 140 is formed on surfaces of the polycrystalline semiconductor 110 layer after the metal diffuses to the surfaces of the polycrystalline semiconductor layer 110 ;
  • FIG. 3 is a cross-sectional diagram of the device after the etching.
  • Implanting dopant ions can be performed using single-sided ion implant on the metal-semiconductor-compound nanowires 103 , as shown in FIG.
  • dopant ions are implanted into the sidewall on one side of a respective metal-semiconductor-compound nanowire 103 , so as to cause the metal-semiconductor-compound nanowire 103 to be doped differently on its two sides.
  • Implanting dopant ions may also be performed using double-sided ion implant on the metal-semiconductor-compound nanowires 103 , as shown in FIG.
  • dopant ions are implanted into sidewalls on both sides of a respective metal-semiconductor-compound nanowire 103 while choosing different ion implant doses or different types of ions for the two sides, so as to cause the metal-semiconductor-compound nanowire 103 to be doped differently on its two sides.
  • the implanted ions can congregate near the interface between the metal-semiconductor-compound nanowire 103 and the gate oxide layer 102 , thereby changing the work functions between the metal-semiconductor-compound nanowire 103 and the gate oxide layer 102 , and because the work function of the gate determines the threshold voltage of the device, by adjusting the gate work functions at the source region and at the drain region, making them different, so as to create asymmetry in the electrical and physical properties at the source region and at the drain region, the overall performance parameters of the transistor can be more optimized.
  • S 105 Performing source/drain implants to form source/drain regions in the semiconductor substrate 101 , wherein, a source region 106 and a drain region 107 are formed in the semiconductor substrate 101 on two sides of the gate, completing the fabrication of the asymmetric gate MOS device 100 , as shown in FIG. 3K .
  • the metal films 130 are deposited onto sidewalls on two sides of the polycrystalline semiconductor layer 110 using a PVD process.
  • a target material is partially ionized into an ionic state, to cause it to produce metal ions, and a first bias voltage is applied to the polycrystalline semiconductor layer 110 .
  • a second bias voltage is applied to the target material to partially ionize the target material into an ionic state.
  • the first bias voltage is any of a direct current bias voltage, an alternating current bias voltage and a pulsed bias voltage.
  • the second bias voltage is any of a direct current bias voltage, an alternating current bias voltage and a pulsed bias voltage.
  • the asymetric gate MOS device 100 By partially ionizing the target material into an ionic state, causing it to produce metal ions, and by applying the first bias voltage to the polycrystalline semiconductor layer 110 , causing the metal ions to accelerate toward the sidewalls of the polycrystalline semiconductor layer 110 and to enter the polycrystalline semiconductor layer 110 , more metal ions can diffuse to the sidewalls of the polycrystalline semiconductor layer 110 , and greater diffusion depth can be obtained.
  • the eventually formed nanowires 103 can have increased width, and the asymetric gate MOS device 100 provided by embodiments of the present invention can have longer gate and larger feature sizes. Therefore, the asymetric gate MOS device 100 provided by embodiments of the present invention can have adjustable gate length. In some embodiments, the gate length of the asymetric gate MOS device 100 can be 2-11 nm.
  • a second bias voltage is applied on the target material to partially ionize the target material into the ionic state.
  • the present invention is not thus limited, however, any means of partially ionizing the target material into an ionic state would be included in the scope of protection for the present invention.
  • the semiconductor substrate 101 is silicon or silicon-on-insulator substrate
  • the polycrystalline semiconductor layer 110 is a polysilicon layer
  • the metal-semiconductor-compound nanowire 103 is a metal silicide nanowire.
  • the semiconductor substrate 101 is germanium or germanium-on-insulator substrate
  • the polycrystalline semiconductor layer 110 is a polycrystalline germanium layer
  • the metal-semiconductor-compound nanowire is a metal germanide nanowire.
  • the semiconductor substrate 101 can be silicon or silicon on insulator, or germanium or germanium on insulator. Understandably, the present invention is not thus limited.
  • the semiconductor substrate 101 can be another kind of semiconductor substrate, such as gallium arsenide or another III-V compound semiconductor substrate, etc.
  • the metal-semiconductor-compound nanowire 103 is formed by chemical reactions between metal and the polycrystalline semiconductor layer 110 .
  • the metal can be any of nickel, cobalt, titanium, and ytterbium, or any of nickel, cobalt, titanium, and ytterbium incorporated with platinum.
  • the platinum is incorporated because pure nickel silicide has poor stability at higher temperature, or tends to become non-uniform and agglomerate, or forms nickel di-silicide (NiSi 2 ), which has a high resistivity, seriously affecting device performance. Therefore, in order to slow down the formation of nickel silicide and prevent agglomeration and nickel di-silicide formation at high temperature, nickel is incorporated with platinum by a certain ratio. Platinum incorporation for other metals can be similarly explained.
  • the metal is further incorporated with tungsten and/or molybdenum, so as to further control the formation of nickel silicide or platinum incorporated nickel silicide and the diffusion of nickel/platinum, and to further enhance the thermal stability of the nickel silicide or platinum incorporated nickel silicide. Tungsten and/or molybdenum incorporation for other metals can be similarly explained.
  • the substrate temperature is at 0 ⁇ 300° C. during the deposition of the metal films 130 on the two sides of polycrystalline semiconductor layer 110 , because for nickel, deposition temperature exceeding 300° C. can result in excessive nickel diffusion and nickel reacting directly with polycrystalline semiconductor (such as polysilicon) layer 110 to form nickel silicide, leading to loss of control of film thickness.
  • nickel would diffuse into the polysilicon sidewalls through surfaces of the polysilicon sidewalls, and such diffusion has the characteristics of self-saturation, that is, the diffusion of nickel into the polysilicon sidewalls only happens in a thin surface layer of the silicon, forming a thin nickel layer of a certain silicon/nickel ratio.
  • the thickness of the thin nickel layer is related to the substrate temperature during deposition. The higher the temperature, the thicker the thin nickel layer. At room temperature, an equivalent nickel thickness of the thin nickel layer is about 2 nanometers.
  • the annealing is performed at a temperature of 200 ⁇ 900° C.
  • the metal-semiconductor-compound nanowires 103 are formed by depositing the metal films 130 on sidewalls on two sides of the polycrystalline semiconductor layer 110 , the metal in the metal films 130 diffusing toward the sidewall surfaces of the polycrystalline semiconductor layer 110 and forming, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) 103 on the sidewall surfaces of the polycrystalline semiconductor layer 110 , high-resolution lithography is not required to form the metal-compound-semiconductor nanowires 103 , resulting in significant cost saving.
  • the present invention provides an asymmetric gate MOS device, which has a metal gate.
  • the metal gate has different work functions on the source side and the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized.
  • a method of making the asymmetric gate MOS device is also provided. The method causes the gate work function to be different on the source side from that on the drain side of the MOS device by implanting dopant ions into the gate of the MOS device, so that the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.

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US20140048875A1 (en) 2014-02-20
US9209029B2 (en) 2015-12-08

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