WO2012146019A1 - 纳米mos器件制备方法及纳米mos器件 - Google Patents

纳米mos器件制备方法及纳米mos器件 Download PDF

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Publication number
WO2012146019A1
WO2012146019A1 PCT/CN2011/081571 CN2011081571W WO2012146019A1 WO 2012146019 A1 WO2012146019 A1 WO 2012146019A1 CN 2011081571 W CN2011081571 W CN 2011081571W WO 2012146019 A1 WO2012146019 A1 WO 2012146019A1
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Prior art keywords
metal
mos device
layer
nano
polycrystalline semiconductor
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PCT/CN2011/081571
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English (en)
French (fr)
Inventor
吴东平
胡成
朱伦
朱志炜
张世理
张卫
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复旦大学
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Priority to US13/635,071 priority Critical patent/US20140034956A1/en
Publication of WO2012146019A1 publication Critical patent/WO2012146019A1/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
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    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
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Definitions

  • the present invention relates to the field of semiconductor process technologies, and in particular, to a nano MOS device fabrication method and a nano MOS device.
  • the ever-decreasing feature size of the device also presents a series of challenges. Since the gate of the conventional MOS device is mostly made of polysilicon, when the size of the conventional polysilicon gate transistor is reduced to a certain extent, a polysilicon depletion effect (PDE) will occur, thereby hindering the performance of the transistor.
  • PDE polysilicon depletion effect
  • the so-called polysilicon gate depletion effect means that when the transistor is in an on state, a depletion layer is formed in the polysilicon gate. Since the depletion layer and the gate oxide layer are superposed, the electrical property is observed.
  • the effective thickness of the gate oxide layer is the sum of the actual thickness of the gate oxide layer and the thickness of the depletion layer, so that the effective thickness of the gate oxide layer is increased, resulting in a decrease in the on-current of the transistor.
  • the metal gate refers to a metal used as a gate of a MOS transistor. Due to the high conductance of the metal, the metal gate can avoid the gate depletion effect, resulting in better performance of the MOS device.
  • the present invention provides a method for fabricating a nano MOS device, the method comprising the following steps:
  • step (3) specifically includes the following steps:
  • the length of the gate is 2 ⁇ 11 nm.
  • the metal thin film is deposited on sidewalls on both sides of the polycrystalline semiconductor layer by a PVD method.
  • the target portion is separated into an ionic state to generate metal ions, and a first bias is applied to the polycrystalline semiconductor layer.
  • the separating the target portion into an ionic state is achieved by applying a second bias to the target.
  • the first bias voltage is any one of a DC bias voltage, an AC bias voltage, and a pulse bias voltage.
  • the second bias voltage is any one of a DC bias voltage, an AC bias voltage, or a pulse bias voltage.
  • the gate oxide layer is a high K dielectric layer.
  • the semiconductor substrate is silicon or silicon on the insulating layer
  • the polycrystalline semiconductor layer is a polysilicon layer
  • the metal semiconductor compound nanowires are metal silicide nanowires.
  • the semiconductor substrate is a germanium or an insulating layer
  • the polycrystalline semiconductor layer is a polysilicon layer
  • the metal semiconductor compound nanowires are metal-deciplex nanowires.
  • the metal semiconductor compound nanowire is formed by reacting a metal with the polycrystalline semiconductor layer, wherein the metal is any one of nickel, cobalt, titanium, and antimony, or nickel, cobalt, titanium, or antimony. Any of them and incorporate platinum.
  • tungsten and/or molybdenum are also incorporated into the metal.
  • a substrate temperature of 0 to 300 ° C is deposited when a metal thin film is deposited on sidewalls on both sides of the polycrystalline semiconductor layer.
  • the annealing temperature is 200 to 900 °C.
  • the present invention also provides a nano MOS device obtained by the above-described method for fabricating a nano MOS device, the nano MOS device comprising:
  • a gate electrode is formed on the gate oxide layer, and sidewalls are formed on both sides of the gate electrode; and source and drain regions are formed in the semiconductor substrate on both sides of the gate electrode.
  • the length of the gate is 2 ⁇ 11 nm.
  • the gate oxide layer is a high K dielectric layer.
  • the semiconductor substrate is silicon or silicon on the insulating layer
  • the metal semiconductor compound nanowire is a metal silicide nanowire.
  • the semiconductor substrate is a germanium or an insulating layer
  • the metal semiconductor compound nanowires are metal germanide nanowires.
  • the method for preparing a nano MOS device provided by the present invention, the gate prepared thereof a metal gate, thereby avoiding the depletion effect of the poly gate and improving the performance of the MOS device; and the method is to deposit a metal film on the sidewall surfaces on both sides of the polycrystalline semiconductor layer, the metal direction in the metal film
  • the sidewall surface of the polycrystalline semiconductor layer is diffused, and after annealing, a metal semiconductor compound nanowire (ie, a metal gate) is formed on a sidewall surface of the polycrystalline semiconductor layer without using high-resolution lithography To form metal semiconductor compound nanowires, thereby greatly saving costs.
  • the nano MOS device provided by the invention has a gate of a metal gate, thereby avoiding the depletion effect of the poly gate and improving the performance of the MOS device.
  • FIG 3 is a cross-sectional view of a nano MOS device according to an embodiment of the present invention.
  • the core idea of the present invention is to provide a method for fabricating a nano MOS device, wherein the gate is a metal gate, thereby avoiding the depletion effect of the poly gate and improving the performance of the MOS device; and the method is Depositing a metal thin film on the sidewall surfaces on both sides of the crystalline semiconductor layer, the metal in the metal thin film diffusing toward the sidewall surface of the polycrystalline semiconductor layer, and after annealing, forming a metal on the sidewall surface of the polycrystalline semiconductor layer.
  • Semiconductor compound nanowires ie, metal gates
  • FIG. 1 is a flowchart of a method for fabricating a nano MOS device according to an embodiment of the present invention
  • FIG. 2A to FIG. 2J are nano MOS according to an embodiment of the present invention.
  • the method for fabricating the nano MOS device 100 according to the embodiment of the present invention includes the following steps:
  • a gate electrode is formed on the gate oxide layer 102, and sidewall spacers 104 are formed on both sides of the gate electrode; wherein the gate electrode is a metal semiconductor compound nanowire 103; specifically, the gate oxide layer Preparing the gate on 102 includes the following steps:
  • a polycrystalline semiconductor layer 110 and an insulating layer 120 are sequentially formed on the gate oxide layer 102, as shown in FIG. 2A;
  • the insulating layer 120 and the polycrystalline semiconductor layer 110 are sequentially etched to remove the insulating layer 120 and the polycrystalline semiconductor layer 110 on both sides, as shown in FIG. 2B;
  • a metal thin film 130 is deposited on sidewalls on both sides of the polycrystalline semiconductor layer 110, as shown in FIG. 2C; metal in the metal thin film 130 is diffused toward the polycrystalline semiconductor layer 110;
  • the metal thin film 130 remaining on the sidewall surface of the polycrystalline semiconductor layer 110 is removed, and as shown in FIG. 2D, after the metal diffuses to the surface of the polycrystalline semiconductor layer 110, the surface of the polycrystalline semiconductor layer 110 is formed. a thin layer of metal semiconductor 140;
  • the gate oxide layer 102 is etched using the metal semiconductor compound nanowire 103 as a mask; the etched device cross-sectional view is as shown in FIG. 2G;
  • Side walls 104 are formed on both sides of the metal semiconductor compound nanowires 103, as shown in Fig. 2H.
  • the length of the gate is 2 to 11 nm.
  • the metal thin film 130 is deposited on sidewalls on both sides of the polycrystalline semiconductor layer 110 by a PVD method. Moreover, in the process of depositing the metal thin film 130 by the PVD method, Separating the target portion into an ionic state to generate metal ions, and applying a first bias voltage to the polycrystalline semiconductor layer 110; wherein the separating the target portion into an ionic state may pass through the target Adding a second bias voltage to the material; and, the first bias voltage is any one of a DC bias voltage, an AC bias voltage, or a pulse bias voltage, and the second bias voltage is a DC bias voltage, an AC bias voltage, or Any of the pulse biases.
  • the target portion is separated into an ionic state to generate metal ions, and a first bias is applied to the polycrystalline semiconductor layer 110 to accelerate the movement of the metal ions toward the sidewall of the polycrystalline semiconductor layer 110. And entering the sidewall of the polycrystalline semiconductor layer 110 such that metal ions diffused to the sidewalls of the polycrystalline semiconductor layer 110 are more diffused to a deeper depth, and thus the width of the finally formed metal semiconductor compound nanowire 103
  • the gate length of the nano MOS device 100 provided by the embodiment of the present invention is lengthened and the feature size is increased. Therefore, the gate length of the nano MOS device 100 provided by the embodiment of the present invention is adjustable. Specifically, the gate length of the nano MOS device 100 may be 2 to 11 nm.
  • the separating the target portion into an ion state is achieved by adding a second bias voltage to the target, but the invention is not limited thereto. Any means for ionizing a portion of the target into an ionic state is within the scope of the present invention.
  • the semiconductor substrate 101 is silicon or silicon on the insulating layer
  • the polycrystalline semiconductor layer 110 is a polysilicon layer
  • the metal semiconductor compound nanowires 103 are metal silicide nanowires.
  • the semiconductor substrate 101 is a germanium or an insulating layer
  • the polycrystalline semiconductor layer 110 is a polysilicon layer
  • the metal semiconductor compound nanowires 103 are metal germanide nanowires.
  • the semiconductor substrate 101 may be silicon or silicon on the insulating layer, and the fault or the insulating layer is wrong. However, it should be recognized that the present invention does not
  • the semiconductor substrate 101 can also be other types of semiconductor substrates, such as gallium arsenide and the like.
  • the metal semiconductor compound nanowire 103 is formed by reacting a metal with the polycrystalline semiconductor layer 110, wherein the metal is any one of nickel, cobalt, titanium, and antimony, or nickel, cobalt, titanium, Any of the ruthenium is doped with platinum; platinum is doped because pure nickel silicide has poor stability under high temperature conditions, or film thickness becomes uneven and agglomerates, or nickel oxynitride NiSi with high resistivity is formed.
  • the metal is further doped with tungsten and/or molybdenum; to further control the growth of nickel silicide or platinum-doped nickel silicide and the diffusion of nickel/platinum, and increase the stability of nickel silicide or platinum-doped nickel silicide; Tungsten and/or molybdenum in the metal is similarly explained.
  • the substrate temperature is 0 to 300 ° C. This is because for the metallic nickel, the deposition temperature exceeds 300 ° C.
  • Nickel reacts directly with the polycrystalline semiconductor layer 110 (eg, polysilicon) to form nickel silicide while excess nickel diffusion, resulting in failure of thickness control; at this particular temperature, nickel proceeds through the polysilicon sidewall surface toward the polysilicon sidewall Diffusion, this diffusion has self-saturation characteristics: The diffusion of nickel to the polysilicon sidewall occurs only in the thin layer of silicon, forming a thin layer of nickel in a silicon/nickel atomic ratio, the thickness of the thin layer of nickel and the deposition The temperature at the bottom of the village is related. The higher the temperature, the greater the thickness of the thin layer of nickel. At room temperature, the equivalent nickel thickness of the thin layer of nickel is about 2 nanometers.
  • the annealing temperature is 200 to 900 °C.
  • the metal semiconductor compound nanowires 103 provided by the embodiments of the present invention are formed by depositing a metal thin film 130 on the sidewall surfaces on both sides of the polycrystalline semiconductor layer 110, the metal in the metal thin film 130 is directed to the side of the polycrystalline semiconductor layer 110.
  • the surface of the wall is diffused, and after annealing, a metal semiconductor compound nanowire 103 (ie, a metal gate) is formed on a sidewall surface of the polycrystalline semiconductor layer 110 without using high-resolution photolithography to form such a fine metal.
  • the semiconductor compound nanowire 103 thus greatly saves cost.
  • the two metal semiconductor compound nanowires 203 formed by the method provided by the present invention together constitute the gate of the MOS transistor 200.
  • the gate is located on the gate oxide layer 202, and sidewalls 204 are formed on both sides of the gate, and a source region 205 and a drain region 206 are formed in the semiconductor substrate 201 on both sides of the gate, wherein the two The metal semiconductor compound nanowires 203 are connected together by an electrode 207.
  • FIG. 3 is a cross-sectional view of a nano MOS device according to an embodiment of the present invention.
  • the gate of the nano MOS device 100 provided by the embodiment of the present invention is a metal gate, and the length of the gate is 2 to 11 nm; wherein the metal gate is a metal semiconductor compound nanowire 103.
  • the nano MOS device 100 provided by the embodiment of the invention includes:
  • a gate oxide layer 102 is formed on the semiconductor substrate 101; wherein the gate oxide layer 102 is a high-k dielectric layer;
  • a gate electrode is formed on the gate oxide layer 102, and sidewalls 104 are formed on both sides of the gate electrode;
  • Source and drain regions are formed in the semiconductor substrate 101 on both sides of the gate; specifically, a source region 105 and a drain region 106 formed in the semiconductor substrate 101 formed on both sides of the gate.
  • the length of the gate is only 2 to 11 nanometers, and according to the scaling rule of the integrated circuit, other parameter values of the nano MOS device are also It should be correspondingly reduced.
  • the source region 105 and the drain region 106 should be an ultra-shallow source region and an ultra-shallow drain region.
  • the semiconductor substrate 101 is silicon or silicon on an insulating layer, and the metal semiconductor compound nanowires are metal silicide nanowires.
  • the semiconductor substrate 101 is a germanium or an insulating layer
  • the metal semiconductor compound nanowires are metal germanide nanowires.
  • the semiconductor substrate 101 may be silicon or silicon on the insulating layer, and the fault or the insulating layer is wrong. However, it should be recognized that the present invention does not
  • the semiconductor substrate 101 can also be other types of semiconductor substrates, such as gallium arsenide and the like.
  • the present invention provides a method for fabricating a nano MOS device, wherein the gate is a metal gate, thereby avoiding the depletion effect of the poly gate and improving the performance of the MOS device; and the method is A metal thin film is deposited on sidewall surfaces of both sides of the polycrystalline semiconductor layer, and a metal in the metal thin film diffuses toward a sidewall surface of the polycrystalline semiconductor layer, and after annealing, is formed on a sidewall surface of the polycrystalline semiconductor layer.
  • Metal-semiconductor compound nanowires ie, metal gates
  • metal gates do not require high-resolution photolithography to form metal semiconductor compound nanowires, thereby greatly saving cost; meanwhile, a nano-MOS device is provided, the gate of which is The metal gate can avoid the depletion effect of the poly gate and improve the performance of the MOS device.

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Description

纳米 MOS器件制备方法及纳米 MOS器件 技术械
本发明涉及半导体工艺技术领域，尤其涉及一种纳米 MOS器件制备方法及 纳米 MOS器件。
说 背景技术
自从第一个晶体管发明以来， 经过几十年的飞速发展， 晶体管的横向和纵 向尺寸都迅速缩小。 据国际半导体技术蓝图 （ITRS , International Technology
Roadmap for Semiconductors )在 2004年的预测书， 到 2018年晶体管的特征尺寸 将达到 7nm。 尺寸的持续缩小使晶体管的性能（速度） 不断提高， 也使得我们 能够在相同面积的芯片上集成更多的器件， 集成电路的功能越来越强， 同时也 降低了单位功能成本。
然而器件特征尺寸的不断减小也带来了一系列的挑战。 由于传统的 MOS器 件的栅极大多采用多晶硅， 而当传统的多晶硅栅晶体管的尺寸缩小到一定程度 后， 将出现多晶硅栅耗尽效应 （PDE, Poly Depletion Effect ), 从而阻碍晶体管 性能的提升。 所谓多晶硅栅耗尽效应， 是指当晶体管处于导通状态时， 在多晶 硅栅极中形成耗尽层， 由于该耗尽层和栅氧化层之间是叠加关系， 因此从电性 能角度观察到的栅氧化层的有效厚度为栅氧化层实际厚度与耗尽层厚度之和， 从而使得栅氧化层的有效厚度增加， 导致晶体管导通电流减小。
为了解决上述的多晶硅栅耗尽效应问题， 金属栅应运而生。 所谓金属栅是 指用金属来作为 MOS晶体管的栅极。 由于金属具有高的电导， 因此金属栅能避 免栅极耗尽效应， 从而使 MOS器件具有更好的性能。
但是， 目前纳米尺度的金属栅的制备还存在一定的技术难点。 这是因为目 前金属栅能达到的最小尺寸主要依赖于光刻技术， 而光刻系统的分辨率目前还 达不到几纳米的程度， 并且光刻系统价格昂贵， 工艺成本太高。
因此， 如何制备出纳米级的金属栅及 MOS器件， 已成为目前业界亟需解决 的技术问题。 发明内容
本发明的目的在于提供一种纳米 MOS器件制备方法及纳米 MOS器件， 以 减小 MOS器件的特征尺寸， 提高 MOS器件的性能。
为解决上述问题， 本发明提出一种纳米 MOS器件的制备方法， 该方法包括 如下步骤：
( 1 )提供半导体村底；
( 2 )在所述半导体村底上制备栅氧化层；
( 3 )在所述栅氧化层上制备栅极， 并在所述栅极的两侧形成侧墙， 其中， 所述栅极为金属半导体化合物纳米线；
( 4 )进行源漏注入， 在所述半导体村底内形成源漏区；
其中， 步骤（3 )具体包括如下步骤：
在所述栅氧化层上依次形成多晶半导体层以及绝缘层；
依次对所述绝缘层以及所述多晶半导体层进行刻蚀， 去掉两侧的绝缘层以 及多晶半导体层；
在所述多晶半导体层两侧的侧壁上沉积金属薄膜， 所述金属薄膜中的金属 向所述多晶半导体层扩散；
去除所述多晶半导体层侧壁表面剩余的金属薄膜；
对所述多晶半导体层进行退火， 在所述多晶半导体层的侧壁表面形成金属 半导体化合物纳米线；
去除所述绝缘层及所述多晶半导体层；
以所述金属半导体化合物纳米线为掩模， 对所述栅氧化层进行刻蚀； 以及 在所述金属半导体化合物纳米线的两侧形成侧墙。
可选的， 所述栅极的长度为 2~llnm。
可选的， 所述金属薄膜是通过 PVD法沉积在所述多晶半导体层两侧的侧壁 上的。
可选的， 在所述 PVD法沉积金属薄膜的过程中， 将靶材部分离化成离子状 态， 使其产生金属离子， 并在所述多晶半导体层上加第一偏压。 可选的， 所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压 实现的。
可选的， 所述第一偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。 可选的， 所述第二偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。 可选的， 所述栅氧化层为高 K介质层。
可选的， 所述半导体村底为硅或绝缘层上硅， 所述多晶半导体层为多晶硅 层， 所述金属半导体化合物纳米线为金属硅化物纳米线。
可选的， 所述半导体村底为锗或绝缘层上锗， 所述多晶半导体层为多晶锗 层， 所述金属半导体化合物纳米线为金属错化物纳米线。
可选的， 所述金属半导体化合物纳米线由金属与所述多晶半导体层反应生 成， 其中， 所述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱中的任 一种并掺入铂。
可选的， 所述金属中还掺入了钨和 /或钼。
可选的， 在所述多晶半导体层两侧的侧壁上沉积金属薄膜时的村底温度为 0~300°C。
可选的， 所述退火的温度为 200~900°C。
同时， 为解决上述问题， 本发明还提出一种利用上述纳米 MOS器件的制备 方法得到的纳米 MOS器件， 所述纳米 MOS器件包括：
半导体村底；
栅氧化层， 形成于所述半导体村底上；
栅极， 形成于所述栅氧化层上， 并且所述栅极的两侧形成有侧墙； 以及 源漏区， 形成于所述栅极两侧的所述半导体村底内。
可选的， 所述栅极的长度为 2~llnm。
可选的， 所述栅氧化层为高 K介质层。
可选的， 所述半导体村底为硅或绝缘层上硅， 所述金属半导体化合物纳米 线为金属硅化物纳米线。
可选的， 所述半导体村底为锗或绝缘层上锗， 所述金属半导体化合物纳米 线为金属锗化物纳米线。
与现有技术相比， 本发明提供的纳米 MOS器件的制备方法， 其制备的栅极 为金属栅， 因而可避免多晶栅极的耗尽效应， 提高 MOS器件的性能； 并且该方 法是通过在多晶半导体层两侧的侧壁表面沉积金属薄膜， 所述金属薄膜中的金 属向所述多晶半导体层的侧壁表面扩散， 经过退火后， 在所述多晶半导体层的 侧壁表面形成金属半导体化合物纳米线（即金属栅）， 而不需要利用高分辨率的 光刻技术来形成金属半导体化合物纳米线， 因而大大节约了成本。
与现有技术相比， 本发明提供的纳米 MOS器件， 其栅极为金属栅， 因而可 避免多晶栅极的耗尽效应， 提高 MOS器件的性能。 附图说明
图
图
Figure imgf000006_0001
应的器件剖面图；
图 3为本发明实施例提供的纳米 MOS器件的剖面图 具体实施方式
以下结合附图和具体实施例对本发明提出的纳米 MOS器件及其制备方法作 进一步详细说明。 根据下面说明和权利要求书， 本发明的优点和特征将更清楚。 需说明的是， 附图均采用非常筒化的形式且均使用非精准的比率， 仅用于方便、 明晰地辅助说明本发明实施例的目的。
本发明的核心思想在于， 提供一种纳米 MOS器件的制备方法， 其制备的栅 极为金属栅， 因而可避免多晶栅极的耗尽效应， 提高 MOS器件的性能； 并且该 方法是通过在多晶半导体层两侧的侧壁表面沉积金属薄膜， 所述金属薄膜中的 金属向所述多晶半导体层的侧壁表面扩散， 经过退火后， 在所述多晶半导体层 的侧壁表面形成金属半导体化合物纳米线（即金属栅）， 而不需要利用高分辨率 的光刻技术来形成金属半导体化合物纳米线， 因而大大节约了成本； 同时， 还 提供一种纳米 MOS器件， 其栅极为金属栅， 因而可避免多晶栅极的耗尽效应， 提高 MOS器件的性能。
请参考图 1 , 以及图 2A至图 2J, 其中， 图 1为本发明实施例提供的纳米 MOS器件的制备方法的流程图，图 2A至图 2J为本发明实施例提供的纳米 MOS 器件的制备方法的各步骤对应的器件剖面图。 结合图 1 , 以及图 2A至图 2J, 本 发明实施例提供的纳米 MOS器件 100的制备方法包括如下步骤：
5101、 提供半导体村底 101;
5102、 在所述半导体村底 101 上制备栅氧化层 102; 其中， 所述栅氧化层 102为高 K介质层；
5103、在所述栅氧化层 102上制备栅极，并在所述栅极的两侧形成侧墙 104; 其中， 所述栅极为金属半导体化合物纳米线 103; 具体地， 在所述栅氧化层 102 上制备栅极包括以下步骤：
在所述栅氧化层 102上依次形成多晶半导体层 110 以及绝缘层 120, 如图 2A所示；
依次对所述绝缘层 120 以及所述多晶半导体层 110进行刻蚀， 去掉两侧的 绝缘层 120以及多晶半导体层 110, 如图 2B所示；
在所述多晶半导体层 110两侧的侧壁上沉积金属薄膜 130, 如图 2C所示； 所述金属薄膜 130中的金属向所述多晶半导体层 110扩散；
去除所述多晶半导体层 110侧壁表面剩余的金属薄膜 130, 如图 2D所示， 所述金属扩散至所述多晶半导体层 110表面后， 在所述多晶半导体层 110的表 面形成含有金属的半导体薄层 140;
对所述多晶半导体层 110进行退火， 在所述多晶半导体层 110的侧壁表面 形成金属半导体化合物纳米线 103, 如图 2E所示；
去除所述绝缘层 120及所述多晶半导体层 110, 如图 2F所示；
以所述金属半导体化合物纳米线 103为掩模， 对所述栅氧化层 102进行刻 蚀； 刻蚀后的器件剖面图如图 2G所示； 以及
在所述金属半导体化合物纳米线 103的两侧形成侧墙 104, 如图 2H所示。
5104、 进行源漏注入， 在所述半导体村底 101 内形成源漏区， 具体地， 在 所述栅极两侧的半导体村底 101内形成源区 106以及漏区 107, 完成纳米 MOS 器件 100的制备， 如图 21所示。
进一步地， 所述栅极的长度为 2~llnm。
进一步地， 所述金属薄膜 130是通过 PVD法沉积在所述多晶半导体层 110 两侧的侧壁上的。 并且， 在所述 PVD法沉积金属薄膜 130的过程中， 还可以选 择将靶材部分离化成离子状态， 使其产生金属离子， 并在所述多晶半导体层 110 上加第一偏压； 其中， 所述将靶材部分离化成离子状态可通过在所述靶材上加 第二偏压实现； 并且， 所述第一偏压为直流偏压、 交流偏压或脉沖偏压中的任 一种， 所述第二偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。
通过将靶材部分离化成离子状态， 使其产生金属离子， 并在所述多晶半导 体层 110上加第一偏压， 使得所述金属离子加速向所述多晶半导体层 110的侧 壁运动， 并进入所述多晶半导体层 110 的侧壁， 从而使得扩散至所述多晶半导 体层 110 的侧壁的金属离子更多， 扩散深度更深， 因而最终形成的金属半导体 化合物纳米线 103的宽度加宽，从而使得本发明实施例提供的纳米 MOS器件 100 的栅极长度加长， 特征尺寸加大； 因此本发明实施例提供的纳米 MOS器件 100 的栅极长度是可调的。具体地，所述纳米 MOS器件 100的栅极长度可为 2~llnm。
需要说明的是， 在本发明的一个具体实施例中， 所述将靶材部分离化成离 子状态是通过在所述靶材上加第二偏压实现的， 然而本发明并不以此为限， 任 何使得靶材的一部分离化成离子状态的方式都在本发明的保护范围之内。
进一步地， 所述半导体村底 101为硅或绝缘层上硅， 所述多晶半导体层 110 为多晶硅层， 所述金属半导体化合物纳米线 103为金属硅化物纳米线。
进一步地， 所述半导体村底 101为锗或绝缘层上锗， 所述多晶半导体层 110 为多晶锗层， 所述金属半导体化合物纳米线 103为金属锗化物纳米线。
需要说明的是， 在本发明的一个具体实施例中， 所述半导体村底 101 可为 硅或绝缘层上硅、 以及错或绝缘层上错， 然而应该认识到， 本发明并不以此为 限， 所述半导体村底 101还可为其它类型的半导体村底， 如砷化镓等三五族半 导体村底。
进一步地， 所述金属半导体化合物纳米线 103 由金属与所述多晶半导体层 110反应生成， 其中， 所述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱中的任一种并掺入铂； 掺入铂是因为纯的一硅化镍在高温条件下稳定性差， 或出现薄膜厚度变得不均匀并结块， 或生成电阻率高的二硅化镍 NiSi2, 严重影 响器件的性能， 因此， 为了减慢硅化镍的生长速度以及防止硅化镍薄层遇到高 温时发生结块或形成二硅化镍， 可以在镍中掺入一定比例的铂； 其它金属中掺 铂作类似解释。 进一步地， 所述金属中还掺入了钨和 /或钼； 以进一步控制硅化镍或掺铂硅 化镍的生长和镍 /铂的扩散， 并增加硅化镍或掺铂硅化镍的稳定性； 其它金属中 掺钨和 /或钼作类似解释。
进一步地， 在所述多晶半导体层 110两侧的侧壁上沉积金属薄膜 130时的 村底温度为 0~300°C ; 这是因为对金属镍来说， 沉积温度超过 300°C会造成在超 量的镍扩散的同时镍会和多晶半导体层 110(例如多晶硅）直接反应形成硅化镍， 导致厚度控制的失败； 在该特定温度下， 镍会经多晶硅侧壁表面向多晶硅侧壁 进行扩散， 这种扩散具有自饱和特性： 镍向多晶硅侧壁进行扩散仅在硅的表面 薄层中发生， 形成一定硅 /镍原子比例的薄层镍， 该薄层镍的厚度和淀积时的村 底温度有关， 温度越高， 该薄层镍的厚度也越大， 在室温下， 该薄层镍的等效 镍厚度为 2纳米左右。
进一步地， 所述退火的温度为 200~900°C。
由于本发明实施例提供的金属半导体化合物纳米线 103是通过在多晶半导 体层 110两侧的侧壁表面沉积金属薄膜 130,所述金属薄膜 130中的金属向所述 多晶半导体层 110的侧壁表面扩散， 经过退火后， 在所述多晶半导体层 110的 侧壁表面形成金属半导体化合物纳米线 103 (即金属栅）， 而不需要利用高分辨 率的光刻技术来形成如此细的金属半导体化合物纳米线 103,因而大大节约了成 本。
需要说明的是， 在本发明的一个具体实施例中， 利用上述方法形成了两个 纳米 MOS器件 100, 然而应该认识到， 由于一般实际应用中的晶体管可能是多 指栅（ multi-finger )结构， 因而利用本发明提供的方法也可以只形成一个晶体管 200,如图 2J所示， 即利用本发明提供的方法形成的两个金属半导体化合物纳米 线 203共同构成 MOS晶体管 200的栅极， 所述栅极位于栅氧化层 202上， 且所 述栅极的两侧形成有侧墙 204, 在所述栅极两侧的半导体村底 201 内形成源区 205以及漏区 206,其中，所述两个金属半导体化合物纳米线 203通过一电极 207 连接在一起。
请参考图 3, 图 3为本发明实施例提供的纳米 MOS器件的剖面图， 如图 3 所示， 本发明实施例提供的纳米 MOS器件 100的栅极为金属栅， 且所述栅极的 长度为 2~llnm; 其中， 所述金属栅为金属半导体化合物纳米线 103。 具体地， 本发明实施例提供的纳米 MOS器件 100包括：
半导体村底 101;
栅氧化层 102, 形成于所述半导体村底 101上； 其中， 所述栅氧化层 102为 高 K介质层；
栅极， 形成于所述栅氧化层 102上， 并且所述栅极的两侧形成有侧墙 104; 以及
源漏区， 形成于所述栅极两侧的所述半导体村底 101 内； 具体地， 包括形 成于所述栅极两侧的所述半导体村底 101内的源区 105以及漏区 106。
需说明的是， 由于本发明实施例提供的纳米 MOS器件， 其栅极的长度只有 2 ~ 11纳米， 根据集成电路的按等比例缩小规则 （ scaling rule ), 该纳米 MOS器 件的其它参数值也应相应缩小， 例如所述源区 105 以及漏区 106应为超浅源区 及超浅漏区。
进一步地， 所述半导体村底 101 为硅或绝缘层上硅， 所述金属半导体化合 物纳米线为金属硅化物纳米线。
进一步地， 所述半导体村底 101 为锗或绝缘层上锗， 所述金属半导体化合 物纳米线为金属锗化物纳米线。
需要说明的是， 在本发明的一个具体实施例中， 所述半导体村底 101 可为 硅或绝缘层上硅、 以及错或绝缘层上错， 然而应该认识到， 本发明并不以此为 限， 所述半导体村底 101还可为其它类型的半导体村底， 如砷化镓等三五族半 导体村底。
综上所述， 本发明提供了一种纳米 MOS器件的制备方法， 其制备的栅极为 金属栅， 因而可避免多晶栅极的耗尽效应， 提高 MOS器件的性能； 并且该方法 是通过在多晶半导体层两侧的侧壁表面沉积金属薄膜， 所述金属薄膜中的金属 向所述多晶半导体层的侧壁表面扩散， 经过退火后， 在所述多晶半导体层的侧 壁表面形成金属半导体化合物纳米线（即金属栅）， 而不需要利用高分辨率的光 刻技术来形成金属半导体化合物纳米线， 因而大大节约了成本； 同时， 还提供 了一种纳米 MOS器件， 其栅极为金属栅， 因而可避免多晶栅极的耗尽效应， 提 高 MOS器件的性能。
显然， 本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明 的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要求及其 等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权 利 要 求 书
1、 一种纳米 MOS器件的制备方法， 其特征在于， 包括如下步骤：
( 1 )提供半导体村底；
( 2 )在所述半导体村底上制备栅氧化层；
( 3 )在所述栅氧化层上制备栅极， 并在所述栅极的两侧形成侧墙， 其中， 所述栅极为金属半导体化合物纳米线；
( 4 )进行源漏注入， 在所述半导体村底内形成源漏区；
其中， 步骤（3 )具体包括如下步骤：
在所述栅氧化层上依次形成多晶半导体层以及绝缘层；
依次对所述绝缘层以及所述多晶半导体层进行刻蚀， 去掉两侧的绝缘层以 及多晶半导体层；
在所述多晶半导体层两侧的侧壁上沉积金属薄膜， 所述金属薄膜中的金属 向所述多晶半导体层扩散；
去除所述多晶半导体层侧壁表面剩余的金属薄膜；
对所述多晶半导体层进行退火， 在所述多晶半导体层的侧壁表面形成金属 半导体化合物纳米线；
去除所述绝缘层及所述多晶半导体层；
以所述金属半导体化合物纳米线为掩模， 对所述栅氧化层进行刻蚀； 以及 在所述金属半导体化合物纳米线的两侧形成侧墙。
2、 如权利要求 1所述的纳米 MOS器件的制备方法， 其特征在于， 所述栅 极的长度为 2~llnm。
3、 如权利要求 1所述的纳米 MOS器件的制备方法， 其特征在于， 所述金 属薄膜是通过 PVD法沉积在所述多晶半导体层两侧的侧壁上的。
4、 如权利要求 3所述的纳米 MOS器件的制备方法， 其特征在于， 在所述 PVD法沉积金属薄膜的过程中， 将靶材部分离化成离子状态， 使其产生金属离 子， 并在所述多晶半导体层上加第一偏压。
5、 如权利要求 4所述的纳米 MOS器件的制备方法， 其特征在于， 所述将 靶材部分离化成离子状态是通过在所述靶材上加第二偏压实现的。
6、 如权利要求 5所述的纳米 MOS器件的制备方法， 其特征在于， 所述第 一偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。
7、 如权利要求 5所述的纳米 M0S器件的制备方法， 其特征在于， 所述第 二偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。
8、 如权利要求 1所述的纳米 MOS器件的制备方法， 其特征在于， 所述栅 氧化层为高 K介质层。
9、 如权利要求 8所述的纳米 MOS器件的制备方法， 其特征在于， 所述半 导体村底为硅或绝缘层上硅， 所述多晶半导体层为多晶硅层， 所述金属半导体 化合物纳米线为金属硅化物纳米线。
10、 如权利要求 8所述的纳米 MOS器件的制备方法， 其特征在于， 所述半 导体村底为锗或绝缘层上锗， 所述多晶半导体层为多晶锗层， 所述金属半导体 化合物纳米线为金属锗化物纳米线。
11、 如权利要求 9或 10所述的纳米 MOS器件的制备方法， 其特征在于， 所述金属半导体化合物纳米线由金属与所述多晶半导体层反应生成， 其中， 所 述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱中的任一种并掺入铂。
12、 如权利要求 11所述的纳米 MOS器件的制备方法， 其特征在于， 所述 金属中还掺入了钨和 /或钼。
13、 如权利要求 1所述的纳米 MOS器件的制备方法， 其特征在于， 在所述 多晶半导体层两侧的侧壁上沉积金属薄膜时的村底温度为 0~300°C。
14、 如权利要求 1所述的纳米 MOS器件的制备方法， 其特征在于， 所述退 火的温度为 200~900°C。
15、一种根据权利要求 1所述的纳米 MOS器件的制备方法得到的纳米 MOS 器件， 其特征在于， 所述纳米 MOS器件包括：
半导体村底；
栅氧化层， 形成于所述半导体村底上；
栅极， 形成于所述栅氧化层上， 并且所述栅极的两侧形成有侧墙； 以及 源漏区， 形成于所述栅极两侧的所述半导体村底内。
16、 如权利要求 15所述的纳米 MOS器件， 其特征在于， 所述栅极的长度 为 2~llnm。
17、 如权利要求 15所述的纳米 MOS器件， 其特征在于， 所述栅氧化层为 高 K介质层。
18、 如权利要求 17所述的纳米 MOS器件， 其特征在于， 所述半导体村底 为硅或绝缘层上硅， 所述金属半导体化合物纳米线为金属硅化物纳米线。
19、 如权利要求 17所述的纳米 MOS器件， 其特征在于， 所述半导体村底 为锗或绝缘层上锗， 所述金属半导体化合物纳米线为金属锗化物纳米线。
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