WO2011153816A1 - 一种场效应晶体管及其制备方法 - Google Patents

一种场效应晶体管及其制备方法 Download PDF

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WO2011153816A1
WO2011153816A1 PCT/CN2011/000729 CN2011000729W WO2011153816A1 WO 2011153816 A1 WO2011153816 A1 WO 2011153816A1 CN 2011000729 W CN2011000729 W CN 2011000729W WO 2011153816 A1 WO2011153816 A1 WO 2011153816A1
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semiconductor substrate
layer
field effect
effect transistor
metal
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PCT/CN2011/000729
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English (en)
French (fr)
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朴颖华
葛亮
吴东平
张世理
张卫
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复旦大学
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Priority to US13/642,286 priority Critical patent/US20130140625A1/en
Publication of WO2011153816A1 publication Critical patent/WO2011153816A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Definitions

  • the invention belongs to the technical field of microelectronic devices, relates to a semiconductor device and a related process preparation method, and more particularly to a field effect transistor and a preparation method thereof.
  • M0S field effect transistor is an abbreviation of metal-oxide-semiconductor field effect transistor. It is a kind of semiconductor device that uses electric field effect to control the current in semiconductor. It only relies on one kind of carrier to participate in conduction, so it is It is called a unipolar transistor. M0S field effect transistors can be made of semiconductor silicon or germanium, or can be made of compound semiconductor gallium arsenide. Currently, silicon materials are the most used. Generally, the M0 book S field effect transistor is composed of a semiconductor substrate, a source region and a drain region, a gate oxide layer, and a gate electrode. The basic structure is generally a four-terminal device, and the middle portion thereof is a metal-insulator.
  • the two sides of the M0S capacitor are the source region and the drain region respectively.
  • the gate is on the insulating layer. Applying a voltage across the gate changes the electric field strength in the insulating layer, controls the electric field on the surface of the semiconductor, and thereby changes the conductivity of the channel on the surface of the semiconductor.
  • the source and drain regions of a conventional MOSFET field effect transistor are purely heavily doped PN junction structures.
  • the PN junction can be formed by diffusion, ion implantation, etc., by incorporating a certain amount of impurities into the semiconductor substrate in the source and drain regions of the field effect transistor.
  • the field effect transistor having such a source-drain structure has a large series resistance, a short channel effect, and is not easily scaled down.
  • Metal silicide source and drain refers to metal silicide as the source and drain of the field effect and a Schottky junction between the metal silicide and the silicon substrate.
  • the main advantage is low parasitic resistance and excellent scaling down characteristics. Simple process manufacturing, low thermal budget and anti-latch effect or floating body effect in silicon (S0I) on insulator.
  • field-effect transistors that are purely composed of Schottky junctions have many potential problems. Schottky junctions often have extra leakage current and soft breakdown. The reliability of such source-drain structure field-effect transistors is still Not well studied.
  • the hybrid junction consists of a mixture of a Schottky junction and a PN junction, and has the advantages of high operating current, fast switching speed, low leakage current, and high breakdown voltage. Summary of the invention The object of the present invention is to provide an asymmetric source-drain field effect transistor with high operating current, fast switching speed and low leakage current, and a preparation method thereof.
  • the field effect transistor proposed by the present invention comprises a semiconductor substrate, a gate structure, a source region and a drain region respectively being a mixed junction and a PN junction, wherein the source region and the drain region are asymmetric in structure, and one of them is formed by a PN structure, and One is formed by a hybrid structure composed of a mixture of a Schottky junction and a PN junction.
  • the Schottky junction is composed of a metal semiconductor compound in contact with the semiconductor substrate, the PN junction being formed by implanting impurity ions of a different type from the semiconductor substrate and by subsequent thermal annealing.
  • the metal semiconductor compound in the mixed junction forms a Schottky junction with the semiconductor substrate and simultaneously forms a highly doped region in the source or drain region in the semiconductor substrate Ohmic contact.
  • the semiconductor substrate is a silicon, germanium, germanium silicon alloy, SOI structure or G0I structure, and the doping concentration of the semiconductor substrate is between 1*1 ( ⁇ to l*l (Tcm : ').
  • the field effect transistor further includes a shallow trench isolation structure formed in the semiconductor substrate, and a sidewall structure on both sides of the gate structure.
  • the metal semiconductor compound is any one of nickel silicide, nickel telluride, cobalt silicide, cobalt telluride, titanium silicide, titanium telluride, platinum silicide, platinum telluride or a mixture thereof. .
  • Another object of the present invention is to provide a method of fabricating the above-described asymmetric source-drain field effect transistor, comprising the steps of:
  • a providing a semiconductor substrate, forming an isolation structure by a shallow trench isolation process; 'b, forming a first insulating dielectric layer, then forming an electrode layer on the first insulating dielectric layer, and then passing through a photolithography, etching process Graphically etching the electrode layer and the first insulating layer to form a gate structure and source and drain regions on both sides thereof;
  • e performing ion implantation, selecting an implantation angle ⁇ such that ions are reached in a portion of the source region or the drain region, performing annealing to activate the implanted ions, and forming a junction in the source region and the drain region;
  • the metal layer depositing a metal layer, and after annealing, the metal layer reacts with the exposed semiconductor substrate in the source region and the drain region to form a metal semiconductor compound conductor layer, and removes a reaction layer that does not react with the semiconductor substrate The metal layer.
  • the present invention provides another method of fabricating the asymmetric source-drain field effect transistor, comprising the steps of: a, providing a semiconductor substrate, and forming an isolation structure by a shallow trench isolation process; b, forming a first insulating dielectric layer, then forming an electrode layer on the first insulating dielectric layer, and then pattern etching the electrode layer and the first insulating layer by photolithography and etching processes Forming a gate structure and source and drain regions on both sides thereof;
  • the metal layer depositing a metal layer, and after annealing, the metal layer reacts with the exposed semiconductor substrate in the source region and the drain region to form a metal semiconductor compound conductor layer, and removes a reaction layer that does not react with the semiconductor substrate The metal layer.
  • the semiconductor substrate is a silicon, germanium, germanium silicon alloy, SOI structure or G0I structure.
  • the first insulating dielectric layer is a silicon dioxide, silicon nitride, aluminum oxide or bismuth based high dielectric constant dielectric material.
  • the electrode layer described in the above two methods comprises at least one conductive layer, and the conductive layer is any one of polysilicon, titanium nitride, tantalum nitride, tungsten metal, metal silicide or between them. Multi-layer structure.
  • the above two methods form a peak impurity concentration of not less than 1*10 19 crtT' in the semiconductor substrate by the ion implantation.
  • the metal layer is any one of nickel, cobalt, titanium, platinum or a mixture therebetween.
  • the metal semiconductor compound conductor layer of the above two methods is any one of nickel silicide, nickel telluride, cobalt silicide, cobalt telluride, titanium silicide, titanium telluride, platinum silicide, platinum telluride or the like. a mixture of several.
  • the invention has the advantages of high working current, fast switching speed, small leakage current and high breakdown voltage.
  • Figure 1 is a schematic cross-sectional view showing a semiconductor substrate used in an example of the present invention after forming a shallow trench isolation structure.
  • Figure 2 is a schematic cross-sectional view showing the first insulating dielectric layer and the electrode layer formed on the semiconductor substrate subsequent to Figure 1.
  • Fig. 3 is a schematic cross-sectional view showing the gate structure formed by photolithography and etching after Fig. 2.
  • Figure 4 is a schematic cross-sectional view showing the formation of a second insulating dielectric layer subsequent to Figure 3.
  • FIG. 5 is a schematic cross-sectional view showing the sidewall structure after the etching step is performed after FIG. 4.
  • FIG. ⁇ Fig. 6 is a schematic cross-sectional view showing ion implantation and annealing subsequent to Fig. 5.
  • Figure 7 is a schematic cross-sectional view of the metal layer after deposition of Figure 6.
  • Fig. 8 is a schematic cross-sectional view of an asymmetric source/drain field effect transistor formed after annealing and removing a metal layer subsequent to Fig. 7.
  • Fig. 9 is a schematic cross-sectional view showing ion implantation and annealing after Fig. 3.
  • Figure 10 is a schematic cross-sectional view showing the formation of a second insulating dielectric layer subsequent to Figure 9.
  • Fig. 11 is a schematic cross-sectional view showing the side wall structure after the etching step is performed after Fig. 10.
  • Figure 12 is a schematic cross-sectional view of the metal layer after deposition of Figure 11.
  • Figure 13 is a schematic cross-sectional view of an asymmetric source-drain field effect transistor formed after annealing and removing the metal layer in Figure 12
  • Figure 1 is a schematic cross-sectional view showing a semiconductor substrate used in an example of the present invention after forming a shallow trench isolation structure.
  • the silicon substrate 101 is prepared and various processes such as cleaning and removing a thin layer of natural silicon dioxide on the silicon surface are completed.
  • the semiconductor substrate is monocrystalline silicon.
  • Isolation structure 102 is then fabricated around the transistor using a shallow trench isolation process. ⁇
  • a first insulating dielectric layer 203 is first formed on a substrate. Then, an electrode layer 204 is formed on the first insulating dielectric layer 203.
  • the electrode layer and the first insulating dielectric layer are patterned by photolithography and etching processes to form a gate structure and source and drain regions on both sides thereof.
  • the insulating dielectric layer 305 is anisotropically etched by a dry etching process to form a sidewall structure 315 along both sides of the gate structure, and the cross-sectional shape is as shown in FIG. '
  • ion implantation is performed, and the implantation angle ⁇ is selected such that the source region or the drain region partially has ions to
  • the annealing is performed to activate the implanted ions, and a region 406 having a doping type opposite to the substrate is formed in the semiconductor substrate, and 406 forms a PN junction with the silicon substrate 101.
  • a metal layer 507 is deposited on the substrate, and 507 is any one of nickel, cobalt, titanium, platinum or a mixture thereof, after annealing 507 and the source region and the drain region.
  • the exposed substrate reacts to form a metal semiconductor compound.
  • the metal semiconductor compound conductor layer 517 is exposed after removing the remaining unreacted metal layer 507, and 517 is nickel silicide, nickel telluride, cobalt silicide, cobalt telluride, titanium silicide, titanium telluride, platinum silicide, Any one of deuterated platinum or a mixture between them.
  • Other processes may be used to form the conductor layer 517 without departing from the spirit of the present invention.
  • Figure 1 is a schematic cross-sectional view showing a semiconductor substrate used in an example of the present invention after forming a shallow trench isolation structure.
  • the silicon substrate 101 is prepared and various processes such as cleaning and removing a thin layer of natural silicon dioxide on the silicon surface are completed.
  • the semiconductor substrate is monocrystalline silicon.
  • Isolation structure 102 is then fabricated around the transistor using a shallow trench isolation process.
  • a first insulating dielectric layer 203 is first formed on a substrate. Then, an electrode layer 204 is formed on the first insulating dielectric layer 203.
  • the electrode layer and the first insulating dielectric layer are patterned by photolithography and etching processes to form a gate structure and source and drain regions on both sides thereof.
  • ion implantation is performed, and an implantation angle is selected such that ions are reached in the source region or the drain region portion, annealing is performed to activate the implanted ions, and a doping type is formed in the semiconductor substrate opposite to the substrate. Regions 606, 606 and 101 form a PN junction.
  • a second insulating dielectric layer 705 is deposited. Then, the insulating dielectric layer is anisotropically etched by a dry etching process to form a sidewall structure 715 along both sides of the gate structure, and the thickness of the 715 should be smaller than the product of the height of the gate structure and tana, that is, a guarantee A portion of the substrate 101 is exposed, and the cross-sectional shape is as shown in Fig. 11.
  • a metal layer 807 is deposited on the substrate, and 807 is any one of nickel, cobalt, titanium, platinum or a mixture therebetween, and after annealing 807 and the source region and the drain region.
  • the exposed substrate reacts to form a metal semiconductor compound.
  • 817 is any one of nickel silicide, nickel telluride, cobalt silicide, cobalt telluride, titanium silicide, titanium telluride, platinum silicide, and platinum telluride or a mixture thereof. Other processes may be used to form the conductor layer 817 without departing from the spirit of the present invention.

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Description

一种场效应晶体管及其制备方法
技术领域
本发明属于微电子器件技术领域，涉及半导体器件和相关工艺制备方法，更具体的说， 涉及场效应晶体管及其制备方法。
背景技术
M0S 场效应晶体管 （M0SFET) 是金属 -氧化物-半导体场效应晶体管的简称， 是利用电 场效应来控制半导体中电流的一种半导说体器件， 只依靠一种载流子参与导电， 故又称为单 极型晶体管。 M0S 场效应晶体管可以用半导体硅、 锗为材料， 也可用化合物半导体砷化镓 等材料制作， 目前以使用硅材料的最多。 通常 M0书S场效应晶体管由半导体衬底、 源区和漏 区、 栅氧化层以及栅电极等几个主要部分组成， 其基本结构一般是一个四端器件， 它的中 间部分是由金属-绝缘体-半导体组成的 M0S电容结构， M0S电容的两侧分别是源区和漏区， 在正常的工作状态下， 载流子将从源区流入， 从漏区流出， 绝缘层上为栅极， 在栅极上施 加电压， 可以改变绝缘层中的电场强度， 控制半导体表面电场， 从而改变半导体表面沟道 的导电能力。
常规 M0S场效应晶体管的源区和漏区是纯粹重掺杂 PN结结构。 这种 PN结可以采用扩 散、 离子注入等制造工艺， 将一定数量的杂质掺入半导体衬底在场效应晶体管的源区和漏 区形成。 然而， 具有这种源漏结构的场效应晶体管其串眹电阻比较大， 短沟道效应严重， 且不易按比例缩小。
如果将金属硅化物源漏来代替传统的重掺杂 PN结源漏并应用在未来超缩微化的 CMOS 器件中， 将会在一定程度上提高场效应晶体管的性能。 金属硅化物源漏是指金属硅化物作 为场效应的源极和漏极并且金属硅化物和硅衬底之间形成肖特基结， 其主要优势是低的寄 生电阻， 优良的按比例缩小特性， 简便的工艺制造， 低的热预算以及抗闩锁效应或者绝缘 体上的硅 （S0I ) 里的浮体效应。 然而， 纯粹由肖特基结组成源漏的场效应晶体管也有许 多潜在的问题， 肖特基结常存在额外的漏电流和软击穿， 这种源漏结构的场效应晶体管的 可靠性目前还没有得到很好的研究。
混合结由肖特基结和 PN 结混合构成， 具有工作电流高、 开关速度快、 漏电流小， 击 穿电压高等优点。 发明内容 本发明的目的是提出一种工作电流高、 开关速度快、 漏电流小的不对称型源漏场效应 晶体管及其制备方法。
本发明提出的场效应晶体管， 包括半导体衬底、 栅极结构、 分别为混合结和 PN 结的 源区和漏区， 所述源区与漏区结构不对称， 其一由 PN 结构成， 另外一个由混合结构成， 所述混合结由肖特基结和 PN结混合构成。
优选地， 所述肖特基结由金属半导体化合物和所述半导体衬底接触构成， 所述 PN 结 是通过注入与所述半导体衬底掺杂类型不同的杂质离子并通过随后的热退火形成。
优选地， 所述混合结中的所述金属半导体化合物与所述半导体衬底形成肖特基结， 并 同时与所述半导体衬底中的所述源区或漏区中的高掺杂区域形成欧姆接触。
优选地， 所述半导体衬底是硅、 锗、 锗硅合金、 S0I结构或 G0I结构， 所述半导体衬 底的掺杂浓度在 1 *1(^到 l*l (Tcm :'之间。
优选地， 所述场效应晶体管进一步包括形成在所述半导体衬底中的浅槽隔离结构、 位 于所述栅极结构两侧的侧墙结构。
优选地， 所述的金属半导体化合物为硅化镍、 锗化镍、 硅化钴、 锗化钴、 硅化钛、 锗 化钛、 硅化铂、 锗化铂中的任意一种或者它们之中几种的混合物。
本发明的另一目的是提供一种制备上述不对称型源漏场效应晶体管的方法， 包括如下 步骤：
a，提供一个半导体衬底， 用浅槽隔离工艺形成隔离结构； ' b,形成第一绝缘介质层， 接着在所述第一绝缘介质层上形成一个电极层， 然后通过光 刻、 刻蚀工艺对所述电极层和所述第一绝缘层进行图形化刻蚀从而形成栅极结构及其两侧 的源极区域和漏极区域；
c,淀积形成第二绝缘介质层；
d,利用选择性各向异性刻蚀工艺对所述第二绝缘介质层进行刻蚀， 从而沿着所述栅极 结构两侧形成侧墙结构；
e,进行离子注入， 选择注入角度 α使得源极区域或漏极区域部分有离子到达， 进行退 火使注入的离子激活， 在源极区域和漏极区域形成 ΡΝ结；
f， 淀积一金属层， 退火后所述金属层和所述源极区域和漏极区域内暴露出来的所述半 导体衬底反应形成金属半导体化合物导体层， 除去未与上述半导体衬底反应的所述金属 层。
本发明提供另一种制备所述不对称型源漏场效应晶体管的方法， 包括如下步骤： a,提供一个半导体衬底， 用浅槽隔离工艺形成隔离结构； b,形成第一绝缘介质层， 接着在所述第一绝缘介质层上形成一个电极层， 然后通过光 刻、 刻蚀工艺对所述电极层和所述第一绝缘层进行图形化刻蚀从而形成栅极结构及其两侧 的源极区域和漏极区域；
c,进行第一次离子注入， 选择注入角度 α使得源极区域或漏极区域部分有离子到达， 进行退火使注入的离子激活， 在源极区域和漏极区域形成 ΡΝ结；
d，淀积形成第二绝缘介质层；
e, 利用选择性各向异性刻蚀工艺对所述第二绝缘介质层进行刻蚀， 从而沿着所述栅 极结构两侧形成侧墙结构， 侧墙结构的厚度应小于栅极结构的高度与 tana的乘积；
f,淀积一金属层， 退火后所述金属层和所述源极区域和漏极区域内暴露出来的所述半 导体衬底反应形成金属半导体化合物导体层， 除去未与上述半导体衬底反应的所述金属 层。
优选地， 以上两种方法中所述半导体衬底是硅、 锗、 锗硅合金、 S0I结构或 G0I结构。 优选地， 以上两种方法所述第一绝缘介质层为二氧化硅、 氮化硅、 氧化铝或袷基高介 电常数介质材料。
优选地， 以上两种方法所述的电极层包含至少一个导电层， 所述导电层为多晶硅、 氮 化钛、 氮化钽、 钨金属、 金属硅化物中的任意一种或者为它们之间的多层结构。
优选地， 以上两种方法通过所述离子注入在所述半导体衬底中形成的杂质峰值浓度不 低于 l*1019crtT'。
优选地， 以上两种方法所述金属层为镍、 钴、 钛、 铂中的任意一种或者为它们之间的 混合物。
优选地， 以上两种方法所述金属半导体化合物导体层为硅化镍、 锗化镍、 硅化钴、 锗 化钴、 硅化钛、 锗化钛、 硅化铂、 锗化铂中的任意一种或者它们之中几种的混合物。
本发明具有工作电流高、 开关速度快、 漏电流小， 击穿电压高等优点。
这些目标以及本发明的内容和特点， 将经过下面的附图说明进行详细的讲解。 附图说明
图 1是本发明一个实例中使用的半导体衬底在形成浅槽隔离结构后的截面示意图。 图 2是继图 1后在半导体衬底上形成第一绝缘介质层和电极层后的截面示意图。 图 3是继图 2后通过光刻和刻蚀方法形成栅极结构后的截面示意图。
图 4是继图 3后淀积形成第二绝缘介质层后的截面示意图。
图 5是继图 4后进行刻蚀步骤形成侧墙结构后的截面示意图。 · 图 6是继图 5后进行离子注入并退火后的截面示意图。
图 7是继图 6后淀积金属层后的截面示意图。
图 8 是继图 7 后退火并除去金属层后形成的不对称型源漏场效应晶体管的截面示意 图 9是继图 3后进行离子注入并退火后的截面示意图。
图 10是继图 9后淀积形成第二绝缘介质层后的截面示意图。
图 11是继图 10后进行刻蚀步骤形成侧墙结构后的截面示意图。
图 12是继图 1 1后淀积金属层后的截面示意图。
图 13是继图 12后退火并除去金属层后形成的不对称型源漏场效应晶体管的截面示意
具体实施方式
下面结合附图对本发明提出的不对称型源漏场效应晶体管结构与制造工艺进行详细 的描述。 后面的描述中， 相同的附图标记表示相同的组件， 对其重复描述将省略。 在后面 的参考附图中， 为了方便说明， 放大或者縮小了不同层和区域的尺寸， 所以所示大小并不 一定代表实际尺寸， 也不反映尺寸的比例关系。
应当注意的是在不偏离本发明的精神和范围的情况下还可以构成许多有很大差别的 实施例。 应当理解， 除了如所附的权利要求所限定的， 本发明不限于在说明书中所述的具 体实例。
图 1是本发明一个实例中使用的半导体衬底形成浅槽隔离结构后的截面示意图。 首先 准备硅衬底 101并完成生长前的各项工艺如清洗和去除硅表面的天然二氧化硅薄层等。 在 该实例中， 所述的半导体衬底为单晶硅。 然后使用浅槽隔离工艺在晶体管周围制造隔离结 构 102。 ·
如图 2所示， 首先在衬底上形成第一绝缘介质层 203。 然后再在第一绝缘介质层 203 上形成一层电极层 204。
如图 3所示， 通过光刻和刻蚀工艺对电极层和第一绝缘介质层进行图形化处理， 从而 形成栅极结构及其两侧的源极区域和漏极区域。
如图 4所示， 继续淀积形成第二绝缘介质层 305。 然后利用干法刻蚀工艺对该绝缘介 质层进行各向异性刻蚀， 从而沿着栅极结构两侧形成侧墙结构 315， 此时截面形状如图 5 所示。 '
如图 6所示， 进行离子注入， 选择注入角度 α使得源极区域或漏极区域部分有离子到 达，进行退火使注入的离子激活，在半导体衬底中形成掺杂类型与衬底相反的区域 406, 406 与硅衬底 101形成 PN结。
如图 7所示， 在衬底上淀积一金属层 507, 507为镍、 钴、 钛、 铂中的任意一种或者为 它们之间的混合物， 退火后 507和源极区域、 漏极区域曝露出来的衬底反应生成金属半导 体化合物。
如图 8所示，除去剩余未反应的金属层 507后金属半导体化合物导体层 517裸露出来， 517 为硅化镍、 锗化镍、 硅化钴、 锗化钴、 硅化钛、 锗化钛、 硅化铂、 锗化铂中的任意一 种或者为它们之间的混合物。 在不偏离本发明精神的基础上， 也可以选用其他工艺方法形 成导体层 517。
下面描述根据本发明制备不对称型源漏场效应晶体管的又一个实例：
图 1是本发明一个实例中使用的半导体衬底形成浅槽隔离结构后的截面示意图。 首先 准备硅衬底 101并完成生长前的各项工艺如清洗和去除硅表面的天然二氧化硅薄层等。 在 该实例中， 所述的半导体衬底为单晶硅。 然后使用浅槽隔离工艺在晶体管周围制造隔离结 构 102。
如图 2所示， 首先在衬底上形成第一绝缘介质层 203。 然后再在第一绝缘介质层 203 上形成一层电极层 204。
如图 3所示， 通过光刻和刻蚀工艺对电极层和第一绝缘介质层进行图形化处理， 从而 形成栅极结构及其两侧的源极区域和漏极区域。
如图 9所示， 进行离子注 Λ, 选择注入角度， 使得源极区域或漏极区域部分有离子到 达，进行退火使注入的离子激活，在半导体衬底中形成掺杂类型与衬底相反的区域 606, 606 与 101形成 PN结。
如图 10所示， 淀积形成第二绝缘介质层 705。然后利用干法刻蚀工艺对该绝缘介质层 进行各向异性刻蚀， 从而沿着栅极结构两侧形成侧墙结构 715， 715 的厚度应小于栅极结 构的高度与 tana的乘积， 即保证有部分衬底 101暴露出来， 此时截面形状如图 1 1所示。
如图 12所示， 在衬底上淀积一金属层 807, 807为镍、 钴、 钛、 铂中的任意一种或者 为它们之间的混合物， 退火后 807和源极区域、 漏极区域曝露出来的衬底反应生成金属半 导体化合物。
如图 13所示， 除去剩余未反应的金属层 807后所述金属半导体化合物导体层 817裸 露出来， 817与 101 形成肖特基结， 与 606形成欧姆接触。 817为硅化镍、 锗化镍、 硅化 钴、 锗化钴、 硅化钛、 锗化钛、 硅化铂、 锗化铂中的任意一种或者为它们之间的混合物。 在不偏离本发明精神的基础上， 也可以选用其他工艺方法形成导体层 817。

Claims

权 利 要 求 书
1、 一种场效应晶体管结构， 其结构包括： 半导体衬底、 栅极结构、 分别为混合结和 PN结的源区和漏区， 其特征在于： 所述源区与漏区结构不对称， 其一由 PN .结构成， 另外 一个由混合结构成， 所述混合结由肖特基结和 PN结混合构成。
2、 根据权利要求 1 所述的场效应晶体管， 其特征在于： 所述肖特基结由金属半导体 化合物和所述半导体衬底接触构成， 所述 PN 结是通过注入与所述半导体衬底掺杂类型不 同的杂质离子并通过随后的热退火处理形成。
3、 根据权利要求 2 所述的场效应晶体管， 其特征在于： 所述混合结中的所述金属半 导体化合物与所述半导体衬底形成肖特基结， 并同时与所述半导体衬底中的所述源区或漏 区中的高掺杂区域形成欧姆接触。
4、 根据权利要求 1 所述的场效应晶体管， 其特征在于： 所述半导体衬底是硅、 锗、 锗硅合金、 S0I结构或 G0I结构， 所述半导体衬底的掺杂浓度在 1 * 1 (T到 l*10l9cnT'之间。
5、 根据权利要求 1 所述的场效应晶体管， 其特征在于： 所述场效应晶体管进一歩包 括形成在所述半导体衬底中的浅槽隔离结构、 位于所述栅极结构侧边的侧墙结构。
6、 根据权利要求 3 所述的场效应晶体管， 其特征在于： 所述的金属半导体化合物为 硅化镍、 锗化镍、 硅化钴、 锗化钴、 硅化钛、 锗化钛、 硅化铂、 锗化铂中的任意一种或者 它们之中几种的混合物。
7、 一种如权利要求 1所述场效应晶体管的制造方法， 其特征在于： 具体步骤为下述 2 种方案之一：
第一种：
a,提供一个半导体衬底， 用浅槽隔离工艺形成隔离结构；
b,形成第一绝缘介质层， 接着在所述第一绝缘介质层上形成一个电极层， 然后通过光 刻、 刻蚀工艺对所述电极层和所述第一绝缘层进行图形化刻蚀， 从而形成栅极结构及其两 侧的源极区域和漏极区域；
c,淀积形成第二绝缘介质层；
d,利用选择性各向异性刻蚀工艺对所述第二绝缘介质层进行刻蚀， 从而沿着所述栅极 结构两侧形成侧墙结构；
e,进行第一次离子注入， 选择注入角度 α使得源极区域或漏极区域部分有离子到达， 进行退火使注入的离子激活， 在源极区域和漏极区域形成 ΡΝ结；
f , 淀积一金属层， 退火后所述金属层和所述源极区域和漏极区域内暴露出来的所述 半导体衬底反应形成金属半导体化合物导体层， 除去未与上述半导体衬底反应的所述金属 层。
第二种： ..
a,提供一个半导体衬底， 用浅槽隔离工艺形成隔离结构；
b,形成第一绝缘介质层， 接着在所述第一绝缘介质层上形成一个电极层， 然后通过光 刻、 刻蚀工艺对所述电极层和所述第一绝缘层进行图形化刻蚀， 从而形成栅极结构及其两 侧的源极区域和漏极区域；
c,进行第一次离子注入， 选择注入角度 α使得源极区域或漏极区域部分有离子到达， 进行退火使注入的离子激活， 在源极区域和漏极区域形成 ΡΝ结；
d，淀积形成第二绝缘介质层；
e,利用选择性各向异性刻蚀工艺对所述第二绝缘介质层进行刻蚀， 从而沿着所述栅极 结构两侧形成侧墙结构， 侧墙结构的厚度小于栅极结构的高度与 tanoc的乘积：
f,淀积一金属层， 退火后所述金属层和所述源极区域和漏极区域内暴露出来的所述半 导体衬底反应形成金属半导体化合物导体层， 除去未与上述半导体衬底反应的所述金属 层。
8、 根据权利要求 7所述的场效应晶体管的制造方法， 其特征在于： 所述半导体衬底是 硅、 锗、 锗硅合金、 S0I结构或 G0I结构。
9、 根据权利要求 7所述的场效应晶体管的制造方法， 其特征在于： 所述第一绝缘介质 层为二氧化硅、 氮化硅、 氧化铝或铪基高介电常数介质材料。
10、 根据权利要求 7 所述的场效应晶体管的制造方法其特征在于：， 所述的电极层包 含至少一个导电层， 所述导电层为多晶硅、 氮化钛、 氮化钽、 钨金属、 金属硅化物中的任 意一种或者为它们之间的多层结构。
11、 根据权利要求 7所述的场效应晶体管的制造方法， 其特征在于： 通过所述离子注 入在所述半导体衬底中形成的杂质峰值浓度不低于 i*io'9 cm— :i。
12、 根据权利要求 7所述的场效应晶体管的制造方法， 其特征在于： 所述金属层为镍、 钴、 钛、 铂中的任意一种， 或者为它们之间中几种的混合物。
13、 根据权利要求 7所述的场效应晶体管的制造方法， 其特征在于： 所述金属半导体 化合物导体层为硅化镍、 锗化镍、 硅化钴、 锗化钴、 硅化钛、 锗化钛、 硅化铂、 锗化铂中 的任意一种或者它们之中几种的混合物。
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Publication number Priority date Publication date Assignee Title
CN101887917A (zh) * 2010-06-10 2010-11-17 复旦大学 一种场效应晶体管及其制备方法
CN102446718A (zh) * 2011-09-08 2012-05-09 上海华力微电子有限公司 一种减小半导体器件热载流子注入损伤的方法
US8664072B2 (en) * 2012-05-30 2014-03-04 Globalfoundries Inc. Source and drain architecture in an active region of a P-channel transistor by tilted implantation
US9768062B1 (en) * 2016-06-16 2017-09-19 Samsung Electronics Co., Ltd. Method for forming low parasitic capacitance source and drain contacts
CN108321201B (zh) * 2017-01-16 2021-03-30 立锜科技股份有限公司 功率元件
JP2018125518A (ja) * 2017-02-03 2018-08-09 ソニーセミコンダクタソリューションズ株式会社 トランジスタ、製造方法
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
CN110350029B (zh) * 2019-06-20 2023-04-28 北京元芯碳基集成电路研究院 晶体管及其制造方法
US10892362B1 (en) * 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
US11522053B2 (en) 2020-12-04 2022-12-06 Amplexia, Llc LDMOS with self-aligned body and hybrid source
US11205737B1 (en) 2021-05-03 2021-12-21 King Abdulaziz University Photomemcapacitor and method for the production thereof
WO2022233045A1 (zh) * 2021-05-07 2022-11-10 华为技术有限公司 一种低功耗冷源场效应晶体管及其制造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750088B2 (en) * 2001-09-28 2004-06-15 Oki Electric Industry Co., Ltd. SOI MOS field effect transistor and manufacturing method therefor
CN101241912A (zh) * 2007-02-09 2008-08-13 台湾积体电路制造股份有限公司 半导体结构及其形成方法
JP2009295641A (ja) * 2008-06-02 2009-12-17 Sanken Electric Co Ltd 電界効果半導体装置及びその製造方法
CN101719517A (zh) * 2009-11-19 2010-06-02 复旦大学 一种肖特基隧穿晶体管结构及其制备方法
CN101807602A (zh) * 2010-03-25 2010-08-18 复旦大学 一种不对称型源漏场效应晶体管及其制备方法
CN101834141A (zh) * 2010-04-28 2010-09-15 复旦大学 一种不对称型源漏场效应晶体管的制备方法
CN101887917A (zh) * 2010-06-10 2010-11-17 复旦大学 一种场效应晶体管及其制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125041A1 (en) * 2004-12-14 2006-06-15 Electronics And Telecommunications Research Institute Transistor using impact ionization and method of manufacturing the same
US7608898B2 (en) * 2006-10-31 2009-10-27 Freescale Semiconductor, Inc. One transistor DRAM cell structure
US7960223B2 (en) * 2008-06-16 2011-06-14 International Business Machines Corporation Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750088B2 (en) * 2001-09-28 2004-06-15 Oki Electric Industry Co., Ltd. SOI MOS field effect transistor and manufacturing method therefor
CN101241912A (zh) * 2007-02-09 2008-08-13 台湾积体电路制造股份有限公司 半导体结构及其形成方法
JP2009295641A (ja) * 2008-06-02 2009-12-17 Sanken Electric Co Ltd 電界効果半導体装置及びその製造方法
CN101719517A (zh) * 2009-11-19 2010-06-02 复旦大学 一种肖特基隧穿晶体管结构及其制备方法
CN101807602A (zh) * 2010-03-25 2010-08-18 复旦大学 一种不对称型源漏场效应晶体管及其制备方法
CN101834141A (zh) * 2010-04-28 2010-09-15 复旦大学 一种不对称型源漏场效应晶体管的制备方法
CN101887917A (zh) * 2010-06-10 2010-11-17 复旦大学 一种场效应晶体管及其制备方法

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