WO2011088735A1 - 一种混合结型源漏场效应晶体管及其制备方法 - Google Patents

一种混合结型源漏场效应晶体管及其制备方法 Download PDF

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Publication number
WO2011088735A1
WO2011088735A1 PCT/CN2011/000013 CN2011000013W WO2011088735A1 WO 2011088735 A1 WO2011088735 A1 WO 2011088735A1 CN 2011000013 W CN2011000013 W CN 2011000013W WO 2011088735 A1 WO2011088735 A1 WO 2011088735A1
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junction
metal
field effect
effect transistor
layer
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PCT/CN2011/000013
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English (en)
French (fr)
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吴东平
张世理
葛亮
仇志军
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复旦大学
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Priority to US13/255,498 priority Critical patent/US20120119268A1/en
Publication of WO2011088735A1 publication Critical patent/WO2011088735A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact

Definitions

  • the invention belongs to the technical field of microelectronic devices, and in particular relates to a semiconductor device structure and a preparation method.
  • the 5 field 1 ⁇ 2 transistor is an abbreviation for metal-oxide-semiconductor field effect transistor. It is a semiconductor device that uses the electric field effect to control the current in the semiconductor. It relies on only one kind of carrier to participate in conduction, so it is also called Unipolar transistor. M0S field-effect transistors can be made of semiconductor silicon or germanium, or can be made of compound semiconductor gallium arsenide. Currently, more than 3 ⁇ 4 of silicon materials are used. Generally, the MOS field effect transistor is composed of a semiconductor substrate, a source region and a drain region, a gate oxide layer, and a gate electrode.
  • the basic structure is generally a four-terminal device, and the middle portion thereof is a mountain metal-insulator-
  • the M0S capacitor structure composed of semiconductors, the two sides of the M0S capacitor are the source and drain regions respectively. Under normal working conditions, carriers will flow from the source region, flow out from the drain region, and the gate is on the insulating layer. Applying a voltage to the pole changes the electric field strength in the insulating layer and controls the electric field on the surface of the semiconductor, thereby changing the conductivity of the channel on the surface of the semiconductor.
  • the source and drain regions of a conventional MOSFET field effect transistor are purely heavily doped PN junction structures.
  • the PN junction can be formed by diffusion, ion implantation, etc., by incorporating a certain amount of impurities into the semiconductor substrate in the source and drain regions of the field effect transistor.
  • a field effect transistor having such a source-drain structure has a large series resistance, a short channel effect, and is not easily scaled down.
  • Metal silicide source and drain refers to metal silicide as the source and drain of the field effect and a Schottky junction between the metal silicide and the silicon substrate.
  • the main advantage is low parasitic resistance and excellent scaling down characteristics. , Easy process manufacturing, low thermal budget and anti-latch effect or floating body effect in silicon (S0I) on insulator.
  • field-effect transistors that are purely composed of Schottky junctions have many potential problems. Schottky junctions often have extra leakage current and soft breakdown. The reliability of such source-drain structure field-effect transistors is still Not well studied.
  • the present invention proposes a field-effect transistor with a mixed junction source and drain. .
  • the field effect transistor proposed by the present invention comprises a semiconductor substrate, a gate structure, a spacer, a source having a mixed junction, and a mixed junction and a P junction.
  • the switching characteristic of the field effect transistor is determined by the Chant base node in the mixed junction.
  • the semiconductor substrate is a silicon substrate, the Schottky junction metal silicide and the silicon substrate are formed, and the germanium junction is formed by implanting impurities different in doping type from the silicon substrate.
  • the ions are formed by subsequent thermal annealing that forms an ohmic contact with the highly doped regions of the tantalum junction.
  • the semiconductor substrate is a germanium substrate
  • the Schottky junction is composed of a metal germanide and the germanium substrate
  • the germanium junction is formed by implanting an impurity different from the germanium substrate doping type.
  • the ions are formed by subsequent thermal annealing that forms an ohmic contact with the highly doped regions of the tantalum junction.
  • the invention also provides a method for fabricating the mixed junction source-drain field effect transistor, the method comprising: providing a semiconductor substrate, and forming an isolation structure by shallow trench isolation;
  • first insulating dielectric layer Forming a first insulating dielectric layer, then forming an electrode layer on the first insulating dielectric layer, and then patterning the electrode layer and the first insulating layer by photolithography and etching to form a gate Pole structure
  • a metal layer is deposited and annealed to react the metal layer with the underlying semiconductor substrate to form a metal semiconductor compound, and the unreacted metal layer is removed.
  • the first insulating dielectric layer is any one of silicon dioxide, silicon nitride, aluminum oxide, cerium-containing sorghum medium or zirconium-containing sorghum medium, or several of them compound of.
  • the electrode layer comprises at least one conductive layer
  • the conductive layer is any one of polysilicon, titanium nitride, tantalum nitride, tungsten metal, metal silicide, or a plurality of them Layer structure.
  • a Schottky junction is formed between the metal semiconductor compound and the semiconductor substrate, and the metal---conductor compound simultaneously forms an ohmic contact with a highly doped region in the PN junction.
  • the semiconductor substrate is a silicon substrate
  • the metal layer is nickel, cobalt, titanium, platinum, any benefits in any one of 1, or a mixture of several of them
  • said metal semiconductor compound Li It is any one of nickel silicide, cobalt silicide, titanium silicide, platinum silicide, or a mixture of several of them.
  • the semiconductor substrate is a germanium substrate
  • the metal layer is any one of nickel, cobalt, titanium, platinum or a mixture thereof
  • the metal semiconductor compound is nickel telluride, germanium Any one of cobalt, titanium telluride, and platinum telluride, or a mixture of them.
  • the field effect transistor proposed by the present invention has lower source-drain leakage turbulence compared to the field effect transistor having a luted gold-based gold silicide source-drain structure, and the source-drain series is 3 ⁇ 4-resistance than the conventional heavily doped junction.
  • Type source leakage field effect crystal The source-drain series resistance is small.
  • Figure 1 is a flow chart showing the process of preparing a mixed junction source-drain field effect transistor of the present invention.
  • FIG 2-a to 2 m denotes a substrate of the present invention hybrid junction sequence prepared in Example FET source and drain process schematic sectional view.
  • Figure 1 is a flow chart showing the process of preparing a field effect transistor having a mixed junction source and drain.
  • the first germanium 100 provides a semiconductor substrate on which the field effect transistor of the present invention having a mixed junction source and drain is formed.
  • a second pass 102, the isolation structure is formed using a shallow trench isolation (STI) structure on the provided semiconductor substrate.
  • the third ⁇ 104 is formed on the semiconductor substrate on which the isolation structure has been formed.
  • the detailed description includes first forming an insulating layer on the surface of the semiconductor substrate, then depositing an electrode layer on the insulating layer, and then forming a gate structure by a photolithography and etching process.
  • a sidewall structure is formed on both sides of the gate.
  • the structure forms a first sidewall structure in a vertical direction.
  • the fifth ⁇ 108, ion implantation and annealing to form ⁇ . ⁇ ' junction Ion implantation is performed in the semiconductor substrate under the mask of the side walls on both sides of the gate structure to form a junction, and the semiconductor substrate is annealed to activate the implanted ions.
  • a second sidewall structure is formed on both sides of the gate.
  • An insulating dielectric layer having a thickness of d2 (d2 ⁇ dl) is deposited, and the insulating dielectric layer is anisotropically etched by a dry etching process, and the remaining insulating dielectric layer is followed by etching
  • the gate structure forms a second sidewall structure thinner than the first sidewall structure in the vertical direction.
  • the eighth electrode 114 forms a metal silicide simultaneously in the source region and the drain region or the gate electrode region. Depositing a layer of gold under the mask of the second sidewall on both sides of the gate, annealing to react the metal with the underlying silicon substrate to form a metal silicide, and then removing the unreacted metal on the surface of the substrate, thereby The desired metal silicide layer is obtained on the silicon surface.
  • silicon wafer and substrate used include any structure having a bare surface on which various integrated circuit structures may already be contained.
  • substrate is also understood to include semiconductor wafers being processed, possibly including other thin film layers prepared thereon.
  • Attachment 2-a is a schematic cross-sectional view of a substrate of a process example of the present invention, comprising a semiconductor substrate 201 and an isolation trench dielectric layer 202 on which a field effect transistor of a mixed junction type source and drain is formed.
  • the semiconductor substrate 201 is not limited to a silicon material, and may further include germanium, silicon-germanium alloy and SOI (silicon on insulator) or G0I (germanium on insulator) structure substrate or other semiconductor material, which is silicon in the following description. The material is described as an example.
  • the semiconductor substrate 201 may be of a P type, such as doped with boron or indium, or may be of an N type, such as doped with phosphorus, arsenic or antimony.
  • the isolation structure between the devices is formed on the semiconductor substrate 201 by a shallow trench isolation process technique, including the insulating dielectric 202 filled in the shallow trench isolation, which may be silicon dioxide, silicon nitride or other insulating material. .
  • an insulating layer 203 is deposited on the semiconductor substrate 201.
  • the material of the insulating layer 203 may be silicon dioxide, silicon nitride, aluminum oxide, high-k dielectric containing germanium, and zirconium-containing. Any of the high K media or a mixture of several of them.
  • the insulating layer 203 is used as a gate dielectric layer of a mixed junction source-drain field effect transistor.
  • the insulating layer 203 may be formed on the upper surface of the semiconductor substrate 201 by thermal growth or by deposition.
  • an electrode layer 204 is formed on the insulating layer 203 by deposition.
  • the electrode layer 204 includes at least one conductive layer, and the conductive layer may be polysilicon, titanium nitride, tantalum nitride, or tungsten metal.
  • the metal silicide or the multilayer structure formed by them, the electrode layer 204 is used as a gate electrode of the mixed junction type source/drain transistor.
  • the electrode layer 204 and the insulating layer 203 are patterned and etched by photolithography and etching processes to form a gate structure of the hybrid junction type source-drain transistor as described in the present invention.
  • an insulating layer 205 having a thickness dl is deposited, which may be silicon dioxide, silicon nitride or a mixture thereof, but may not be isolated from the shallow trenches described above.
  • the insulating medium 202 used is of the same material.
  • the insulating layer 205 is anisotropically etched by a thousand etching process. When the surface of the semiconductor substrate 201 or the surface of the semiconductor substrate 201 is exposed, it is an end point of the etch. After etching the insulating layer 205, a spacer structure 206 formed along the gate structure in the vertical H direction remains.
  • the transistor is ion implanted under the masking of the sidewall structure 206 on either side of the gate structure.
  • the source-drain implanted ions are N-type impurities such as phosphorus or arsenic; if the semiconductor substrate is N-type, the source-drain implanted ions are P-type impurities such as boron or indium. Annealing is performed to electrically activate the implanted various impurity ions.
  • a PN junction 207 is formed between the source region and the semiconductor substrate 201 and the drain region and the semiconductor substrate 201, respectively.
  • the insulating layer 205 is different from the insulating medium 202 used in the shallow trench isolation, and the gate electrode can be anisotropically etched, isotropically etched, or both.
  • the thicker side walls 206 on the sides are removed to prepare for subsequent deposition of the metal to form a Schottky junction.
  • an insulating layer 208 having a thickness d2 (d2 ⁇ dl) is deposited, and the insulating layer 208 may be silicon dioxide, silicon nitride or a mixture thereof. .
  • the insulating dielectric layer 208 is anisotropically etched by a dry etching process. When the surface of the electrode layer 204 or the semiconductor substrate 201 is exposed, it is a dry etching end point. After etching the insulating dielectric layer 208, a spacer structure 209 is formed which is formed in the vertical direction along the gate structure. The lateral width of the side wall 209 is smaller than the width of the side wall 206 described above.
  • a layer of metal 210 is deposited which may be nickel, cobalt, titanium, platinum or an alloy therebetween.
  • Annealing is performed as shown in Figure 2-1 to react the metal 210 with the exposed silicon substrate to form a metal silicide.
  • the metal silicide is nickel silicide, cobalt silicide, titanium silicide, platinum silicide or a mixture of several of them.
  • the unreacted metal is removed to obtain the desired metal silicide layer 211. Normally, annealing is performed again to make the resulting metal silicide 21 1 more stable.
  • the substrate is lightly doped, and the formed gold sulphide 21 1 near the gate electrode forms a Schottky junction with the silicon substrate and forms an ohmic contact with the heavily doped ion implantation region.
  • a metal silicide 212 is also formed on the top of the gate.
  • a metal oxide-semiconductor field effect transistor with a mixed junction source and drain is formed, including gate structures 203 and 204, an isolation structure 202, sidewall spacers 209 on both sides of the gate structure, and a semiconductor lining.
  • the source and drain structures formed by the bottom 201 and the ⁇ ⁇ junction and the Schottky junction.
  • the portion of the metal silicide layer 211 close to the gate electrode forms a Schottky junction with the silicon substrate, which in turn forms an ohmic contact with the high-doping region of the upper surface of the tantalum junction 207.
  • the hybrid junction source-drain field effect transistor is characterized in that: the switching characteristics of the field effect transistor are determined by the Schottky junction in the hybrid junction, and thus can be classified as a special-junction junction field effect transistor, while the source region and the drain region are Most regions form a ⁇ junction between the substrate and the substrate, thus having a low source-drain leakage current characteristic compared to a pure Schottky junction field effect transistor.

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Description

一种混合结型源漏场效应晶体管及其制备方法
技术领域
本发明属于微电子器件技术领域， 具体涉及半导体器件结构和制备方法。
背景技术 1
5场½应晶体管 （M0SFET ) 是金属 -氧化物-半导体场效应晶体管的简称， 是利用电 场效应来控制半导体中电流的一种半导体器件， 只依靠一种载流子参与导电， 故又称 为单极型晶体管。 M0S场效应晶体管可以用半导体硅、 锗为材料， 也可用化合物半导体砷 化镓等材料制作， 目前以使用硅材料的 ¾多。通常 M0S场效应晶体管由半导体衬底、源区和 漏区、 栅氧化层以及栅电极等几个主耍部分组成， 其基本结构一般是一个四端器件， 它的 中间部分是山金属 -绝缘体-半导体组成的 M0S电容结构， M0S电容的两侧分别是源区和漏区， 在正常的工作状态下， 载流子将从源区流入， 从漏区流出， 绝缘层上为栅极， 在栅极上施 加电压， 可以改变绝缘层中的电场强度， 控制半导体表面电场， 从而改变半导体表面沟道 的导电能力。
常规 M0S场效应晶体管的源区和漏区是纯粹重掺杂 PN结结构。 这种 PN结可以采用扩散、 离子注入等制造工艺， 将一定数量的杂质掺入半导体衬底在场效应晶体管的源区和漏区形 成。 然而， 具有这种源漏结构的场效应晶体管其串联电阻比较大， 短沟道效应严重， 且不 易按比例缩小。
如果将金属硅化物源漏来代替传统的重掺杂 结源漏并应用在未来超缩微化的 CMOS 器件中， 将会在一定程度上提高场效应晶体管的性能。 金属硅化物源漏是指金属硅化物作 为场效应的源极和漏极并且金属硅化物和硅衬底之间形成肖特基结， 其主要优势是低的寄 生电阻， 优良的按比例缩小特性， 简便的工艺制造， 低的热预算以及抗闩锁效应或者绝缘 体上的硅（S0I )里的浮体效应。 然而， 纯粹由肖特基结组成源漏的场效应晶体管也有许多 潜在的问题， 肖特基结常存在额外的漏电流和软击穿， 这种源漏结构的场效应晶体管的可 靠性目前还没有得到很好的研究。
发明内容
为了解决传统重掺杂 PN 结型源漏场效应晶体管的高源漏串联电阻和肖特基结场效应 晶体管高源漏泄漏电流等问题， 本发明提出一种混合结型源漏的场效应晶体管。
本发明提出的场效应晶体管， 其包括半导体衬底、 栅极结构、 侧墙、 具有混合结的源 和 ， 所述混合结山 特基结和 P 结混合构成。
优选地， 所述场效应晶体管的丌关特性 ώ所述混合结中的所述尚特基结决定。 优选地， 所述半导体衬底为硅衬底， 所述肖特基结 ώ金属硅化物和所述硅衬底构成， 所述 ΡΝ结是通过注入与所述硅衬底掺杂类型不同的杂质离子并通过随后的热退火形成，所 述金属硅化物与所述 ΡΝ结中高掺杂的区域形成欧姆接触。
优选地， 所述半导体衬底为锗衬底， 所述肖特基结由金属锗化物和所述锗衬底构成， 所述 ΡΝ结是通过注入与所述锗衬底掺杂类型不同的杂质离子并通过随后的热退火形成，所 述金属锗化物与所述 ΡΝ结中高掺杂的区域形成欧姆接触。
本发明还提出所述混合结型源漏的场效应晶体管的制备方法， 该方法包括： 提供一个半导体衬底， 用浅沟槽隔离形成隔离结构；
形成第一绝缘介质层，接着在所述第一绝缘介质层上形成一个电极层，然后通过光刻、 刻蚀工艺对所述电极层和所述第一绝缘层进行图形化刻蚀从而形成栅极结构；
淀积形成第二绝缘介质层， 利用各向异性千法刻蚀工艺对所述第二绝缘介质层进行刻 蚀， 从而沿着所述栅极结构两侧形成第一侧墙结构；
离子注入， 在半导体衬底形成 P '结， 再进行退火， 使注入的离子激活；
刻蚀除去栅极两侧的第一侧墙结构， 淀积形成第三绝缘介质层， 利用各向异性千法刻 蚀工艺对所述第三绝缘介质层进行刻蚀， 从而形成第二侧墙结构；
淀积一金属层， 进行退火从而使所述金属层和其下的所述半导体衬底反应生成金属半 导体化合物， 再除去未反应的所述金属层。
优选地， 所述的第一绝缘介质层为二氧化硅、 氮化硅、 氧化铝、 含铪的高 Κ介质或含 锆的高 Κ介质中的任意一种， 或者为它们之中几种组成的化合物。
优选地， 所述的电极层包含至少一个导电层， 所述导电层为多晶硅、 氮化钛、 氮化钽、 钨金属、 金属硅化物中的任意一种， 或者为它们之中几种的多层结构。
优选地， 所述金属半导体化合物和所述半导体衬底之间形成肖特基结， 且所述金属- ·- 导体化合物同时和所述 PN结中的高掺杂区域形成欧姆接触。
优选地， 所述半导体衬底为硅衬底， 所述的金属层为镍、 钴、 钛、 铂中的任意任意一 利1 , 或为它们之中几种的混合物， 所述金厲半导体化合物为硅化镍、 硅化钴、 硅化钛、 硅 化铂中的任意一种， 或为它们之中几种组成的混合物。
优选地， 所述半导体衬底为锗衬底， 所述的金属层为镍、 钴、 钛、 铂中的任意一种或 为它们组成的混合物， 所述金属半导体化合物为锗化镍、 锗化钴、 锗化钛、 锗化铂中的任 意一种， 或为它们之中儿种组成的混合物。
冋具有 ί特基结金屈硅化物源漏结构的场效应晶体管相比， 本发明提出的场效应晶体 管具有较低的源漏泄漏屯流，同时其源漏串联¾阻比传统重掺杂 结型源漏场效应晶体 的源漏串联电阻要小。
这些 I目标以及本发明的内容和特点， 将经过下面的的工艺实例图进行详细的讲解， 实 例图中相同的附图标记表示相同的组件。
附图说明
图 1表示本发明制备混合结型源漏场效应晶体管的工艺流程图。
图 2-a至图 2 m表示本发明按顺序制备混合结型源漏场效应晶体管工艺实例的衬底截面 示意图。
具体实施方式
下面结合附图和具体工艺实例对本发明提出的制备混合结型源漏场效应晶体管进行详 细的描述。
后面的描述中， 相同的附图标记表示相同的组件， 对其重复描述将省略。 在其后的附 图中， 为了便于说明和观察本发明的工艺流程， 放大或者缩小了不同层和区域的尺寸， 所 以附图中所示大小不一定代表实际尺寸， 也不反映尺寸的比例关系。 附图是本发明的理想 化实施例的示意图， 本发明所示的实施例不应该被认为仅限于图中所示区域的特定形状， 而是包括所得到的形状， 比如制造引起的偏差。 例如刻蚀得到的曲线通常具有弯曲或圆润 的特点， 但在本发明实施例中， 均以矩形表示， 图中的表示是示意性的。
图 1表示本发明制备具有混合结型源漏的场效应晶体管的工艺流程图。
第一歩 100, 提供一个半导体衬底， 在该半导体衬底上形成本发明所述的具有混合结 型源漏的场效应晶体管。
第二歩 102， 在所提供的半导体衬底利用浅沟槽隔离 （STI ) 结构形成隔离结构。 第三歩 104 , 在上述已形成隔离结构的半导体衬底上形成栅极结构。 本歩骤详细包括 先在该半导体衬底表面形成一个绝缘层， 接着在该绝缘层上淀积一个电极层， 然后通过光 刻、 刻蚀工艺形成栅极结构。
第四歩 106, 在栅极两侧形成侧墙结构。在以上所述半导体衬底淀积一层厚度为 dl绝 缘介质层， 再利用干法刻蚀工艺对该绝缘介质层进行各向异性刻蚀， 刻蚀之后剩下的绝缘 介质层沿着栅极结构在竖直方向形成第一侧墙结构。
第五歩 108， 进行离子注入和退火形成 Ρ.\'结。 在栅极结构两侧侧墙的掩蔽下向半导体 衬底中进行离子注入形成 结， 再将上述半导体衬底进行退火， 使注入的离子激活。
第六歩 1 10， 刻蚀栅极两侧第一侧墙。 将栅极两侧第一侧墙刻蚀掉。
第七步 112， 在栅极两侧形成第二侧墙结构。 淀积一层厚度为 d2 (d2<dl )的绝缘介质 层， 利用干法刻蚀工艺对该绝缘介质层进行各向异性刻蚀， 刻蚀之后剩下的绝缘介质层沿 着栅极结构在竖直方向形成比第一侧墙结构薄的第二侧墙结构。
第八歩 114 , 在源区和漏区或栅电极区同时形成金属硅化物。 在上述栅极两侧第二侧 墙的掩蔽下淀积一层金屈， 进行退火从而使金属和其下的硅衬底反应生成金属硅化物， 再 除去衬底表面未反应的金属， 从而在硅表面上得到所需的金属硅化物层。
下文结合附图 2-a至附图 2- m对本发明制备混合结型源漏场效应晶体管的工艺流程加 以详细说明。
在下面的描述中， 所使用的术语硅片和衬底包括任何具有裸露表面的结构， 其上可能 已经含有各种集成电路结构。 术语衬底也可以理解为包括正在工艺加工中的半导体硅片， 可能包括在其上所制备的其它薄膜层。
附阁 2- a是本发明一个工艺实例的衬底截面示意图， 包含半导体衬底 201和隔离槽介 质层 202 , 在该半导体衬底上形成混合结型源漏的场效应晶体管。 半导体衬底 201不限定 于硅材料， 还可包括锗， 硅-锗合金及 S0I (绝缘体上的硅） 或 G0I (绝缘体上的锗） 结构 衬底或者其他半导体材料， 在后续的描述中以硅材料为例进行说明。 半导体衬底 201可以 为 P型， 比如用硼或铟等进行掺杂； 也可以为 N型， 比如用磷、 砷或锑等进行掺杂。 通过 浅沟槽隔离工艺技术在半导体衬底 201上形成器件之间的隔离结构， 包含浅沟槽隔离中填 充的绝缘介质 202， 该绝缘介质 202可以是二氧化硅、 氮化硅或其它绝缘材料。
如附图 2 b所示， 在上述半导体衬底 201上淀积一层绝缘层 203， 绝缘层 203的材料 可以是二氧化硅、 氮化硅、 氧化铝、 含铪的高 K介质和含锆的高 K介质中的任意一种或它 们之中几种的混合物。 该绝缘层 203用来作为混合结型源漏场效应晶体管的栅介质层。 绝 缘层 203可以通过热生长方式也可以通过淀积方式生成在半导体衬底 201的上表面。
如附图 2- c所示， 在上述绝缘层 203上通过淀积形成电极层 204， 电极层 204至少包 含一层导电层， 该导电层可以是多晶硅、 氮化钛、 氮化钽、 钨金属、 金属硅化物或者它们 之问形成的多层结构， 电极层 204用来作为混合结型源漏晶体管的栅电极。
如附图 2 d所示， 通过光刻和刻蚀工艺对电极层 204和绝缘层 203进行图形化刻蚀， 形成如本发明所描述的混合结型源漏晶体管的栅极结构。
如附图 2- c所示， 淀积一层厚度为 dl的绝缘层 205 , 该绝缘层可以是二氧化硅、 氮化 硅或者为它们之问的混合物，但不能与上述浅沟槽隔离中使用的绝缘介质 202的材料相同。
如附图 2- f所示， 再利用千法刻蚀工艺对上述绝缘层 205进行各向异性刻蚀， 当导 ¾ J¾ 204或者半导体衬底 201表面暴露出来吋， 为千法刻蚀终点。 刻蚀绝缘层 205之后剩下 沿栅极结构在竖 H方向形成的侧墙结构 206。
如附图 2 g所示， 在栅极结构两侧的侧墙结构 206的掩蔽下对晶体管进行离子注入。 如果半导体衬底是 P型， 源漏注入的离子为磷或砷等 N型杂质； 如果半导体衬底是 N型， 源漏注入的离子则为硼或铟等 P型杂质。 进行退火， 使注入的各种杂质离子电激活。 通过 以上步骤， 在源区与半导体衬底 201和漏区与半导体衬底 201之间分别形成 PN结 207。
如附图 2- h所示， 绝缘层 205和浅沟槽隔离中的使用的绝缘介质 202不同， 可以利用 各向异性刻蚀， 各向同性刻蚀或者兼有两者的方式将栅极两侧的较厚侧墙 206去除， 为后 续淀积金属形成肖特基结做准备。
如附图 2- i所示，在完成上述工艺流程之后淀积一层厚度为 d2 ( d2<dl )的绝缘层 208， 绝缘层 208可以是二氧化硅、 氮化硅或者它们之间的混合物。
如附图 2-j所示， 再利用干法刻蚀工艺对该绝缘介质层 208进行各向异性刻蚀， 当电 极层 204或者半导体衬底 201表面暴露出来时， 为干法刻蚀终点。 刻蚀绝缘介质层 208之 后剩下沿栅极结构在竖直方向形成的侧墙结构 209。 侧墙 209的横向宽度比前述侧墙 206 的宽度要小。
如附图 2-k所示， 淀积一层金属 210， 可以是镍、 钴、 钛、 铂或者为它们之间的合金。 如附图 2-1所示， 进行退火， 使金属 210和裸露在外的硅衬底反应生成金属硅化物。 金属硅化物为硅化镍、 硅化钴、 硅化钛、 硅化铂或者为它们之中几种的混合物。 除去表面 未反应的金属， 从而得到所需的金属硅化物层 211。 通常情况下， 再次进行退火， 使得生 成的金属硅化物 21 1更加稳定。
ώ于衬底是的掺杂较轻， 形成的金屈硅化物 21 1靠近栅电极的部分与硅衬底形成肖特 基结， 而与重掺杂的离子注入区形成欧姆接触。
如附图 2- m所示， 如果在栅极 204上表面覆盖有多晶硅， 那么同时也会在栅极的顶部 形成金属硅化物 212。
基于上述工艺， 一种混合结型源漏的金属一氧化物一半导体场效应晶体管就形成了， 包括栅极结构 203和 204， 隔离结构 202, 位于栅极结构两侧的侧墙 209， 半导体衬底 201 和 ώ Ρ 结和肖特基结混合形成的源漏结构。金属硅化物层 211靠近栅电极的部分和硅衬底 形成肖特基结， 同吋又和 ΡΝ结 207的上表面高惨杂区域形成欧姆接触。这种混合结型源漏 场效应晶体管的特征在于： 场效应晶体管的开关特性由混合结中的肖特基结决定， 因此可 以归类为 特基结场效应晶体管， 同时源区和漏区的大部分区域和衬底之间形成 ΡΝ结， 因 此和纯粹的肖特基结场效应晶体管相比拥有低源漏泄漏电流的特性。
应当注意的是在不偏离本发明的精神和范围的情况下还可以构成许多有很大差别的实 施例。 应当理解， 除了如所附的权利耍求所限定的， 本发明不限于在说明书中所述的具体 实施例。

Claims

权 利 要 求 书
1. 一种场效应晶体管， 其特征在于： 包括半导体衬底、 栅极结构、 侧墙、 具有混合 结的源区和漏区， 所述混合结由肖特基结和 P 1结混合构成。
2.根据权利要求 1所述的场效应晶体管， 其特征在于： 所述场效应晶体管的开关特性 ώ所述混合结中的所述肖特基结决定。
3. 根据权利要求 1 所述的场效应晶体管， 其特征在于： 所述半导体衬底为硅衬底， 所述肖特基结由金属硅化物和所述硅衬底构成， 所述 ΡΝ 结是通过注入与所述硅衬底掺杂 类型不同的杂质离子并通过随后的热退火形成， 且所述金属硅化物与所述 ΡΝ 结中高掺杂 的区域形成欧姆接触。
4. 根据权利要求 1 所述的场效应晶体管， 其特征在于： 所述半导体衬底为锗衬底， 所述肖特基结由金属锗化物和所述锗衬底构成， 所述 Ρ.Ν 结是通过注入与所述锗衬底掺杂 类型不同的杂质离子并通过随后的热退火形成， 所述金属锗化物与所述 P ' 结中高掺杂的 区形域成欧姆接触。
5.一种如权利要求 1所述场效应晶体管的制备方法， 其特征在于包括：
提供一个半导体衬底， 用浅沟槽隔离形成隔离结构；
形成第一绝缘介质层，接着在所述第一绝缘介质层上形成一个电极层，然后通过光刻、 刻蚀工艺对所述电极层和所述第一绝缘层进行图形化刻蚀从而形成栅极结构；
淀积形成第二绝缘介质层， 利用各向异性千法刻蚀工艺对所述第二绝缘介质层进行刻 蚀， 从而沿着所述栅极结构两侧形成第一侧墙结构；
离子注入， 在半导体衬底形成 ΡΝ结， 再进行退火， 使注入的离子激活；
刻蚀除去栅极两侧的第一侧墙结构， 淀积形成第三绝缘介质层， 利用各向异性干法刻 蚀工艺对所述第三绝缘介质层进行刻蚀， 从而形成第二侧墙结构；
淀积一金属层， 进行退火从而使所述金属层和其下的所述半导体衬底反应生成金屈半 导体化合物， 再除去未反应的所述金属层。
6. 根据权利要求 5 所述的方法， 其特征在于所述的第一绝缘介质层为二氧化硅、 ί 化硅、 氧化铝、 含铪的高 Κ介质或含锆的高 Κ介质中的任意一种， 或者为它们之中几种组 成的化合物。
7. 根据权利耍求 5 所述的方法， 其特征在于所述的电极层包含至少一个导电层， 所 述导¾层为多晶硅、 氮化钛、 氮化钽、 钨金属、 金属硅化物中的任意一种， 或者为它们之 中儿种的多层结构。
8. 根据权利耍求 5所述的方法， 其特征在于所述金属半导体化合物和所述半导体衬底 之间形成肖特基结， 且所述金属半导体化合物同时和所述 PN结中的高掺杂区域形成欧姆接 触。
9. 根据权利要求 5所述的方法， 其特征在于所述半导体衬底为硅衬底， 所述的金属层 为镍、 钴、 钛、 铂中的任意一种， 或为它们之中几种组成的混合物； 所述金属半导体化合 物为硅化镍、 硅化钴、 硅化钛、 硅化铂中的任意一种， 或为它们之中几种组成的混合物。
10.根据权利耍求 7 所述的方法， 其特征在于所述半导体衬底为锗衬底， 所述的金属 层为镍、 钴、 钛、 铂中的任意一种， 或为它们之中几种组成的混合物； 所述金属半导体化 合物为锗化镍、 锗化钴、 锗化钛、 锗化铂中的任意一种， 或为它们之中几种组成的混合物。
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