WO2012071814A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2012071814A1
WO2012071814A1 PCT/CN2011/071356 CN2011071356W WO2012071814A1 WO 2012071814 A1 WO2012071814 A1 WO 2012071814A1 CN 2011071356 W CN2011071356 W CN 2011071356W WO 2012071814 A1 WO2012071814 A1 WO 2012071814A1
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source
metal silicide
drain
semiconductor device
substrate
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PCT/CN2011/071356
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English (en)
French (fr)
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罗军
赵超
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中国科学院微电子研究所
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Priority to US13/380,096 priority Critical patent/US20120139047A1/en
Publication of WO2012071814A1 publication Critical patent/WO2012071814A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

Definitions

  • the present application relates to a semiconductor device and a method of fabricating the same, and, in particular, to a MOSFET structure having an epitaxially grown ultrathin metal silicide source/drain and a method of fabricating the same. Background technique
  • the source-drain series resistance When the channel is long, the channel resistance is much larger than the source-drain series resistance, and the effect of parasitic series resistance can be ignored. However, the source-drain resistance does not decrease proportionally as the channel size shrinks. In particular, the contact resistance increases approximately squarely as the size decreases, causing the equivalent operating voltage to drop. If the conventional highly doped source/drain is replaced with a metal silicide source and drain in the existing MOSFET fabrication technology, the parasitic series resistance and contact resistance can be greatly reduced.
  • FIG. 1 it is a schematic diagram of an existing metal silicide source/drain MOSFET (also referred to as a Schottky barrier source/drain MOSFET), on a bulk silicon substrate 10 or a silicon-on-insulator (S0I) substrate.
  • Metal silicide source and drain regions 30 and 31 are formed on both sides of the channel region 20 or 21 in the gate region, and a gate structure 40/41 and a gate spacer 50/51 are sequentially formed on the channel region, wherein the metal silicide is completely As a source/drain material that directly contacts the channel.
  • a shallow trench isolation STI 60/61 can also be placed in the device substrate. The STI is not directly between the bulk silicon substrate and the SOI substrate, but for the sake of convenience, the two substrates are not connected.
  • This metal silicide source-drain MOSFET has excellent scale-down characteristics and is easy to manufacture, thus attracting widespread attention and becoming one of the hotspots of current MOSFET technology development.
  • the driving ability of a metal silicide source-drain MOSFET is controlled by the Schottky barrier height (SBH) between its source and channel. As the SBH decreases, the drive current increases. The results of the device simulation show that when the SBH is reduced to about 0. leV, the metal silicide source/drain MOSFET is reachable. To the same drive capability as conventional MOSFETs.
  • SBH Schottky barrier height
  • FIG. 2 a schematic diagram of a method for reducing SBH using silicide as doped source technology (SADS).
  • SADS silicide as doped source technology
  • metal silicide source/drain MOSFETs are reduced in size to sub-20 nm gate lengths, the thickness of metal silicide source drains also needs to be reduced to control short channel effects (SCEs), especially for those formed on SOI substrates.
  • SCEs short channel effects
  • the metal silicide source-drain MOSFET before shrinking size has a longer channel region 20/21, and the metal silicide source/drain film 30/31 is thicker, and its thermal stability is better when annealed.
  • the metal silicide source leaks thinner, its thermal stability also deteriorates.
  • FIG. 3 after the size is reduced, the channel 20/21 becomes shorter, and the metal silicide source/drain film 30/31 must also be thinned accordingly to better control the short channel effect, but the thinned silicide film 30 is 30.
  • /31 is poor in thermal stability during annealing, and tends to agglomerate, resulting in a sharp increase in resistivity.
  • the silicide film cannot withstand the high temperature annealing required for the separation of the doping ions at the silicide/silicon interface, and therefore, for the metal silicide source and drain MOSFET, it cannot be lowered. SBH.
  • metal silicide source-drain MOSFETs are considered to be sub-20nm next-generation CMOS structures, while existing SADS methods to reduce the SBH between the source and channel regions to improve drive capability are in channel shortening, metal silicide Thin film thinning cannot be carried out because it cannot withstand high temperature annealing.
  • the present invention provides a semiconductor device including a substrate, a channel region in the substrate, source and drain regions on both sides of the channel region, a gate structure on the channel region, and a gate electrode. a gate spacer surrounding the pole structure, wherein: the source and drain regions are formed by epitaxially grown ultra-thin metal silicide, and doped ions are present at the interface between the source and drain regions and the channel region. Separation condensation zone.
  • the epitaxially grown ultra-thin metal silicide material is NiSi 2 - y , Ni ⁇ Pt ⁇ Si ⁇ , . ( ⁇ or ⁇ , where X is greater than 0 and less than 1, and y is greater than or equal to 0 and less than 1.
  • the thickness of the epitaxially grown ultrathin metal silicide is less than or equal to 15 nm.
  • the doping ions are boron B, aluminum Al, gallium Ga, indium In; for n-type epitaxially grown ultra-thin metal silicide source-drain MOSFET, the doping ions are nitrogen N, phosphorus, arsenic As, oxygen 0 , sulfur 3, selenium Se, ⁇ Te, fluorine, chlorine chloride.
  • the substrate may be a bulk silicon or a semiconductor-on-insulator substrate.
  • the present invention also provides a method of fabricating a semiconductor device, comprising:
  • the epitaxially grown ultrathin metal silicide forms the source and drain regions of the device, and the semiconductor substrate under the gate structure forms a channel region;
  • a second annealing is performed to form a separation condensation region of dopant ions at the interface between the epitaxially grown ultra-thin source and drain regions and the channel region.
  • the epitaxially grown ultra-thin metal silicide material is NiSi 2 - y , Ni ⁇ Pt ⁇ Si ⁇ , . ( ⁇ ⁇ or ⁇ where X is greater than 0 and less than 1, and y is greater than or equal to 0 and less than 1.
  • the doping ions are boron aluminum Al, gallium Ga, and indium; for n-type epitaxially grown ultra-thin metal silicide source-drain MOSFETs, doped ions For nitrogen N, phosphorus? , arsenic As, oxygen 0, sulfur 3, selenium Se, ⁇ Te, fluorine? , Chlorine Cl.
  • the implantation dose of the implanted dopant ions is l X 10 14 cm - 2 to l X 10 16 cm - 2 .
  • the temperature of the first annealing and / or the second annealing is 500 to 850 'C.
  • the thickness of the metal layer is less than or equal to 5 nm.
  • the substrate can be a bulk silicon or a semiconductor-on-insulator substrate.
  • the epitaxially grown ultra-thin metal silicide source-drain MOSFET with doped ion separation condensation region has many advantages. First, the conventional high-doped source/drain is replaced by a metal silicide source and drain, which can greatly reduce parasitic series connection.
  • the epitaxial growth formed is ultra-thin
  • the silicide film has better thermal stability and can withstand silicide as doping source technology (SADS) to reduce the Schottky barrier height (SBH), specifically the epitaxially grown ultrathin metal silicide source.
  • SADS silicide as doping source technology
  • SBH Schottky barrier height
  • the drain and the silicide/silicon interface of the substrate channel region form an activated separation and condensation of the doped ion region, which reduces the SBH and thus improves the driving capability of the device.
  • the high temperature second annealing of the SBH process can be repaired.
  • the silicide film caused by ion implantation is damaged.
  • an ultra-thin metal silicide film which is stably an epitaxially grown by two annealings is used, thereby improving the short-channel, epitaxial growth of the ultra-thin metal silicide source and drain by the SADS method.
  • the driving capability of the MOSFET is provided according to the MOSFET of the present invention and the method of fabricating the same.
  • FIG. 1 is a schematic cross-sectional view of a conventional metal silicide source/drain MOSFET
  • FIG. 2 is a schematic diagram of a conventional SADS technique for reducing SBH
  • FIG. 3 is a schematic cross-sectional view of a short channel metal silicide source and drain MOSFET
  • 4 to 8 are schematic cross-sectional views of devices corresponding to respective steps of an epitaxially grown ultrathin metal silicide source drain MOSFET manufacturing method in accordance with the present invention. detailed description
  • a substrate and a gate basic structure are formed.
  • a conventional semiconductor substrate may be employed, for example, a bulk silicon substrate, or other basic semiconductor or compound semiconductor such as Ge, SiGe, GaAs, InP or Si: C or the like may be included.
  • the substrate 200 includes various doping configurations, which may include an epitaxial layer, and may also include a semiconductor-on-insulator (S0I) structure. It can have stress to enhance performance.
  • an SOI substrate is preferably employed.
  • the SOI substrate 110 includes a silicon substrate 111, a buried oxide layer 112 on the silicon substrate 111, and a top silicon layer 113 on the buried oxide layer 112, wherein the thickness of the top silicon layer 113 may be 10 nm or less.
  • source-drain implantation is not performed, and metal silicide source leakage is not activated.
  • a metal layer is deposited.
  • a thin metal layer 600/610 for forming a metal silicide is deposited over the entire basic structure, covering the substrate, the gate structure, and the gate spacer.
  • the metal thin layer material may be cobalt Co, nickel Ni, nickel platinum alloy Ni-Pt (Pt content is 8% or less) or nickel-cobalt alloy Ni-Co (Co content is 10% or less), etc.
  • the thickness of the metal thin layer may be smaller than It is equal to 5 nm, preferably 4 nm or less.
  • the thin metal layer may be a Co layer having a thickness of 5 nm or less, or a Ni, Ni_Pt, Ni_Co layer having a thickness of 4 nm or less.
  • the first anneal is performed.
  • the first annealing is performed at a temperature of 500 to 85 (TC temperature) to form an epitaxially grown ultra-thin metal silicide in the source/drain region.
  • the material of the epitaxially grown ultra-thin metal silicide source drain 700/710 may be NiSi 2 - y , Ni ⁇ Pt ⁇ Si ⁇ ⁇ determined by the deposited metal thin layer 600/610 material. ( ⁇ ⁇ or ⁇ where X is greater than 0 and less than 1, and y is greater than or equal to 0 and less than 1.
  • the thickness of epitaxially grown ultrathin metal silicide source and drain 700/710 is less than or equal to 15 nm.
  • ultrathin silicide Due to the reasonable selection of metal thin layer material, thickness and First annealing temperature control, epitaxial growth
  • the resulting ultrathin silicide is very thermally stable and can withstand the subsequent high temperature annealing treatment, particularly the second annealing required to form the ion separation condensation zone.
  • doping ions are implanted into the epitaxially grown ultrathin silicide formed in the source and drain regions, as shown in FIG.
  • the doping ion can be boron 8, aluminum Al, gallium Ga, indium In, etc.
  • the doping ion can be nitrogen/phosphorus?
  • the implantation process will damage the epitaxially grown ultra-thin metal silicide source and drain, so the implantation energy should not be too large.
  • the implantation energy is preferably low enough to ensure that most of the implanted dopant ions are confined to the epitaxially grown ultrathin silicide source and a second anneal is performed. Performing a second annealing at a temperature range of 500 to 850 ° C to drive the doped ions in the epitaxially grown ultrathin metal silicide source drain 700/710 to the silicide/silicon interface to form a doped ion separation condensation zone 800/810.
  • the cross-sectional structure of the finally formed semiconductor device is as shown in FIG. 8, and includes a bulk silicon substrate 100 or an SOI substrate 110 (the SOI substrate 110 includes a silicon substrate 111, a buried oxide layer 112 on the silicon substrate 111, and a buried oxide layer).
  • the 200/210 has an isolated condensation zone 800/810 with dopant ions at the interface of the epitaxially grown ultra-thin metal silicide source drain 700/710.
  • the epitaxially grown ultra-thin metal silicide material is NiSi 2 - y , (031 2 - or 1 - 0 ⁇ -, where X is greater than 0 and less than 1, y is greater than or equal to 0 and less than 1, and the thickness is less than or equal to 15 nm.
  • ultra-thin metal silicide source-drain M0SFETs doped ions Boron B, aluminum Al, gallium Ga, indium In; for n-type epitaxial growth of ultra-thin metal silicide source-drain MOSFET, doping ions are nitrogen N, phosphorus, arsenic As, oxygen 0, sulfur 3, selenium Se, ⁇ Te, fluorine?, chlorine Cl.
  • the epitaxially grown ultra-thin metal silicide source-drain MOSFET with doped ion separation condensation region has many advantages. First, the conventional high-doped source/drain is replaced by a metal silicide source and drain, which can greatly reduce parasitic series connection.
  • the epitaxial growth formed is ultra-thin
  • the silicide film has better thermal stability and can withstand silicide as doping source technology (SADS) to reduce the Schottky barrier height (SBH), specifically the epitaxially grown ultrathin metal silicide source.
  • SADS silicide as doping source technology
  • SBH Schottky barrier height
  • the drain and the silicide/silicon interface of the substrate channel region form an activated separation and condensation of the doped ion region, which reduces the SBH and thus improves the driving capability of the device.
  • the high temperature second annealing of the SBH process can be repaired.
  • the silicide film caused by ion implantation is damaged.
  • an ultra-thin metal silicide film which is stably an epitaxially grown by two annealings is used, thereby improving the short-channel, epitaxial growth of the ultra-thin metal silicide source and drain by the SADS method.
  • the driving capability of the MOSFET is provided according to the MOSFET of the present invention and the method of fabricating the same.

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Description

半导体器件及其制造方法 技术领域
本申请涉及一种半导体器件及其制造方法， 特别地涉及一种具有 外延生长的超薄金属硅化物源 /漏的 MOSFET结构及其制造方法。 背景技术
当前 IT应用领域不断要求 IC集成度大幅提升， 随着传统 MOSFET器 件持续按比例缩小， 一些工艺上可以控制的参数例如沟道长度、 栅氧 化层厚度、 衬底掺杂浓度等等能够按比例变化， 尽管随着器件尺寸减 小， 工艺起伏影响越大， 但是， 很多物理参数例如硅禁带宽度、 费米 势、 界面态及氧化层电荷、 热电势及 pn结自建势等等不能按比例变化， 这些大大影响了按比例缩小的器件的性能。
其中之一便是源漏串联电阻。 沟道较长时， 沟道电阻远大于源漏 区串联电阻， 可以忽略寄生串联电阻带来的影响。 然而源漏电阻不随 沟道尺寸缩小而按比例降低， 特别是接触电阻随着尺寸减小而近似平 方倍增加， 使等效工作电压下降。 如果在现有 MOSFET制造技术中将传 统的高掺杂源 /漏替换为金属硅化物源漏， 可以大幅减小寄生串联电阻 以及接触电阻。
如附图 1所示， 为现有的金属硅化物源 /漏 MOSFET (也被称为肖特 基势垒源 /漏 MOSFET) 示意图， 在体硅衬底 10或绝缘体上硅 （S0I ) 衬 底 11中的沟道区 20或 21两侧形成金属硅化物源漏区 30和 31， 沟道区上 依次形成有栅极结构 40/41以及栅极侧墙 50/51， 其中金属硅化物被完 全作为直接接触沟道的源 /漏极材料。器件衬底中还可以设置浅沟槽隔 离 STI 60/61, 图中 STI并非直接介于体硅衬底和 S0I衬底之间， 而仅仅 是为了方便示例起见， 两种衬底不相连。
这种金属硅化物源漏 MOSFET具有极佳的可按比例缩小特性且易于 制造， 因此吸引了广泛关注而成为当前 MOSFET技术发展热点之一。
金属硅化物源漏 MOSFET的驱动能力是由其源极和沟道之间的肖特 基势垒高度 （SBH) 来控制的。 随着 SBH降低， 驱动电流增大。 器件模 拟的结果显示， 当 SBH降低至约 0. leV时， 金属硅化物源 /漏 MOSFET可达 到与传统 MOSFET相同的驱动能力。
如附图 2所示， 为使用硅化物作掺杂源极技术 （SADS) 以降低 SBH 的方法示意图。首先，将硼 B、砷 As等离子注入硅化物薄膜 31中； 接着， 在 500至 850 'C温度下执行退火以使得掺杂离子分离凝结在硅化物 /硅 界面处， 形成激活的分离凝结的掺杂离子区 71。 该分离凝结的掺杂离 子 71降低了源极和沟道之间的 SBH， 因此而改进了器件的驱动能力； 同 时， 离子注入带来的硅化物薄膜受损也由于退火而得到修复。
随着金属硅化物源 /漏 MOSFET尺寸缩减至亚 20nm栅极长度，金属硅 化物源漏的厚度也需要缩减以便控制短沟道效应 （SCEs ) ， 特别是对 于那些形成在 S0I衬底上的器件而言。
如图 1所示为缩减尺寸前的金属硅化物源漏 MOSFET, 沟道区 20/21 较长， 金属硅化物源漏薄膜 30/31较厚， 在退火时其热稳定性比较好。 但是， 随着金属硅化物源漏厚度变薄， 其热稳定性也会变差。 如图 3所 示， 尺寸缩减后， 沟道 20/21变短， 金属硅化物源漏薄膜 30/31必须也 相应变薄以便较好地控制短沟道效应， 但是变薄的硅化物薄膜 30/31在 退火时热稳定性较差， 容易聚团， 导致电阻率急剧增大。 由于在前述 降低 SBH的 SADS方法中，硅化物薄膜无法承受为了将掺杂离子分离凝结 在硅化物 /硅界面处而所需的高温退火， 因此， 对于金属硅化物源漏 MOSFET而言， 无法降低 SBH。
总而言之， 金属硅化物源漏 MOSFET被视为亚 20nm下一代 CMOS的结 构，而现有的为了降低源极和沟道区之间 SBH以提高驱动能力的 SADS方 法， 在沟道缩短、 金属硅化物薄膜减薄时因为无法承受高温退火而不 能实施。
因此， 需要一种能有效降低金属硅化物源漏 MOSFET的 SBH的方法， 以及由此制造的具有热稳定性的金属硅化物源漏 M0SFET。 发明内容
为了解决上述问题， 本发明提供了一种半导体器件， 包括衬底、 位于衬底中的沟道区、 位于沟道区两侧的源漏区、 位于沟道区上的栅 极结构、 位于栅极结构周围的栅极侧墙， 其特征在于： 源漏区由外延 生长的超薄金属硅化物构成， 源漏区与沟道区的界面处具有掺杂离子 的分离凝结区。
其中， 外延生长的超薄金属硅化物材质为 NiSi2-y、 Ni^Pt^Si^, 。(^^^或 ^^^^，其中 X大于 0小于 1， y大于等于 0小于 1。外延生长 的超薄金属硅化物厚度小于等于 15nm。对于 p型外延生长的超薄金属硅 化物源漏 MOSFET而言， 掺杂离子为硼 B、 铝 Al、 镓 Ga、 铟 In; 对于 n型 外延生长的超薄金属硅化物源漏 M0SFET, 掺杂离子为氮 N、 磷？、 砷 As、 氧 0、 硫3、 硒 Se、 碲 Te、 氟？、 氯 Cl。 衬底可为体硅或绝缘体上半导体 衬底。
本发明还提供了一种半导体器件的制造方法， 包括：
在衬底上形成栅极结构和栅极侧墙；
沉积覆盖衬底、 栅极结构和栅极侧墙的金属层；
执行第一退火， 以使栅极两侧的金属层与衬底反应形成外延生长 的超薄金属硅化物；
剥除未反应的金属层， 则外延生长的超薄金属硅化物形成器件的 源漏区， 位于栅极结构下方的半导体衬底形成沟道区；
向外延生长的超薄源漏区内注入掺杂离子； 以及
执行第二退火， 在外延生长的超薄源漏区与沟道区的界面处形成 掺杂离子的分离凝结区。
其中， 外延生长的超薄金属硅化物材质为 NiSi2-y、 Ni^Pt^Si^, 。(^ ^或 ^^^ 其中 X大于 0小于 1， y大于等于 0小于 1。
对于 P型外延生长的超薄金属硅化物源漏 MOSFET而言， 掺杂离子为 硼^ 铝 Al、 镓 Ga、 铟 In; 对于 n型外延生长的超薄金属硅化物源漏 MOSFET, 掺杂离子为氮 N、 磷？、 砷 As、 氧 0、 硫3、 硒 Se、 碲 Te、 氟？、 氯 Cl。 注入掺杂离子的注入剂量为 l X 1014cm— 2至 l X 1016cm— 2。
其中， 第一退火和 /或第二退火的温度为 500至 850'C。
其中金属层的厚度小于等于 5nm。
其中， 衬底可为体硅或绝缘体上半导体衬底。
这种具有掺杂离子分离凝结区的外延生长的超薄金属硅化物源漏 MOSFET具有诸多优点， 首先是将传统的高掺杂源 /漏替换为金属硅化物 源漏，可以大幅减小寄生串联电阻以及接触电阻，从而可以抑制亚 20nm 器件中对于器件电学性能有重大影响的短沟道效应， 将等效工作电压 保持在需要的水平上； 其次， 由于较好控制了金属硅化物前驱物一也 即沉积的金属层的厚度以及处理工艺特别是第一退火的时间和温度范 围，使得形成的外延生长的超薄硅化物薄膜具有较佳的热稳定性，可以 经受硅化物作掺杂源极技术 （SADS) 以降低肖特基势垒高度 （SBH) ， 具体而言就是在外延生长的超薄金属硅化物源漏和衬底沟道区的硅化 物 /硅界面处， 形成激活的分离凝结的掺杂离子区， 降低了 SBH因此而 提高了器件的驱动能力； 再次， 降低 SBH过程的高温第二退火可以修复 离子注入带来的硅化物薄膜损伤。 总之， 依照本发明的 MOSFET及其制造 方法， 采用了两次退火得到稳定的外延生长的超薄金属硅化物薄膜， 从 而可以采用 SADS方法提高短沟道、 外延生长的超薄金属硅化物源漏 MOSFET的驱动能力。
本发明所述目的， 以及在此未列出的其他目的， 在本申请独立权 利要求的范围内得以满足。 本发明的实施例限定在独立权利要求中， 具体特征限定在其从属权利要求中。 附图说明
以下结合附图来详细说明本发明技术方案， 其中：
图 1为现有的金属硅化物源 /漏 MOSFET剖面示意图；
图 2为现有的 SADS技术以降低 SBH的方法示意图；
图 3为短沟道金属硅化物源漏 MOSFET剖面示意图； 以及
图 4至图 8为依照本发明的外延生长的超薄金属硅化物源漏 MOSFET 制造方法的各个步骤对应的器件剖面示意图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了具有热稳定性外延生长的超薄金属硅化 物源漏的 MOSFET及其制造方法。 需要指出的是， 类似的附图标记表示 类似的结构， 本申请中所用的术语 "第一"、 "第二"、 "上"、 "下" 等等可用于修饰各种器件结构。 这些修饰除非特别说明并非暗示所修 饰器件结构的空间、 次序或层级关系。
图 4至图 8为依照本发明的外延生长的超薄金属硅化物源漏 MOSFET 制造方法的各个步骤对应的器件剖面示意图。各图中 STI并非直接介于 体硅衬底和 S0I衬底之间， 而仅仅是为了方便示例起见， 两种衬底不相 连。
首先， 如附图 4所示， 形成衬底和栅极基本结构。 对于本发明的实 施例， 可以采用常规的半导体衬底， 例如， 可以包括体硅衬底， 或其 他基本半导体或化合物半导体， 例如 Ge、 SiGe、 GaAs、 InP或 Si : C等。 根据现有技术公知的设计要求 （例如 P型衬底或者 n型衬底） ， 所述衬 底 200包括各种掺杂配置， 可以包括外延层， 也可以包括绝缘体上半导 体 （S0I ) 结构， 还可以具有应力以增强性能。 对于本发明的实施例， 优选采用 S0I衬底。 具体地， 在体硅衬底 100或绝缘体上硅（S0I )衬底 110中的沟道区 200或 210上， 形成栅极结构 300或 310， 在栅极结构周围 形成有栅极侧墙 400或 410， 器件衬底中还可以设置浅沟槽隔离 STI 500/510。其中，沟道区 200/210长度小于等于 20nm，也即器件为亚 20nm 的短沟道 M0SFET。 特别地， S0I衬底 110包括硅衬底 111、 硅衬底 111上 的埋氧层 112以及埋氧层 112上的顶硅层 113， 其中顶硅层 113的厚度可 小于等于 10nm。 在形成基本结构的步骤中， 不执行源漏注入， 也不激 活金属硅化物源漏。
其次， 沉积金属层。 如图 5所示， 在整个基本结构上沉积用于形成 金属硅化物的金属薄层 600/610， 覆盖衬底、 栅极结构以及栅极侧墙。 金属薄层材质可以为钴 Co、 镍 Ni、 镍铂合金 Ni-Pt (Pt含量小于等于 8 % )或镍钴合金 Ni-Co (Co含量小于等于 10% )等等， 金属薄层厚度可 小于等于 5nm， 优选地小于等于 4nm。 具体地， 金属薄层可为厚度小于 等于 5nm的 Co层， 或是厚度小于等于 4nm的 Ni、 Ni_Pt、 Ni_Co层。
再次， 执行第一退火。 在 500至 85(TC温度下执行第一退火， 在源 漏区域内形成外延生长的超薄金属硅化物。
接着， 剥除未反应的金属薄层， 如图 6所示， 得到外延生长的超薄 金属硅化物源漏 700/710。 由前述沉积的金属薄层 600/610材质决定， 外延生长的超薄金属硅化物源漏 700/710的材质可为 NiSi2-y、 Ni^Pt^Si^^ 。(^ ^或 ^^^ 其中 X大于 0小于 1， y大于等于 0小 于 1。 外延生长的超薄金属硅化物源漏 700/710的厚度小于等于 15nm。 由于合理选择金属薄层材质、 厚度以及第一退火温度的控制， 外延生 长得到的超薄硅化物是具有很好的热稳定性的， 能够经受后期的高温 退火处理， 特别是形成掺杂离子分离凝结区所需的第二退火。
然后， 向在源漏区形成的外延生长的超薄硅化物内注入掺杂离子， 如图 7所示。 向外延生长的超薄金属硅化物源漏 700/710注入掺杂离子， 剂量为 1 X 1014cm— 2至 1 X 1016cm— 2，对于 p型外延生长的超薄金属硅化物源 漏 M0SFET, 掺杂离子可为硼8、 铝 Al、 镓 Ga、 铟 In等等， 对于 n型外延 生长的超薄金属硅化物源漏 M0SFET, 掺杂离子可为氮^ 磷？、 砷 As、 氧 0、 硫3、 硒 Se、 碲 Te、 氟？、 氯 C1等等。 注入过程会损伤外延生长的 超薄金属硅化物源漏， 因此注入能量不宜过大。 注入能量最好是足够 低， 以确保大部分注入的掺杂离子被限定在外延生长的超薄硅化物源 最后， 执行第二退火。 在 500至 850°C温度范围下执行第二退火， 将外延生长的超薄金属硅化物源漏 700/710中的掺杂离子驱赶至硅化 物 /硅界面处， 形成掺杂离子的分离凝结区 800/810。
最后形成的半导体器件的剖面结构如附图 8所示， 包括体硅衬底 100或 S0I衬底 110 (S0I衬底 110包括硅衬底 111、硅衬底 111上的埋氧层 112以及埋氧层 112上的顶硅层 113， 其中顶硅层 113的厚度可小于等于 lOnm) ， 沟道区 200/210位于衬底 100/110中， 外延生长的超薄金属硅 化物源漏区 700/710位于沟道区两侧， 栅极结构 300/310位于沟道区上 方， 栅极侧墙 400/410位于栅极结构周围， 衬底 100/110中还可以具有 STI 500/510 , 在沟道区 200/210与外延生长的超薄金属硅化物源漏 700/710的界面处具有掺杂离子的分离凝结区 800/810。 其中， 外延生 长的超薄金属硅化物材质为 NiSi2-y、
Figure imgf000008_0001
( 0312-或 1- 0^ -， 其中 X大于 0小于 1， y大于等于 0小于 1， 厚度小于等于 15nm。 对于 p型外 延生长的超薄金属硅化物源漏 M0SFET而言， 掺杂离子为硼 B、 铝 Al、 镓 Ga、 铟 In; 对于 n型外延生长的超薄金属硅化物源漏 M0SFET, 掺杂离子 为氮 N、 磷？、 砷 As、 氧 0、 硫3、 硒 Se、 碲 Te、 氟？、 氯 Cl。
这种具有掺杂离子分离凝结区的外延生长的超薄金属硅化物源漏 M0SFET具有诸多优点， 首先是将传统的高掺杂源 /漏替换为金属硅化物 源漏，可以大幅减小寄生串联电阻以及接触电阻，从而可以抑制亚 20nm 器件中对于器件电学性能有重大影响的短沟道效应， 将等效工作电压 保持在需要的水平上； 其次， 由于较好控制了金属硅化物前驱物一也 即沉积的金属层的厚度以及处理工艺特别是第一退火的时间和温度范 围，使得形成的外延生长的超薄硅化物薄膜具有较佳的热稳定性，可以 经受硅化物作掺杂源极技术 （SADS) 以降低肖特基势垒高度 （SBH) ， 具体而言就是在外延生长的超薄金属硅化物源漏和衬底沟道区的硅化 物 /硅界面处， 形成激活的分离凝结的掺杂离子区， 降低了 SBH因此而 提高了器件的驱动能力； 再次， 降低 SBH过程的高温第二退火可以修复 离子注入带来的硅化物薄膜损伤。 总之， 依照本发明的 MOSFET及其制造 方法， 采用了两次退火得到稳定的外延生长的超薄金属硅化物薄膜， 从 而可以采用 SADS方法提高短沟道、 外延生长的超薄金属硅化物源漏 MOSFET的驱动能力。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1.一种半导体器件， 包括衬底、 位于所述衬底中的沟道区、 位于 所述沟道区两侧的源漏区、 位于所述沟道区上的栅极结构、 位于所述 栅极结构周围的栅极侧墙， 其特征在于：
所述源漏区由外延生长的金属硅化物构成， 所述源漏区与所述沟 道区的界面处具有掺杂离子的分离凝结区。
2.如权利要求 1所述的半导体器件， 其特征在于， 所述外延生长的 金属硅化物材质为 NiSi2—y、 NU Si2—y、 CoSi2-^NH Si2-y， 其中 x 大于 0小于 1， y大于等于 0小于 1。
3. 如权利要求 1所述的半导体器件， 其特征在于， 所述外延生长 的金属硅化物厚度小于等于 15nm。
4. 如权利要求 1所述的半导体器件， 其特征在于， 对于 p型金属硅 化物源漏 MOSFET而言， 所述掺杂离子为硼 B、 铝 Al、 镓 Ga、 铟 In; 对于 n型金属硅化物源漏 M0SFET, 所述掺杂离子为氮 N、 磷？、 砷 As、 氧 0、 硫3、 硒 Se、 碲 Te、 氟？、 氯 Cl。
5. 如权利要求 1所述的半导体器件， 其特征在于， 所述衬底为体 硅或绝缘体上半导体衬底。
6. 一种半导体器件的制造方法， 包括：
在衬底上形成栅极结构和栅极侧墙；
沉积覆盖所述衬底、 所述栅极结构和所述栅极侧墙的金属层； 执行第一退火， 以使所述栅极两侧的金属层与衬底反应形成外延 生长的金属硅化物；
剥除未反应的所述金属层， 则所述外延生长的金属硅化物形成所 述器件的源漏区， 位于所述栅极结构下方的半导体衬底形成沟道区； 向所述外延生长的源漏区内注入掺杂离子； 以及
执行第二退火， 在所述外延生长的源漏区与所述沟道区的界面处 形成掺杂离子的分离凝结区。
7. 如权利要求 6所述的半导体器件的制造方法， 其中， 所述外延 生长的金属硅化物材质为 NiSi2-y、
Figure imgf000010_0001
( 0312-或 1- 0^12-" 其中 X大于 0小于 1， y大于等于 0小于 1。
8. 如权利要求 6所述的半导体器件的制造方法， 其中， 对于 p型金 属硅化物源漏 MOSFET而言， 所述掺杂离子为硼 B、 铝 Al、 镓 Ga、 铟 In; 对于 n型金属硅化物源漏 MOSFET, 所述掺杂离子为氮 N、 磷？、 砷 As、 氧 0、 硫3、 硒 Se、 碲 Te、 氟？、 氯 Cl。
9. 如权利要求 6所述的半导体器件的制造方法， 其中， 所述第一 退火和 /或所述第二退火的温度为 500至 850°C。
10. 如权利要求 6所述的半导体器件的制造方法， 其中注入掺杂离 子的注入剂量为 l X 1014cm— 2至 l X 1016cm— 2。
11. 如权利要求 6所述的半导体器件的制造方法， 其中所述金属层 的厚度小于等于 5nm。
12.如权利要求 6至 11之一所述的半导体器件的制造方法， 其中， 所述衬底为体硅或绝缘体上半导体衬底。
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