JP2013545289A - SiGeチャネルを有するpFET接合プロフィールのための方法および構造体 - Google Patents
SiGeチャネルを有するpFET接合プロフィールのための方法および構造体 Download PDFInfo
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 104
- 238000000034 method Methods 0.000 title claims description 63
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- 208000032750 Device leakage Diseases 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
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- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
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- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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Abstract
【解決手段】本開示では、Si基板12の上部に配置されたSiGeチャネル層14の直接真下に、NまたはCドープSi層16を形成することによって、pFETデバイスに対する階段ソース/ドレイン接合が設けられる。しかして、(SiGeチャネル層とSi基板との間に挟まれた)NまたはCドープSi層16が、p型ドーパントに対して上層のSiGeチャネル層とほぼ同じ拡散速度を有する、構造体が提供される。NまたはCドープSi層と上層のSiGeチャネル層14とがp型ドーパントに対しほぼ同じ拡散率を有し、NまたはCドープSi層16が、下層のSi基板中へのp型ドーパントの拡散を遅延させるので、階段ソース/ドレイン接合を形成することが可能になる。
【選択図】図4
Description
Claims (25)
- 半導体構造体を作製する方法であって、
Si基板12と、前記Si基板の上部表面上に配置されたNまたはCドープSi層16と、前記NまたはCドープSi層の上部表面上に配置されたSiGeチャネル層14とを包含する構造体を設けるステップと、
前記SiGeチャネル層の上部表面上にpFETゲート・スタック18を形成するステップと、
p型ドーパントのイオン注入によって、前記SiGeチャネル層の一部内、前記NまたはCドープSi層の一部内、および前記pFETゲート・スタックのフットプリントに、ソース領域およびドレイン領域26を形成するステップであって、前記ソース領域および前記ドレイン領域は階段接合プロフィールを有する、前記形成するステップと、
を含む方法。 - 前記構造体を前記設けるステップは、前記Si基板の上部表面上に前記SiGe層を形成し、次いで前記Si基板の前記上部領域16’中にNまたはCを注入することによって、前記Si基板12の上部部分内に前記NまたはCドープ層を形成するステップを含む、請求項1に記載の方法。
- 前記Si基板の前記上部表面上に前記SiGe層を前記形成するステップは、エピタキシャル成長プロセスを含み、前記SiGe層は応力歪を有する、請求項2に記載の方法。
- 前記NまたはCの注入は、1E12atoms/cm2〜5E15atoms/cm2のイオン・ドーズを用いて、2keV〜10keVの範囲のエネルギで行われる、請求項2に記載の方法。
- 前記構造体を前記設けるステップは、前記Si基板の上部表面上に前記NまたはCドープSi層を形成するステップと、次いで前記NまたはCドープSi層の上部表面上に前記SiGeチャネル層14を形成するステップとを含む、請求項1に記載の方法。
- 前記NまたはCドープSi層を前記形成するステップおよび前記SiGeチャネル層を形成するステップの両方が、エピタキシャル成長プロセスを含む、請求項5に記載の方法。
- 前記NまたはCドープSi層を形成するステップおよび前記SiGeチャネル層を形成するステップの間真空が維持されている、請求項6に記載の方法。
- 前記構造体を前記設けるステップは、前記Si基板の上部領域内に前記NまたはCドープSi層を形成するステップと、次いで前記NまたはCドープSi層16の上部表面上に前記SiGeチャネル層を形成するステップとを含む、請求項1に記載の方法。
- 前記NまたはCドープSi層を前記形成するステップは、前記Si基板の前記上部領域中にNまたはCをイオン注入するステップを含む、請求項8に記載の方法。
- NまたはCを前記注入するステップは、1E12atoms/cm2〜5E15atoms/cm2のイオン・ドーズを用いて、2keV〜10keVの範囲のエネルギで実施される、請求項9に記載の方法。
- 前記SiGeチャネル層を形成するステップは、エピタキシャル成長プロセスを含む、請求項8に記載の方法。
- 半導体構造体を形成する方法であって、
Si基板12の表面上に配置されたSiGeチャネル層14を包含する構造体を設けるステップと、
前記SiGeチャネル層の一部分上にpFETゲート・スタックを形成するステップと、
NまたはCを、ハロー・イオンと共に共注入し、前記Si基板の上部領域と、前記pFETゲート・スタックのフットプリントとにNまたはCドープSi層16’を形成する、ハロー・イオン注入処理を実施するステップと、
p型ドーパントのイオン注入によって、前記SiGe層チャネル14の一部内、前記NまたはCドープSi層16’の一部内、および前記pFETゲート・スタックのフットプリントに、ソース領域およびドレイン領域26を形成するステップであって、前記ソース領域および前記ドレイン領域26は階段接合プロフィールを有する、前記形成するステップと、
を含む方法。 - 前記構造体を前記設けるステップは、前記Si基板の前記表面上に前記SiGeチャネル層をエピタキシャルに成長させるステップを含む、請求項12に記載の方法。
- 前記ハロー・イオン注入は、前記Si基板の垂直方向から15°〜45°の角度で行われる、請求項12に記載の方法。
- 前記ハロー・イオン注入は、5keV〜30keVのエネルギで行われる、請求項12に記載の方法。
- 前記ハロー・イオン注入は、1E12atoms/cm2〜5E15atoms/cm2のNまたはCのドーズ、および5E12atoms/cm2〜1E14atoms/cm2のハロー・イオンのドーズを含む、請求項12に記載の方法。
- Si基板12と、前記Si基板の上部表面上に配置されたNまたはCドープSi層と、前記NまたはCドープSi層の上部表面上に配置されたSiGeチャネル層14と、前記SiGeチャネル層の上部表面上に配置されたpFETゲート・スタックと、ソース領域およびドレイン領域26であって、前記SiGeチャネル層の一部分内、前記NまたはCドープSi層の一部分内、および前記pFETゲート・スタックのフットプリントにそれぞれ配置され、階段接合をそれぞれ含む、前記ソース領域およびドレイン領域と、を含む半導体構造体。
- 前記NまたはCドープSi層は、エピタキシャルNまたはCドープSi層である、請求項17に記載の半導体構造体。
- 前記SiGeチャネル層はエピタキシャルSiGeチャネル層である、請求項17に記載の半導体構造体。
- 前記SiGeチャネル層は応力歪を有する、請求項17に記載の半導体構造体。
- 前記NまたはCドープSi層はSi:Nを含む、請求項17に記載の半導体構造体。
- 前記NまたはCドープSi層はSi:Cを含む、請求項17に記載の半導体構造体。
- 前記NまたはCドープSi層が、前記SiGeチャネル層の真下に連続して所在する、請求項17に記載の半導体構造体。
- 前記NまたはCドープSi層が、前記SiGe層の真下に部分的に所在する、請求項17に記載の半導体構造体。
- 前記ゲート・スタックは、ゲート導体層22と積層されたゲート誘電体層20から成る、請求項17に記載の半導体構造体。
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US8659054B2 (en) | 2014-02-25 |
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