JP2009283496A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
【解決手段】本発明の一態様に係る半導体装置は、素子分離領域2により分離された第1および第2のトランジスタ領域10、20を有する半導体基板1と、第1および第2のトランジスタ領域10、20において、半導体基板上1に形成された不純物拡散抑制層12、22と、不純物拡散抑制層12、22上に形成されたエピタキシャル結晶層13、23と、を有し、不純物拡散抑制層22の厚さは、不純物拡散抑制層12の厚さよりも厚く、チャネル領域11に含まれる導電型不純物は、エピタキシャル結晶層13中の領域における濃度が、半導体基板1中の領域における濃度よりも低く、チャネル領域21に含まれる導電型不純物は、エピタキシャル結晶層23中の領域における濃度が、半導体基板1中の領域における濃度よりも低い。
【選択図】図1
Description
Hong-Jyh Li et al., "Mat. Res. Soc. Symp. Proc.", vol. 737, p. 643, 2003. F. Ducroquet et al., "2004 IEDM Technical Digest.", p. 437.
(半導体装置の構成)
図1は、本発明の第1の実施の形態に係る半導体装置の断面図である。
図4A(a)〜(c)、図4B(d)〜(e)は、本発明の第1の実施の形態に係る半導体装置の製造工程を示す断面図である。
本発明の第1の実施の形態によれば、不純物拡散抑制層12、22を異なる厚さに形成することにより、第1および第2のトランジスタ領域10、20におけるそれぞれのトランジスタの閾値電圧を各々に適切な値に設定することができる。
本発明の第2の実施の形態は、半導体装置の一部の製造工程が第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略または簡略化する。
図5(a)〜(c)は、本発明の第2の実施の形態に係る半導体装置の製造工程を示す断面図である。
本発明の第2の実施の形態によれば、第1の実施の形態と異なる方法により不純物拡散抑制層12、22を異なる厚さに形成することができる。
本発明の第3の実施の形態は、一方のトランジスタ領域にのみ不純物拡散抑制層が形成される点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、説明を省略または簡略化する。
図6は、本発明の第3の実施の形態に係る半導体装置の断面図である。また、図7(a)、(b)は、それぞれ第1および第2のトランジスタ領域におけるチャネル領域周辺の部分断面図である。なお、図7(a)、(b)においては、ゲート絶縁膜14、24、ゲート電極15、25およびゲート側壁16、26の図示を省略する。
図8(a)〜(c)は、本発明の第3の実施の形態に係る半導体装置の製造工程を示す断面図である。
本発明の第3の実施の形態によれば、第1のトランジスタ領域10に不純物拡散抑制層を形成せず、第2のトランジスタ領域20に不純物拡散抑制層21を形成することにより、バイアス電圧を印加した場合に閾値電圧を大きく変化させるトランジスタと、ほとんど変化させないトランジスタを同一基板上に形成することができる。
本発明の第4の実施の形態は、不純物拡散抑制層が形成されるトランジスタのゲート電極が金属層を有する点において第3の実施の形態と異なる。なお、第3の実施の形態と同様の点については、説明を省略または簡略化する。
図9は、本発明の第4の実施の形態に係る半導体装置の断面図である。
本発明の第4の実施の形態によれば、高誘電材料からなるゲート絶縁膜24と金属層25aを含むゲート電極25が形成され、フェルミレベル・ピニング等の閾値電圧の低下を困難にする現象が発生する第2のトランジスタ領域20と、閾値電圧の調整が比較的容易である第1のトランジスタ領域10が同一基板上に形成される場合であっても、第2のトランジスタ領域20に不純物拡散抑制層22を形成することにより、電荷の移動度を低下させることなく、各トランジスタの閾値電圧を低い好ましい値に設定することができる。
本発明は、上記各実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。
Claims (5)
- 素子分離領域により分離された第1および第2のトランジスタ領域を有する半導体基板と、
前記第1のトランジスタ領域において、前記半導体基板上に形成された第1の不純物拡散抑制層と、
前記第2のトランジスタ領域において、前記半導体基板上に形成され、前記第1の不純物拡散抑制層よりも厚さの厚い第2の不純物拡散抑制層と、
前記第1の不純物拡散抑制層上に形成された第1の結晶層と、
前記第2の不純物拡散抑制層上に形成された第2の結晶層と、
前記第1の結晶層上に第1のゲート絶縁膜を介して形成された第1のゲート電極と、
前記第2の結晶層上に第2のゲート絶縁膜を介して形成された第2のゲート電極と、
前記第1のトランジスタ領域において、前記半導体基板、前記第1の不純物拡散抑制層および前記第1の結晶層中の前記第1のゲート電極下の領域に形成され、第1の導電型不純物を含む第1のチャネル領域と、
前記第2のトランジスタ領域において、前記半導体基板、前記第2の不純物拡散抑制層および前記第2の結晶層中の前記第2のゲート電極下の領域に形成され、第2の導電型不純物を含む第2のチャネル領域と、
前記第1のチャネル領域の両側に形成された第1のソース・ドレイン領域と、
前記第2のチャネル領域の両側に形成された第2のソース・ドレイン領域と、
を有し、
前記第1の導電型不純物は、前記第1のチャネル領域の前記第1の結晶層中の領域における濃度が、前記第1のチャネル領域の前記半導体基板中の領域における濃度よりも低く、
前記第2の導電型不純物は、前記第2のチャネル領域の前記第2の結晶層中の領域における濃度が、前記第2のチャネル領域の前記半導体基板中の領域における濃度よりも低い、
ことを特徴とする半導体装置。 - 前記第1および第2の導電型不純物はBであり、
前記第1および第2の不純物拡散抑制層はSi:C、SiGe、またはSiGe:Cである、
ことを特徴とする請求項1に記載の半導体装置。 - 素子分離領域により分離された第1および第2のトランジスタ領域を有する半導体基板と、
前記第1のトランジスタ領域において、前記半導体基板上に第1のゲート絶縁膜を介して形成された第1のゲート電極と、
前記第2のトランジスタ領域において、前記半導体基板上に形成された不純物拡散抑制層と、
前記不純物拡散抑制層上に形成された結晶層と、
前記結晶層上に第2のゲート絶縁膜を介して形成された第2のゲート電極と、
前記第1のトランジスタ領域において、前記半導体基板中の前記第1のゲート電極下の領域に形成され、第1の導電型不純物を含む第1のチャネル領域と、
前記第2のトランジスタ領域において、前記半導体基板、前記不純物拡散抑制層および前記結晶層中の前記第2のゲート電極下の領域に形成され、第2の導電型不純物を含む第2のチャネル領域と、
前記第1のチャネル領域の両側に形成された第1のソース・ドレイン領域と、
前記第2のチャネル領域の両側に形成された第2のソース・ドレイン領域と、
を有し、
前記第2の導電型不純物は、前記第2のチャネル領域の前記結晶層中の領域における濃度が、前記第2のチャネル領域の前記半導体基板中の領域における濃度よりも低く、
前記第2のチャネル領域の前記半導体基板中の領域における前記第2の導電型不純物は、前記第1のチャネル領域の前記第1の導電型不純物よりも高い濃度を有する、
ことを特徴とする半導体装置。 - 前記第2のゲート絶縁膜は高誘電膜からなり、
前記第2のゲート電極は金属または金属化合物からなる層を含み、
前記第1のゲート電極はSi系多結晶からなる、
ことを特徴とする請求項3に記載の半導体装置。 - 前記第2の導電型不純物はBであり、
前記第2の不純物拡散抑制層はSi:C、SiGe、またはSiGe:Cである、
ことを特徴とする請求項3または4に記載の半導体装置。
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