CN113224158A - 半导体晶体管及其制作方法 - Google Patents

半导体晶体管及其制作方法 Download PDF

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CN113224158A
CN113224158A CN202010079601.1A CN202010079601A CN113224158A CN 113224158 A CN113224158 A CN 113224158A CN 202010079601 A CN202010079601 A CN 202010079601A CN 113224158 A CN113224158 A CN 113224158A
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channel layer
epitaxial channel
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刘昇旭
黄世贤
谈文毅
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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Abstract

本发明公开一种半导体晶体管及其制作方法，其中该半导体晶体管包含一基底，具有第一导电型，其中所述基底具有一主表面；一离子阱，具有一第二导电型，位于所述基底中；彼此相区隔的一源极区和一漏极区，设于所述离子阱中，其中所述源极区和所述漏极区具有所述第一导电型；一外延通道层，具有所述第一导电型，从所述基底的所述主表面长出，并且位于所述源极区和所述漏极区之间；一栅极，设于所述外延通道层上；以及一栅极介电层，位于所述栅极和所述外延通道层之间。

Description

半导体晶体管及其制作方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种改良的半导体晶体管及其制作方法。
背景技术
已知，MOSFET元件的结构主要包含形成在硅基底表面上的源极区和漏极区、形成在栅极之间的栅极氧化层，和形成在栅极氧化层上的栅极。在源极区和漏极区之间的硅基底的表面区域被定义为通道区。通道区的长度是源极区和漏极区之间的距离，通常比栅极长度短一些。
为了提高MOSFET元件的速度，元件的结构已被缩小到更小的尺寸。微缩元件尺寸的方法之一是缩减栅极长度。然而，栅极长度缩减而发生的最明显的影响之一是栅极控制力的损失，其有时被称为阈值滚降(VT roll-off)。MOSFET元件的阈值电压VT被定义为跨栅极和源极施加的栅极-源极电压Vgs，低于该电压，MOSFET元件的漏极-源极电流Ids接近零。
在现有技术中，通常是在沉积多晶硅栅极之前，利用阈值调整离子注入(VTadjust implant)制作工艺进行硅-栅极氧化层界面处的通道掺杂，以调整晶体管的阈值分布。然而，以上述阈值调整离子注入制作工艺注入的掺质由于扩散，会在接近硅基底表面处形成高斯分布(Gauss function distribution)，难以达到均一的掺质浓度分布。因此，现有技术无法有效的控制因元件漏电引起的元件最小电压(Vmin)不稳定现象。
发明内容
本发明主要目的在于提供一种改良的半导体晶体管及其制作方法，能够解决上述现有技术的不足与缺点。
本发明一方面提供一种半导体晶体管，包含一基底，具有第一导电型，其中所述基底具有一主表面；一离子阱，具有一第二导电型，位于所述基底中；彼此相区隔的一源极区和一漏极区，设于所述离子阱中，其中所述源极区和所述漏极区具有所述第一导电型；一外延通道层，具有所述第一导电型，从所述基底的所述主表面长出，并且位于所述源极区和所述漏极区之间；一栅极，设于所述外延通道层上；以及一栅极介电层，位于所述栅极和所述外延通道层之间。
依据本发明实施例，所述半导体晶体管另包含：一浅沟绝缘区，隔离一主动(有源)区域，其中所述离子阱、所述源极区和所述漏极区位于所述主动区域内。
依据本发明实施例，所述浅沟绝缘区包含一沟槽填充层，其中所述沟槽填充层的一上部突出于所述基底的所述主表面。
依据本发明实施例，所述外延通道层具有一边缘刻面，邻近所述沟槽填充层的所述上部。
依据本发明实施例，所述边缘刻面与所述沟槽填充层的所述上部的侧壁之间的夹角介于0°～45°。
依据本发明实施例，所述第一导电类型为P型，所述第二导电类型为N型。
依据本发明实施例，所述外延通道层包含P型掺杂硅或P型掺杂硅化锗。
依据本发明实施例，所述外延通道层的P型掺质的浓度介于
Figure BDA0002379794360000021
Figure BDA0002379794360000022
依据本发明实施例，所述P型掺杂硅化锗的锗浓度介于25at.％～50at.％。
依据本发明实施例，所述外延通道层的厚度介于5nm至50nm。
本发明另一方面提供一种形成半导体晶体管的方法，包含：提供一第一导电型的基底，其中所述基底具有一主表面；在所述基底中形成一第二导电型的离子阱；从所述基底的所述主表面长出一第一导电型的外延通道层；在所述外延通道层上形成一栅极介电层；在所述栅极介电层上形成一栅极；以及在所述基底中形成一第一导电型的源极区和一第一导电型的漏极区。
依据本发明实施例，所述方法另包含：在所述基底中形成一浅沟绝缘区，隔离一主动区域，其中所述离子阱、所述源极区和所述漏极区位于所述主动区域内。
依据本发明实施例，所述浅沟绝缘区包含一沟槽填充层，其中所述沟槽填充层的一上部突出于所述基底的所述主表面。
依据本发明实施例，所述外延通道层具有一边缘刻面，邻近所述沟槽填充层的所述上部。
依据本发明实施例，所述边缘刻面与所述沟槽填充层的所述上部的侧壁之间的夹角介于0°～45°。
依据本发明实施例，所述第一导电类型为P型，所述第二导电类型为N型。
依据本发明实施例，所述外延通道层包含P型掺杂硅或P型掺杂硅化锗。
依据本发明实施例，所述外延通道层的P型掺质的浓度介于
Figure BDA0002379794360000031
Figure BDA0002379794360000032
依据本发明实施例，所述P型掺杂硅化锗的锗浓度介于25at.％～50at.％。
依据本发明实施例，所述外延通道层的厚度介于5nm至50nm。
附图说明
图1至图9为依据本发明实施例所绘示的半导体晶体管制作方法的示意图，其中：
图1和图7为晶体管元件部分布局示意图；
图2～6和图9为沿着图1中的切线I-I’所绘示的剖面示意图；
图8为沿着图7中的切线II-II’所绘示的剖面示意图。
主要元件符号说明
100 基底
100a 主表面
101 氧化层
102 浅沟绝缘区
102I 沟槽填充层
102U 上部
102S 侧壁
104 离子阱
106 凹陷区域
106b 底部
110 外延通道层
110E 边缘刻面
112 栅极介电层
120S 源极区
120D 漏极区
121 硅化锗层
AA 主动区域
G1～G4 栅极
SP1～SP4 间隙壁
T 半导体晶体管
Φ 夹角
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图9，其为依据本发明实施例所绘示的半导体晶体管制作方法的示意图，其中，图1和图7例示出晶体管元件部分布局示意图，图2～图6和图9为沿着图1中的切线I-I’(Y轴方向)所绘示的剖面示意图，图8为沿着图7中的切线II-II’(X轴方向)所绘示的剖面示意图。虽然图式中以PMOS元件为例来说明半导体晶体管制作方法，但该领域技术人员应理解本发明也能应用在NMOS晶体管的制作。
如图1和图2所示，首先提供一基底100，具有第一导电型，例如，P型。基底100可以是半导体基底，例如，硅基底，但不限于此。基底100具有一主表面100a。接着，在基底100中形成一浅沟绝缘区102，隔离主动区域AA。浅沟绝缘区102包含沟槽填充层102I，其中沟槽填充层102I具有一上部102U，突出于基底100的主表面100a。依据本发明实施例，上部102U的侧壁102S约略垂直于主表面100a。依据本发明实施例，在主动区域AA上可以有一氧化层101。
如图3所示，接着于基底100中形成一离子阱104。依据本发明实施例，离子阱104可以具有第二导电型，例如，N型。依据本发明实施例，离子阱104可以利用光刻制作工艺和离子注入制作工艺形成。
如图4所示，接着可以选择性的进行一蚀刻制作工艺，蚀刻掉主动区域AA上的氧化层101和部分的基底100，形成一凹陷区域106，其中凹陷区域106的底部106b的深度d约介于0埃至500埃，但不限于此。在其它实施例中，也可以只去除掉主动区域AA上的氧化层101，但是不形成凹陷区域106。
接着，如图5所示，进行一清洁制作工艺和一外延生长(epitaxial growth)制作工艺，从凹陷区域106的底部106b长出一外延通道层110。依据本发明实施例，外延通道层110具有第一导电型，例如，P型。依据本发明实施例，外延通道层110可以包含P型掺杂硅(Pdoped Si)或P型掺杂硅化锗(P doped SiGe)，其中P型掺杂硅化锗以Si(1-x)Gex表示，x＝0.25～0.5。
依据本发明实施例，外延通道层的P型掺质的浓度可以介于
Figure BDA0002379794360000051
Figure BDA0002379794360000052
依据本发明实施例，上述P型掺杂硅化锗的锗浓度介于25at.％～50at.％。依据本发明实施例，外延通道层110的厚度介于5nm至50nm。
依据本发明实施例，如图5右侧的放大图所示，外延通道层110具有一边缘刻面110E，邻近沟槽填充层102的上部102U。依据本发明实施例，边缘刻面110E是一个不平行于基底100的主表面100a的斜面。依据本发明实施例，边缘刻面110E与沟槽填充层102的上部102U的侧壁102S之间的夹角Φ可以介于0°～45°。
接着，如图6所示，在外延通道层110上形成一栅极介电层112，例如，二氧化硅层。依据本发明实施例，栅极介电层112可以利用热氧化方法形成，但不限于此。接着，在栅极介电层112上形成栅极G1～G4。依据本发明实施例，栅极G1～G4可以是多晶硅栅极，但不限于此。依据本发明实施例，在栅极G1～G4的侧壁上可以分别形成间隙壁SP1～SP4。请同时参阅图7，其显示出栅极G1～G4和主动区域AA的相对位置。依据本发明实施例，栅极G1和栅极G4分别通过主动区域AA的两端。
请同时参阅图8，其为沿着图7中的切线II-II’(X轴方向)所绘示的剖面示意图。如图8所示，在此方向上(也就是栅极长度方向)，也可以看见外延通道层110在邻近沟槽填充层102的上部102U处，具有相同的边缘刻面110E。
接着，如图9所示，在基底100的主动区域AA内形成源极区120S和漏极区120D。依据本发明实施例，源极区120S和漏极区120D可以具有第一导电型，例如，P型。例如，形成源极区120S和漏极区120D的方法可以包括在基底100的主动区域AA内蚀刻出沟槽，再以选择性外延生长制作工艺生长出硅化锗层121。上述形成源极区120S和漏极区120D的方法为周知技术，故其细节不另赘述。
依据本发明实施例，外延通道层110介于源极区120S和漏极区120D的栅极G2和栅极G3的下方，构成半导体晶体管T的通道区。此外，外延通道层110可以直接接触到源极区120S和漏极区120D的硅化锗层121。
本发明的优点在于利用外延通道层110取代现有技术中的阈值调整离子注入制作工艺，由于外延通道层110可以具有均一的掺质浓度，因此可以解决现有技术无法有效的控制因元件漏电引起的元件最小电压(Vmin)不稳定现象。此外，本发明还可以提升通道区内的载流子移动率(carrier mobility)。
从图8和图9中可看出，结构上，本发明半导体晶体管T，包含基底100，具有第一导电型(例如P型)，其中基底100具有主表面100a。于基底100中设有离子阱104，具有第二导电型(例如N型)。在离子阱104中设有彼此相区隔的源极区120S和漏极区120D，其中源极区120S和漏极区120D具有所述第一导电型(例如P型)。
本发明半导体晶体管T另包含外延通道层110，具有第一导电型(例如P型)，从基底100的主表面100a或从凹陷区域106的底部106b长出。依据本发明实施例，外延通道层的厚度介于5nm至50nm。外延通道层110位于源极区120S和漏极区120D之间。在外延通道层110上，设有栅极G2和G3。于栅极G2和G3和外延通道层110之间，设有栅极介电层112。
依据本发明实施例，半导体晶体管T另包含浅沟绝缘区102，隔离主动区域AA，其中离子阱104、源极区120S和漏极区120D位于主动区域AA内。依据本发明实施例，浅沟绝缘区102包含沟槽填充层102I，其中沟槽填充层102I的上部102U突出于基底100的主表面100a。
依据本发明实施例，外延通道层110可以具有边缘刻面110E，邻近沟槽填充层102I的上部102U。依据本发明实施例，边缘刻面110E与沟槽填充层102I的上部102U的侧壁102S之间的夹角Φ介于0°～45°。
依据本发明实施例，外延通道层110可以包含P型掺杂硅或P型掺杂硅化锗，但不限于此。依据本发明实施例，例如，外延通道层110的P型掺质的浓度可以介于
Figure BDA0002379794360000071
依据本发明实施例，以P型掺杂硅化锗为例，其中锗浓度可以介于25at.％～50at.％。
例如，以NMOS晶体管为例，外延通道层110可以包含掺杂硼的硅层(Si:B)、掺杂硼的碳化硅层(SiC:B)、掺杂碳的砷化镓层(GaAs:C)或掺杂镁的氮化镓层(GaN:Mg)，其中，以掺杂硼的碳化硅层(SiC:B)为例，其碳浓度可以介于3at.％至15at.％。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属于本发明的涵盖范围。

Claims (20)

1.一种半导体晶体管，其特征在于，包含：
基底，具有第一导电型，其中所述基底具有主表面；
离子阱，具有第二导电型，位于所述基底中；
彼此相区隔的源极区和漏极区，设于所述离子阱中，其中所述源极区和所述漏极区具有所述第一导电型；
外延通道层，具有所述第一导电型，从所述基底的所述主表面长出，并且位于所述源极区和所述漏极区之间；
栅极，设于所述外延通道层上；以及
栅极介电层，位于所述栅极和所述外延通道层之间。
2.如权利要求1所述的半导体晶体管，其中另包含：
浅沟绝缘区，隔离主动区域，其中所述离子阱、所述源极区和所述漏极区位于所述主动区域内。
3.如权利要求2所述的半导体晶体管，其中所述浅沟绝缘区包含沟槽填充层，其中所述沟槽填充层的上部突出于所述基底的所述主表面。
4.如权利要求3所述的半导体晶体管，其中所述外延通道层具有边缘刻面，邻近所述沟槽填充层的所述上部。
5.如权利要求4所述的半导体晶体管，其中所述边缘刻面与所述沟槽填充层的所述上部的侧壁之间的夹角介于0°～45°。
6.如权利要求1所述的半导体晶体管，其中所述第一导电类型为P型，所述第二导电类型为N型。
7.如权利要求1所述的半导体晶体管，其中所述外延通道层包含P型掺杂硅或P型掺杂硅化锗。
8.如权利要求7所述的半导体晶体管，其中所述外延通道层的P型掺质的浓度介于
Figure FDA0002379794350000011
9.如权利要求7所述的半导体晶体管，其中所述P型掺杂硅化锗的锗浓度介于25at.％～50at.％。
10.如权利要求1所述的半导体晶体管，其中所述外延通道层的厚度介于5nm至50nm。
11.一种形成半导体晶体管的方法，包含：
提供第一导电型的基底，其中所述基底具有主表面；
在所述基底中形成第二导电型的离子阱；
从所述基底的所述主表面长出第一导电型的外延通道层；
在所述外延通道层上形成栅极介电层；
在所述栅极介电层上形成栅极；以及
在所述基底中形成第一导电型的源极区和第一导电型的漏极区。
12.如权利要求11所述的方法，其中另包含：
在所述基底中形成浅沟绝缘区，隔离主动区域，其中所述离子阱、所述源极区和所述漏极区位于所述主动区域内。
13.如权利要求12所述的方法，其中所述浅沟绝缘区包含沟槽填充层，其中所述沟槽填充层的上部突出于所述基底的所述主表面。
14.如权利要求13所述的方法，其中所述外延通道层具有边缘刻面，邻近所述沟槽填充层的所述上部。
15.如权利要求14所述的方法，其中所述边缘刻面与所述沟槽填充层的所述上部的侧壁之间的夹角介于0°～45°。
16.如权利要求11所述的方法，其中所述第一导电类型为P型，所述第二导电类型为N型。
17.如权利要求11所述的方法，其中所述外延通道层包含P型掺杂硅或P型掺杂硅化锗。
18.如权利要求17所述的方法，其中所述外延通道层的P型掺质的浓度介于
Figure FDA0002379794350000021
19.如权利要求17所述的方法，其中所述P型掺杂硅化锗的锗浓度介于25at.％～50at.％。
20.如权利要求11所述的方法，其中所述外延通道层的厚度介于5nm至50nm。
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