JP2009049171A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009049171A JP2009049171A JP2007213567A JP2007213567A JP2009049171A JP 2009049171 A JP2009049171 A JP 2009049171A JP 2007213567 A JP2007213567 A JP 2007213567A JP 2007213567 A JP2007213567 A JP 2007213567A JP 2009049171 A JP2009049171 A JP 2009049171A
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Abstract
【解決手段】本発明の一態様に係る半導体装置は、半導体基板と、前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、前記半導体基板の前記ゲート電極下の領域に形成されたチャネル領域と、前記チャネル領域を挟んで形成され、チャネル方向に平行な方向の導電型不純物の濃度分布が、前記ゲート電極から遠くなるに従って濃度が増加する部分を有するソース領域およびドレイン領域と、を有する。
【選択図】図1
Description
J. Murota et al. Surf. Interface Anal. 2002; 34: 423-431.
(半導体装置の構成)
図1は、本発明の第1の実施の形態に係る半導体装置の断面図である。半導体装置1は、半導体基板2上にゲート絶縁膜3を介して形成されたゲート電極4と、ゲート電極4の側面に形成されたゲート側壁5と、半導体基板2内のゲート電極4の下方に形成されたチャネル領域7と、チャネル領域7を挟んで形成されたエピタキシャル層6と、半導体基板2内のエピタキシャル層6の底面と半導体基板2との界面付近の領域に形成された成長抑制領域8と、ゲート電極4の上面に形成された第1のシリサイド層9aと、エピタキシャル層6の上面に形成された第2のシリサイド層9bと、半導体基板2内に形成された素子分離領域10と、を有して概略構成される。
図4A(a)〜(c)、図4B(d)〜(f)、図4C(g)〜(h)は、本発明の第1の実施の形態に係る半導体装置の製造工程を示す断面図である。
本発明の第1の実施の形態によれば、成長抑制領域8を形成し、導入する導電型不純物の濃度を大きくしながら、エピタキシャル層6を半導体基板2のチャネル領域7側からX方向に成長させることにより、エピタキシャル層6中のチャネル領域7近傍の領域における導電型不純物の濃度を他の領域よりも低くすることができる。このため、エピタキシャル層6をチャネル領域7に近づけて、ロールオフ特性の劣化を起こさずに、効果的にチャネル領域に歪みを与えることができる。
本発明の第2の実施の形態は、成長抑制領域8の代わりに成長抑制膜18を形成する点において第1の実施の形態と異なる。なお、他の部材の構成や製造工程等、第1の実施の形態と同様の点については、簡単のために説明を省略する。
図7は、本発明の第2の実施の形態に係る半導体装置の断面図である。
図8(a)〜(c)は、本発明の第2の実施の形態に係る半導体装置の製造工程を示す断面図である。
本発明の第2の実施の形態によれば、第1の実施の形態に係る成長抑制領域8の代わりに成長抑制膜18を形成し、第1の実施の形態と同様の効果を得ることができる。
本発明の第3の実施の形態は、エピタキシャル層6の形状において第1の実施の形態と異なる。なお、他の部材の構成や製造工程等、第1の実施の形態と同様の点については、簡単のために説明を省略する。
図9は、本発明の第3の実施の形態に係る半導体装置の断面図である。
図10A(a)〜(c)、図10B(d)〜(f)、図10C(g)〜(h)は、本発明の第3の実施の形態に係る半導体装置の製造工程を示す断面図である。
本発明の第3の実施の形態によれば、エピタキシャル層6にエクステンション領域6eを設けることにより、より効果的にロールオフ特性の劣化を抑制することができる。
本発明の第4の実施の形態は、エピタキシャル層6および成長抑制領域8の形状において第1の実施の形態と異なる。なお、他の部材の構成や製造工程等、第1の実施の形態と同様の点については、簡単のために説明を省略する。
図11は、本発明の第4の実施の形態に係る半導体装置の断面図である。
図12A(a)〜(c)、図12B(d)〜(f)、図12C(g)〜(i)は、本発明の第4の実施の形態に係る半導体装置の製造工程を示す断面図である。
本発明の第4の実施の形態によれば、成長抑制領域8の不純物濃度に、チャネル領域7側から素子分離領域10側に向かって濃度が増加する分布を与えることにより、エピタキシャル層6の形状を階段状にすることができる。エピタキシャル層6の階段形状の段数、段差等は、成長抑制領域8の不純物濃度の分布を調節することにより変えることができ、それにより、エピタキシャル層6がチャネル領域7へ与える歪みの大きさを変えることができる。
本発明は、上記各実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。
(1) 半導体基板と、
前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記半導体基板の前記ゲート電極下の領域に形成されたチャネル領域と、
前記チャネル領域を挟んで形成されたエピタキシャル層と、
前記半導体基板内の前記エピタキシャル層の底面と前記半導体基板との界面付近の少なくとも一部の領域である所定の領域に形成された、結晶のエピタキシャル成長を抑制する成長抑制部と、
を有することを特徴とする半導体装置。
(2) 前記成長抑制部は、前記半導体基板の前記所定の領域に不純物を注入して形成される成長抑制領域、または前記半導体基板の前記所定の領域上に形成された絶縁膜からなる成長抑制膜であることを特徴とする(1)に記載の半導体装置。
(3) 前記成長抑制領域は、前記不純物の濃度が異なる複数の領域を有し、
前記エピタキシャル層は、前記成長抑制領域の前記不純物の濃度が異なる前記複数の領域の位置に対応した、表面の高さの異なる複数の領域を有することを特徴とする(2)に記載の半導体装置。
Claims (5)
- 半導体基板と、
前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記半導体基板の前記ゲート電極下の領域に形成されたチャネル領域と、
前記チャネル領域を挟んで形成され、チャネル方向に平行な方向の導電型不純物の濃度分布が、前記ゲート電極から遠くなるに従って濃度が増加する部分を有するソース領域およびドレイン領域と、
を有することを特徴とする半導体装置。 - 前記半導体基板内の前記ソース領域および前記ドレイン領域の底面と前記半導体基板との界面付近の少なくとも一部の領域である所定の領域に、結晶のエピタキシャル成長を抑制する成長抑制部が形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記成長抑制部は、前記半導体基板の前記所定の領域に不純物を注入して形成される成長抑制領域、または前記半導体基板の前記所定の領域上に形成された絶縁膜からなる成長抑制膜であることを特徴とする請求項2に記載の半導体装置。
- 前記ソース領域および前記ドレイン領域の前記導電型不純物の濃度は、前記エピタキシャル層の前記チャネル領域に隣接する領域において最も低いことを特徴とする請求項1から3のいずれかに記載の半導体装置。
- 前記ソース領域および前記ドレイン領域は、他の領域よりも深さが浅く、前記チャネル領域に隣接したエクステンション領域を含むことを特徴とする請求項1から4のいずれかに記載の半導体装置。
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