CN109473398B - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN109473398B
CN109473398B CN201710800066.2A CN201710800066A CN109473398B CN 109473398 B CN109473398 B CN 109473398B CN 201710800066 A CN201710800066 A CN 201710800066A CN 109473398 B CN109473398 B CN 109473398B
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isolation structure
outer layer
substrate
gate
forming
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CN109473398A (zh
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陈冠宏
李荣原
陆俊岑
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制造方法。所述半导体元件包括基底、隔离结构、外层结构以及栅极结构。隔离结构配置于基底上。外层结构环绕隔离结构的侧壁。栅极结构环绕外层结构的中间部分，使得被栅极结构所覆盖的中间部分成为通道区，而中间部分的两侧处的外层结构则分别成为源极区与漏极区。

Description

半导体元件及其制造方法
技术领域
本发明涉及一种集成电路及其制造方法，且特别是有关于一种半导体元件及其制造方法。
背景技术
随着半导体制作工艺技术的快速发展，为了增进元件的速度与效能，整个电路元件的尺寸必须不断缩小，以提升元件的集成度。目前已经开发出立体或非平面(non-planar)多栅极晶体管元件来取代平面晶体管(planar)元件。举例来说，双栅极(dual-gate)鳍式场效晶体管(FinFET)元件、三栅极(tri-gate)FinFET元件以及Ω(omega)式FinFET元件等非平面多栅极晶体管元件都已被提出。现在，则更发展出利用纳米线作为通道的环绕式栅极(gate-all-around，GAA)晶体管元件，作为继续提升元件集成度与元件效能的方案。然而，传统纳米线晶体管元件有漏电流过大的问题，其导致可靠度降低。
发明内容
本发明提供一种半导体元件及其制造方法，其将通道材料环绕隔离结构的侧壁，以减少漏电流，并可增加有源区域(active region)面积，进而提升导通电流(Ioncurrent)。
本发明提供一种半导体元件包括基底、隔离结构、外层结构以及栅极结构。隔离结构配置于基底上。外层结构环绕隔离结构的侧壁。栅极结构环绕外层结构的中间部分，使得被栅极结构所覆盖的中间部分成为通道区，而中间部分的两侧处的外层结构则分别成为源极区与漏极区。
在本发明的一实施例中，所述隔离结构垂直于所述基底的顶面，以形成垂直纳米线结构。
在本发明的一实施例中，所述隔离结构的材料包括空气、介电材料或其组合。
在本发明的一实施例中，所述介电材料包括氧化硅、氮化硅、氮氧化硅或是介电常数低于4的低介电常数(low-k)材料。
在本发明的一实施例中，所述外层结构的材料包括硅、锗、2D材料或其组合。
在本发明的一实施例中，所述2D材料包括石墨烯、金属硫属化合物或其组合。
在本发明的一实施例中，所述金属硫属化合物包括Mo、W、Nb、V、Ta、Ti、Zr、Hf、Tc、Re、Cu、Ga、In、Sn、Ge以及Pb中的一者的金属原子；以及包括S、Se和Te中的一者的硫属元素原子。
在本发明的一实施例中，所述通道区、所述源极区以及所述漏极区为同一导电型。
在本发明的一实施例中，所述源极区以及所述漏极区为同一导电型，所述源极区以及所述漏极区与所述通道区为不同导电型。
在本发明的一实施例中，所述隔离结构包括：主体部与突出部。主体部毯覆在所述基底上。突出部垂直突出于所述主体部的顶面。所述外层结构环绕所述突出部的侧壁。
在本发明的一实施例中，所述突出部的数量为多个，多个突出部中的一者的直径与所述多个突出部中的另一者的直径相同。
在本发明的一实施例中，所述突出部的数量为多个，多个突出部中的一者的直径与所述多个突出部中的另一者的直径不同。
在本发明的一实施例中，所述栅极结构包括栅介电层与栅电极，所述栅介电层位于所述栅电极与所述通道区之间。
本发明提供一种半导体元件的制造方法，其步骤如下。在基底上形成垂直于所述基底的顶面的隔离结构；在所述隔离结构的侧壁上形成外层结构；在所述基底上形成牺牲层，所述牺牲层环绕所述外层结构的下部部分；在所述牺牲层上形成栅极结构，所述栅极结构环绕所述外层结构的中间部分，使得被所述栅极结构所覆盖的所述中间部分成为通道区，而所述外层结构的所述下部部分与上部部分则分别成为源极区与漏极区；以及移除所述牺牲层。
在本发明的一实施例中，在所述基底上形成垂直于所述基底的所述顶面的所述隔离结构的步骤如下。在所述基底上依序形成隔离结构材料与掩模图案；以所述掩模图案为掩模，移除所述隔离结构材料的一部分；以及对所述隔离结构材料的剩余部分进行圆角化制作工艺。
在本发明的一实施例中，所述圆角化制作工艺包括标准清洗(SC1)制作工艺、含稀释氢氟酸(DHF)的清洗制作工艺或其组合。
在本发明的一实施例中，在所述隔离结构的所述侧壁上形成所述外层结构的步骤如下。在进行所述圆角化制作工艺之后，在所述隔离结构上共形地形成晶种层；在所述晶种层上外延成长通道材料；以及回蚀刻所述晶种层与所述通道材料，以暴露出所述掩模图案的顶面。
在本发明的一实施例中，所述通道材料包括硅、锗、2D材料或其组合。
在本发明的一实施例中，所述牺牲层的材料包括氮化硅、氮氧化硅、碳化硅或其组合。
在本发明的一实施例中，所述隔离结构的材料包括空气、介电材料或其组合。
基于上述，本发明于基底上形成垂直于所述基底的顶面的隔离结构，并将外层结构环绕所述隔离结构的侧壁。之后，将栅极结构环绕所述外层结构的中间部分，使得被所述栅极结构所覆盖的所述中间部分成为通道区，而所述中间部分的两侧处的所述外层结构则分别成为源极区与漏极区。相较于传统纳米线晶体管，本发明的半导体元件可减少漏电流，以提升半导体元件的可靠度。另外，本发明还可增加有源区域面积，进而提升导通电流。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1A至图1J为本发明第一实施例所绘示的半导体元件的制造流程的剖面示意图；
图2为本发明第二实施例所绘示的半导体元件的立体示意图。
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而，本发明也可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再一一赘述。
图1A至图1J为依照本发明第一实施例所绘示的半导体元件的制造流程的剖面示意图。在本实施例中，所述半导体元件可以是具有隔离结构的纳米线晶体管，但本发明不以此为限。
请参照图1A，首先，在基底100上依序形成隔离结构材料102与掩模层104。在一实施例中，基底100可例如为半导体基底、半导体化合物基底或是绝缘层上有半导体基底(Semiconductor Over Insulator，SOI)。半导体例如是IVA族的原子，例如硅或锗。半导体化合物例如是IVA族的原子所形成的半导体化合物，例如是碳化硅或是硅化锗，或是IIIA族原子与VA族原子所形成的半导体化合物，例如是砷化镓。在一实施例中，隔离结构材料102包括介电材料。所述介电材料包括氧化硅、氮化硅、氮氧化硅或是介电常数低于4的低介电常数材料。在一实施例中，掩模层104可以是硬掩模层，其与隔离结构材料102具有高蚀刻选择比。在本实施例中，掩模层104包括但不限于氮化硅。
请参照图1A与图1B，图案化掩模层104，以形成掩模图案104a。接着，以掩模图案104a为掩模，移除所述隔离结构材料102的一部分，以于基底100上形成垂直于基底100的顶面的隔离结构106。详细地说，隔离结构106包括主体部106a与多个突出部106b。主体部106a毯覆在基底100上。突出部106b垂直突出于主体部106a的顶面。如图1B所示，隔离结构106的突出部106b彼此分离，使得隔离结构106形成梳状结构。在一实施例中，突出部106b可以是柱状结构。所述柱状结构包括圆形柱结构、椭圆形柱状结构、多边形柱状结构、不规则形柱状结构等。在一实施例中，突出部106b的一者的宽度(或直径)W1可介于4纳米至10纳米之间。突出部106b的另一者的宽度(或直径)W2可介于4纳米至10纳米之间。也就是说，隔离结构106的突出部106b可视为垂直纳米线结构。在一实施例中，宽度W1可等于宽度W2，也就是说，各突出部106b的宽度相同。在替代实施例中，宽度W1可不等于宽度W2，也就是说，各突出部106b的宽度也可不同。
在一实施例中，在移除所述隔离结构材料102的一部分之后，可对隔离结构材料102的剩余部分(以下称为隔离结构106)进行圆角化制作工艺，以修复隔离结构106的表面粗糙度(surface roughness)。因此，相较于进行圆角化制作工艺之前的隔离结构106，圆角化后的隔离结构106具有更圆滑的轮廓。在一实施例中，所述圆角化制作工艺可以是湿式清洗制作工艺，其包括标准清洗制作工艺(Standard Clean 1，SC1)、含稀释氢氟酸(DHF)的清洗制作工艺或其组合。具体来说，所述标准清洗制作工艺包括使用NH4OH、H2O2以及H2O的清洗溶液。所述NH4OH、H2O2以及H2O的比例可以实际需求来调整，本发明不以此为限。
请参照图1C，在进行所述圆角化制作工艺之后，在隔离结构106上共形地形成晶种层108。晶种层108共形地覆盖隔离结构106的表面与掩模图案104a的表面。在一实施例中，晶种层108的材料包括硅、锗、碳或其组合，其形成方法包括原子层沉积法(ALD)。
请参照图1D，在晶种层108上外延成长通道材料110。通道材料110共形覆盖晶种层108的表面。在一实施例中，通道材料110包括硅、锗、2D材料或其组合。所述2D材料包括石墨烯、金属硫属化合物或其组合。所述金属硫属化合物包括Mo、W、Nb、V、Ta、Ti、Zr、Hf、Tc、Re、Cu、Ga、In、Sn、Ge以及Pb中的一者的金属原子；以及包括S、Se和Te中的一者的硫属元素原子。在一实施例中，在外延成长通道材料110时，可掺入N型掺质或是P型掺质，使得通道材料110具有N型导电型或是P型导电型。举例来说，当通道材料110为硅时，N型掺质可例如是磷或是砷；P型掺质可例如是硼。通道材料110的掺杂浓度可依实际需求来调整，本发明不以此为限。在替代实施例中，也可在通道材料110上形成掺杂层(未绘示)。之后，进行回火处理，使得所述掺杂层中的掺质扩散进入通道材料110中，以形成具有N型导电型或是P型导电型通道材料110。
为了清楚起见，后续图1E至图1J都以图1D的部分200的放大图来说明。
请参照图1D与图1E，回蚀刻晶种层108与通道材料110，以暴露出掩模图案104a的顶面与隔离结构106的主体部106a的顶面。如图1E所示，剩余的晶种层108与通道材料110(以下称为外层结构112，且将两层的晶种层108与通道材料110绘示为单层的外层结构112)覆盖且环绕隔离结构106的突出部106b的侧壁。在此情况下，外层结构112的顶面低于掩模图案104a的顶面。在一实施例中，外层结构112的厚度T1可介于10纳米至40纳米之间。
请参照图1E与图1F，移除掩模图案104a，以暴露出隔离结构106的突出部106b的顶面。在一实施例中，隔离结构106的突出部106b的顶面与外层结构112为共平面。但本发明不以此为限，在其他实施例中，隔离结构106的突出部106b的顶面与外层结构112也可不共平面。
请参照图1G，在基底100上形成牺牲层114。牺牲层114覆盖隔离结构106的主体部106a的顶面，且环绕外层结构112的下部部分112a。在一实施例中，牺牲层114的材料包括氮化硅、氮氧化硅、碳化硅或其组合，其形成方法包括化学气相沉积法(CVD)。在一实施例中，牺牲层114的厚度T2可介于20纳米至60纳米之间，但本发明不以此为限。在本实施例中，牺牲层114的厚度T2可用以定义源极区或漏极区的面积。
请参照图1H与图1I，在牺牲层114上形成栅极结构120。栅极结构120环绕外层结构112的中间部分112b。具体来说，如图1H所示，在牺牲层114上形成栅介电层116，栅介电层116环绕外层结构112的中间部分112b。在一实施例中，栅介电层116的材料包括氧化硅或是介电常数大于4的高介电常数材料，例如是氮化硅、氧化钽、氧化铝、氧化铪或其组合。栅介电层116的形成方法可以是热氧化法、ALD或CVD。接着，如图1I所示，在于牺牲层114上形成栅电极118。栅电极118环绕栅介电层116的表面，使得栅介电层116位于栅电极118与中间部分112b(或通道区)之间。在一实施例中，栅电极118的材料包括导电材料，其可例如是金属、多晶硅、硅化金属或其组合。栅电极118的形成方法可以是物理气相沉积法(PVD)或CVD。
请参照图1I与图1J，移除牺牲层114，以暴露出外层结构112的下部部分112a，以形成具有隔离结构106的纳米线晶体管10。如图1J所示，外层结构112包括下部部分112a、中间部分112b以及上部部分112c。中间部分112b位于下部部分112a与上部部分112c之间。在一实施例中，被栅极结构120所覆盖的中间部分112b可视为通道区；下部部分112a与上部部分112c则可视为源极区与漏极区。在一实施例中，所述通道区、所述源极区以及所述漏极区可以是同一导电型，以形成无接面场效晶体管(junctionless FET)。在替代实施例中，所述源极区以及所述漏极区为同一导电型，而所述源极区以及所述漏极区与所述通道区为不同导电型，以形成金属氧化物半导体场效晶体管(MOSFET)。举例来说，所述源极区以及所述漏极区可以是N型导电型；而所述通道区可以是P型导电型。
值得注意的是，相较于传统纳米线晶体管，本实施例的纳米线晶体管10具有隔离结构106(或突出部106b)，其可减少漏电流，由此提升元件的可靠度。另一方面，本实施例也可调整隔离结构106(或突出部106b)的宽度或直径，以增加有源区域或通道区的面积，进而提升元件的导通电流。
在上述实施例中，隔离结构106的材料包括介电材料。但本发明不以此为限，在其他实施例中，隔离结构106也可以是空气或空气间隙，其可降低隔离结构106的介电常数，以更进一步减少漏电流的现象。当隔离结构106为空气或空气间隙时，其形成方法例如包括以下步骤。在移除牺牲层114的后(如图1J所示)，在基底100上形成介电层(未绘示)，以包覆整个纳米线晶体管10的表面。之后，图案化所述介电层，以暴露出隔离结构106的突出部106b的顶面。接着，移除隔离结构106的突出部106b，以形成空气间隙(未绘示)。然后，密封所述空气间隙，以形成具有空气间隙的纳米线晶体管(未绘示)。
图2为依照本发明第二实施例所绘示的半导体元件的立体示意图。
本实施例的纳米线晶体管20包括基底100、隔离结构106、外层结构112以及栅极结构120。隔离结构106配置于基底100上。具体来说，隔离结构106包括主体部106a与多个突出部106b。主体部106a毯覆在基底100上。突出部106b垂直突出于主体部106a的顶面。外层结构112环绕隔离结构106的突出部106b的侧壁。栅极结构120环绕外层结构112的中间部分112b，使得被栅极结构120所覆盖的中间部分112b成为通道区，而中间部分112b的两侧处的外层结构(亦即下部部分112a与上部部分112c)则分别成为源极区与漏极区。
在一实施例中，突出部106b的一者的宽度(或直径)W1可等于突出部106b的另一者的宽度(或直径)W2。在替代实施例中，宽度W1可不等于宽度W2，也就是说，各突出部106b的宽度不同。因此，环绕突出部106b的一者的外层结构112的直径D1可等于或是不等于环绕突出部106b的另一者的外层结构112的直径D2。换言之，本实施例的纳米线晶体管20可调整隔离结构106的突出部106b的宽度或是调整环绕突出部106b的外层结构112的直径，以符合各种元件的电压需求。
综上所述，本发明于基底上形成垂直于所述基底的顶面的隔离结构，并将外层结构环绕所述隔离结构的侧壁。之后，将栅极结构环绕所述外层结构的中间部分，使得被所述栅极结构所覆盖的所述中间部分成为通道区，而所述中间部分的两侧处的所述外层结构则分别成为源极区与漏极区。相较于传统纳米线晶体管，本发明的半导体元件可减少漏电流，以提升半导体元件的可靠度。另外，本发明还可增加有源区域面积，进而提升导通电流。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (16)

1.一种半导体元件，包括：
隔离结构，配置于基底上，其中所述隔离结构的材料包括：
主体部，毯覆在所述基底上；以及
突出部，垂直突出于所述主体部的顶面而为空气或空气间隙；
外层结构，环绕所述隔离结构中所述突出部的侧壁，其中所述外层结构直接接触所述突出部，所述主体部分隔所述外层结构与所述基底；以及
栅极结构，环绕所述外层结构的中间部分，使得被所述栅极结构所覆盖的所述中间部分成为通道区，而所述中间部分的两侧处的所述外层结构则分别成为源极区与漏极区。
2.如权利要求1所述的半导体元件，其中所述隔离结构垂直于所述基底的顶面，以形成垂直纳米线结构。
3.如权利要求1所述的半导体元件，其中所述外层结构的材料包括硅、锗、2D材料或其组合。
4.如权利要求3所述的半导体元件，其中所述2D材料包括石墨烯、金属硫属化合物或其组合。
5.如权利要求4所述的半导体元件，其中所述金属硫属化合物包括Mo、W、Nb、V、Ta、Ti、Zr、Hf、Tc、Re、Cu、Ga、In、Sn、Ge以及Pb中的一者的金属原子；以及包括S、Se和Te中的一者的硫属元素原子。
6.如权利要求1所述的半导体元件，其中所述通道区、所述源极区以及所述漏极区为同一导电型。
7.如权利要求1所述的半导体元件，其中所述源极区以及所述漏极区为同一导电型，所述源极区以及所述漏极区与所述通道区为不同导电型。
8.如权利要求7所述的半导体元件，其中所述突出部的数量为多个，多个突出部中的一者的直径与所述多个突出部中的另一者的直径相同。
9.如权利要求7所述的半导体元件，其中所述突出部的数量为多个，多个突出部中的一者的直径与所述多个突出部中的另一者的直径不同。
10.如权利要求1所述的半导体元件，其中所述栅极结构包括栅介电层与栅电极，所述栅介电层位于所述栅电极与所述通道区之间。
11.一种半导体元件的制造方法，包括：
在基底上形成垂直于所述基底的顶面的隔离结构，所述隔离结构包括主体部与多个突出部；
在所述隔离结构的侧壁上形成外层结构；
在所述基底上形成牺牲层，所述牺牲层环绕所述外层结构的下部部分；
在所述牺牲层上形成栅极结构，所述栅极结构环绕所述外层结构的中间部分，使得被所述栅极结构所覆盖的所述中间部分成为通道区，而所述外层结构的所述下部部分与上部部分则分别成为源极区与漏极区；移除所述牺牲层，以形成纳米线晶体管；
在所述基底上形成介电层，以包覆整个所述纳米线晶体管的表面；
图案化所述介电层，以暴露出所述隔离结构的所述多个突出部的顶面；
移除所述隔离结构的所述多个突出部，以形成空气间隙；以及
密封所述空气间隙，其中所述外层结构直接接触所述空气间隙，所述主体部分隔所述外层结构与所述基底。
12.如权利要求11所述的半导体元件的制造方法，其中于所述基底上形成垂直于所述基底的所述顶面的所述隔离结构的步骤包括：
在所述基底上依序形成隔离结构材料与掩模图案；
以所述掩模图案为掩模，移除所述隔离结构材料的一部分；以及
对所述隔离结构材料的剩余部分进行圆角化制作工艺。
13.如权利要求12所述的半导体元件的制造方法，其中所述圆角化制作工艺包括标准清洗制作工艺、含稀释氢氟酸的清洗制作工艺或其组合。
14.如权利要求12所述的半导体元件的制造方法，其中于所述隔离结构的所述侧壁上形成所述外层结构的步骤包括：
在进行所述圆角化制作工艺之后，在所述隔离结构上共形地形成晶种层；
在所述晶种层上外延成长通道材料；以及
回蚀刻所述晶种层与所述通道材料，以暴露出所述掩模图案的顶面。
15.如权利要求14所述的半导体元件的制造方法，其中所述通道材料包括硅、锗、2D材料或其组合。
16.如权利要求11所述的半导体元件的制造方法，其中所述牺牲层的材料包括氮化硅、氮氧化硅、碳化硅或其组合。
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