TW201543676A - 整合富含鍺之ｐ－ｍｏｓ源極／汲極接觸之技術 - Google Patents

整合富含鍺之ｐ－ｍｏｓ源極／汲極接觸之技術 Download PDF

Info

Publication number
TW201543676A
TW201543676A TW104104385A TW104104385A TW201543676A TW 201543676 A TW201543676 A TW 201543676A TW 104104385 A TW104104385 A TW 104104385A TW 104104385 A TW104104385 A TW 104104385A TW 201543676 A TW201543676 A TW 201543676A
Authority
TW
Taiwan
Prior art keywords
layer
source
rich
type
sige
Prior art date
Application number
TW104104385A
Other languages
English (en)
Other versions
TWI673871B (zh
Inventor
Glenn Glass
Anand Murthy
Tahir Ghani
Ying Pang
Nabil G Mistkawi
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=54145116&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW201543676(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW201543676A publication Critical patent/TW201543676A/zh
Application granted granted Critical
Publication of TWI673871B publication Critical patent/TWI673871B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

用於改善整合富含鍺(Ge)p-MOS源極/汲極接觸以，例如，減低接觸電阻之技術被揭露。該技術包括直接沉積p型富含Ge層在矽(Si)表面上接觸溝渠位置。因為Si表面有利於高品質導電富含Ge材料的沉積。在一範例方法中，富含Ge層被沉積在Si基板之表面上在源極/汲極接觸溝渠位置中，在去除先前沉積在源極/汲極位置中之犧牲的矽化鍺(SiGe)層之後。在另一範例方法中，富含Ge層被沉積在接觸溝渠位置中之Si披覆層上，其中Si披覆層沉積在功能的p型SiGe層上。在一些情形下，富含Ge層包含至少50%的鍺(且可含有錫(Sn)和/或Si)且硼(B)摻雜以高於1E20 cm-3的水平。

Description

整合富含鍺之P-MOS源極/汲極接觸之技術
本發明係有關一種整合富含鍺之P-MOS源極/汲極接觸之技術。
增加包括電晶體(transistors)、二極體(diodes)、電阻(resistors)、電容(capacitors)之電路裝置以及形成在半導體基板上之其他被動及主動電子裝置的效能通常是設計、製造和操作那些裝置過程中主要的考慮因素。例如，於設計及製造或形成金屬-氧化物-半導體(metal-oxide-semiconductor，MOS)電晶體裝置過程中，例如在互補式金屬-氧化物-半導體(CMOS)裝置中所使用，其通常希望最小化與源極/汲極區及接觸關聯之電阻，也被稱為組件的外部電阻。減少外部電阻能夠改善於給定源極至汲極的電晶體電流。
102、104、106、108、108’、109、110、112、114、116、116’、117、118、120‧‧‧步驟
200、300、400‧‧‧基板
202‧‧‧閘極介電層
203‧‧‧高k閘極介電層
204、304‧‧‧閘極電極層
205、305、405‧‧‧金屬閘極電極
206、360、460‧‧‧硬遮罩層
208、308、408‧‧‧間隔物
212、214、312、314‧‧‧源極/汲極凹洞
212A/214A‧‧‧選擇性尖端區
218、220、318、320‧‧‧犧牲的SiGe層
218’、220’、418’‧‧‧SiGe層
222、322、422‧‧‧披覆層
224、226、224’、226’、324、326、324’、326’、424、426、424’、426’‧‧‧富含Ge層
230、330‧‧‧絕緣層
240、240’‧‧‧源極/汲極接觸溝渠
250‧‧‧源極/汲極金屬接觸插塞
301、401‧‧‧STI/絕緣層
309‧‧‧通道區
310‧‧‧鰭片
318’、320’‧‧‧功能的SiGe層
410‧‧‧奈米線
1000‧‧‧運算裝置
1002‧‧‧母板
1004‧‧‧處理器
1006‧‧‧通訊晶片
第1圖根據本發明一個或多個實施方式之使用犧牲矽化鍺(silicon germanium，SiGe)層以及包括沉積在矽(Si)表面上之富含鍺之源極/汲極接觸層之形成電晶體的方法。
第1’圖根據本發明一個或多個實施方式之使用功能性SiGe層以及包括沉積在Si表面上之富含鍺之源極/汲極接觸層之形成電晶體的方法。
第2A-H’圖根據本發明各種實施方式繪示當執行第1圖或第1’圖任一個用於平面或非平面電晶體架構的方法時之範例結構。
第3A-J’圖根據本發明各種實施方式繪示當執行第1圖或第1’圖任一個用於非平面(即，鰭片式)電晶體結構的方法時之範例結構。
第4圖根據本發明一實施方式繪示當執行第1圖的方法時形成之奈米線/奈米帶電晶體結構之透視圖。
第4’圖根據本發明一實施方式繪示當執行第1’圖的方法時形成之奈米線/奈米帶電晶體結構之透視圖。
第5圖根據本發明一個或多個實施方式繪示之實現具有一個或多個電晶體結構之運算系統。
【發明內容與實施方式】
用於改善整合富含鍺(Ge)p-MOS源極/汲極接觸以，例如，減小接觸電阻之技術被揭露。該技術包括直接沉積p型富含Ge層在接觸溝渠位置之矽(Si)表面 上，因為Si表面有利於沉積高品質導電富含Ge之材料。 在一範例方法中，在去除犧牲矽化鍺(SiGe)層之後在沉積在源極/汲極位置之前，富含Ge層被沉積在源極/汲極接觸溝渠位置中之Si基板上。在另一範例方法中，富含Ge層被沉積在接觸溝渠位置中之Si披覆層上，其中Si披覆層被沉積在功能性p型SiGe層上。在一些情形下，富含Ge層包含至少50%Ge(以及可含有錫(Sn)和/或Si)且硼(B)摻雜高於1E20 cm-3之水平。當根據本發明，許多電晶體配置及合適的製造製程將顯而易見，包括平面和非平面電晶體結構(即，鰭片式和奈米線/奈米帶電晶體配置)。此技術尤其適合用於實施P型MOS(p-MOS)裝置，雖然其它電晶體配置也可受益，像是互補式MOS(CMOS)裝置。根據本發明，許多配置及變化是顯而易見的。
概述
如前面所解釋的，增加電晶體中的驅動電流通常可藉由減小外部電阻，例如接觸電阻，而達成。在一些情況下，用於p型MOS(p-MOS)電晶體之接觸電阻可藉由使用富含Ge材料作為有效的歐姆接觸材料而減小。然而，在MOS製造製程流程中，假如其被沉積在源極/汲極的位置問題可能出現在保存富含Ge材料。例如，富含Ge材料在相關於接觸循環處理之蝕刻、灰化及退火中可能容易受到侵蝕和非故意的去除。問題也可能出現在當材 料沉積在接觸溝渠位置時為獲得富含Ge材料之高品質沉積(即，作為判斷薄膜電阻率)。例如，在接觸溝渠位置之富含Ge材料被沉積的表面可能是「髒的」(即，接觸循環處理的結果)和/或難以清潔。假如富含Ge材料被沉積在「髒的」表面上，那麼其結果可能在局部區或整體產生較差結晶品質的非晶(amorphous)原子排列(atomic arrangement)。較差結晶品質導致較差的摻質激活(activation)及高接觸電阻(contact resistance)。
因此，根據本發明一個或多個實施方式，用 於改善整合富含Ge p-MOS源極/汲極接觸以，例如，減小接觸電阻之技術被揭露。如前面所描述，富含Ge材料可以被使用作為有效的歐姆接觸材料；然而，問題可能出現如果在製程流程中太早沉積之富含Ge材料的保存(即，在源極/汲極處理流程中早於接觸循環處理)，或如果在製程流程中太晚沉積用於獲得富含Ge層之高品質沉積(即，由於「髒的」和/或難以清潔之被沉積的表面上)。因此，本文各種敘述之技術包括直接沉積富含Ge層在接觸溝渠位置之矽(Si)表面上，因為Si具有其容易達到結晶品質清潔表面之特性(即，相較於矽化鍺(SiGe)，其通常用於p-MOS的源極和汲極)。注意，作為本文各種敘述之富含Ge層被使用於p-MOS的源極/汲極接觸且因此為p型層，這意味著它具有p型摻雜(即，使用硼(B)、鎵(Ga)和/或任何其它合適的摻雜劑)。
根據本發明將顯而易見，直接在乾淨的Si表 面上沉積富含Ge層通常使用兩種方法之一來實現：1)在去除犧牲的SiGe層之後沉積富含Ge層在接觸溝渠位置之Si基板上，或2)沉積富含Ge層在接觸溝渠位置之Si披覆層上，其中Si披覆層沉積在功能性p型SiGe層上。 注意在兩個方法中，在接觸循環處理前，SiGe層(無論犧牲或功能性)沉積在源極/汲極位置。還要注意的是，在第一個方法的實施方式中，SiGe層為犧牲的層，而在第二個方法的實施方式中，SiGe層為功能性層，如將在本文更詳細地討論。還應注意雖然在某些情況下SiGe層被稱為犧牲的，它可以是p型摻雜且因此能夠為功能性；然而，在SiGe層被稱為犧牲的係因為在p接觸製程期間它的目的是被去除的，如根據本發明將顯而易見。
一些情況下在其中SiGe層為犧牲的實施方式 中，SiGe層可包含15-30%的鍺。雖然，在某些情況下，犧牲的層可為10%的鍺至純鍺。此外，一些情況下，犧牲的SiGe層也可以是未摻雜。雖然，在其他情況下，犧牲的層可具有一些含量的p型摻雜。在一些實施方式中，犧牲的SiGe層可使用其選擇性的對Si和絕緣體材料的SiGe蝕刻而被去除。這種選擇性蝕刻可以包括，例如，包括水、硝酸、有機酸(如，乙酸或檸檬酸)和/或氫氟酸的濕式蝕刻，並且選擇性蝕刻可具有例如約300Å/min的可用蝕刻速率。
一些情況下(如，由於性能原因以最大化應 力)在其中SiGe層為功能性的實施方式中，SiGe層可包含30-70%的鍺。此外，在此實施方式中，功能性SiGe層為p型摻雜(即，摻雜B)。在其中SiGe層為功能性的實施方式中，Si披覆層可在接觸循環處理前沉積在功能性SiGe層上。接著，在接觸溝渠處理過程中，接觸溝渠蝕刻可以在一個方式下進行，使得Si披覆層可被保留用於後需的富含Ge層沉積。在此種方式中，蝕刻阻擋層(即，氮化物、碳化物或其它具有想比於其上的氧化物/絕緣體足夠不同之蝕刻速率的合適材料)可被使用在接觸溝渠蝕刻中幫助保留Si披覆層，如將在本文更詳細地討論。
在一些實施方式中，富含Ge層的材料可包含 至少50%的鍺(可達100%的鍺)，且也可以包括Si和錫(Sn)。例如，在一些情況下，富含Ge材料可為具有鍺範圍為50-99%的SiGe。在其他況下，富含Ge材料可為鍺化錫(GeSn)，具有可達15%的錫，且可以，在一些情況下，含有微量級(trace levels)的Si(即，<5%)。回想富含Ge層為p型層，且因此為p型摻雜(即，摻雜B)。在一些情況下，p型富含Ge層可為約2E20 cm-3水平之B摻雜，然而，在一些情況下，p型富含Ge層可為高於5E19 cm-3水平之摻雜B，且高達5E21 cm-3。例如，在一些實施方式中，沉積富含Ge層包括具有例如最大溫度為550或500度C的處理。
各種本文所敘述的技術可被用於形成任何數 目的裝置和系統中的電晶體裝置。一些實施方式中，如具有n型MOS(n-MOS)和p型MOS(p-MOS)電晶體兩者的CMOS裝置，可存在n型區。在其中可存在n型區的情形中，接觸可被圖形化從而從n接觸分離開放p接觸。 這也提供當n接觸為獨立地開放時之益處，n型特定的金屬可被使用於降低接觸電阻之原因。此外，可接收的附加益處為p和n接觸金屬不具有需要被共享的結果，如在習知接觸處理。在其他實施方式中，選擇性也包括自然的選擇性。例如，當p型富含Ge層成長在Si表面上時，其不會成長在如氧化矽(SiO2)或氮化矽(SiN)之絕緣表面上；也不會成長在，例如，在n型區之暴露的重磷摻雜的矽上。
本文所提供的技術可以用來改善在任何數目 的電晶體結構和配置之裝置電阻，包括平面、齊平的或凸起的源極/汲極、非平面(即，奈米線電晶體以及如雙閘極和三閘極電晶體結構之鰭片式電晶體)、還有應力和無應力通道結構。源極/汲極區可以被凹入(即，使用蝕刻製程)或無凹入(即，形成在基板的頂表面上)。此外，電晶體裝置可選擇性的包括被設計之源極和汲極尖端區，例如，以降低電晶體之整體電阻同時改善短通道效應(short channel effects，SCE)，但這種尖端區不是必需的。電晶體裝置可更包括任何數目的閘極配置，如多晶閘極(poly gates)、高k介電質(high-k dielectric)金屬閘極、取代金屬閘極(replacement metal gate，RMG)製 程閘極或任何其他閘極結構。任何數目的結構特徵可以配合使用如本文所述之低電阻電晶體技術。
經分析(即，使用掃描/穿透式電子顯微鏡(scanning/transmission electron microscopy，SEM/TEM)及/或組合物映射)，根據一個或多個實施方式配置之結構將有效地顯示包括沉積在Si表面(即，Si基板的表面或Si披覆層的表面)上之富含Ge層的接觸區。此外，當在積體電路上之此種結構可以比作不具有接觸之積體電路上的源極/汲極區。在這種無接觸源極/汲極區中(即，源極/汲極區在用於接觸處理之接觸溝渠蝕刻過程中是不開放)，SiGe層可存在於如本文所述之源極/汲極位置中。例如，在SiGe層的用意為在後續接觸處理為犧牲的情形下，該SiGe層可包含15-30%的鍺且可為未摻雜。在SiGe層的用意為在後續接觸處理為功能性的情形下，該SiGe層可包含30-70%的鍺且可為p型摻雜(即，摻雜B)。此外，在此種情形下，SiGe層可包括Si披覆層。此外，在一些情形下，使用如本文各種敘述之技術製造的電晶體可以提供相對於傳統結構的改善，至少，降低接觸電阻(即，導致於給定操作電壓，20-30%之電流流動改善)。此外，介於富含Ge層和富含Ge層直接地沉積的Si表面之間的介面(即，相較於介於富含Ge層和SiGe表面之間的介面)的潔淨度，例如，可藉由二次離子光譜儀(secondary ion mass spectrometry，SIMS)或離子探針偵測。鑒於本發明，無數的配置及變化將是顯而易 見。
架構和方法
第1圖及第1’圖為根據本發明一個或多個實施方式之形成包括沉積在Si上之富含Ge源極/汲極接觸層之電晶體的方法。第2A-H’圖根據本發明各種實施方式繪示當執行第1圖或第1’圖任一個用於平面或非平面電晶體架構的方法時之範例結構。如鑒於本發明將顯而易見，用於非平面電晶體架構，如鰭片示架構(即，三閘極或鰭片式電晶體(finFET))，第2A-H’圖可描述沿半導體鰭片長度截取的剖視圖。顯示於第1圖及第1’圖之範例方法包括形成一個或多個閘極堆疊在一個或多個電晶體裝置(即，MOS裝置)可形成在其上的半導體基板上，該閘極堆疊被形成在通道區之上且具有鄰近通道區的源極/汲極區。該MOS裝置可包含，例如，p-MOS電晶體，或n-MOS電晶體和p-MOS電晶體兩者(即，CMOS裝置)。
第1圖顯示根據本發明一些實施方式之沉積在去除犧牲的SiGe層之後執行接觸溝渠蝕刻之後之Si基板的表面上之形成包括富含Ge源極/汲極層之電晶體的方法。第1’圖顯示根據本發明一些實施方式之沉積在接觸溝渠蝕刻之後之Si披覆層上之形成包括富含Ge源極/汲極層之電晶體的方法，其中Si披覆層沉積在功能的p型SiGe層上。因此，在一些實施方式中，SiGe層將沉積在源極/汲極區中作為犧牲層，而在其他實施方式中，SiGe 層將沉積在源極/汲極區中作為功能層。SiGe層的特性(即，%鍺摻雜量等等)可取決於SiGe層被用作犧牲層(即，如在第1圖的方法之情形下)或被用作功能性源極/汲極層(即，如在第1’圖的方法之情形下)，當根據本發明將顯而易見。
如可從第1圖和第1’圖看出，該範例方法包 括在半導體基板上執行102淺溝渠絕緣(shallow trench isolation，STI)。基板可使用矽基座或基板形成，如矽單晶晶圓(silicon single crystal wafer)。基板可由，例如，大塊(bulk)矽、絕緣層上矽晶(silicon-on-insulator，SOI)配置或包括那些基板上其中單一組成物鰭片或具有不同組成物用於製造奈米線/奈米帶形成在後續閘極圖形化製程之前的多層結構實現。在其他實施中，半導體基板可使用替代的材料，其可以或可以不與矽結合，如鍺來形成。在更廣泛的意義中，可使用根據本發明之實施方式之任何可在半導體裝置可被建立之上方作為基礎的材料。STI製程可包括圖形化擴散區、蝕刻STI溝渠、沉積絕緣體或氧化物或層間介電質(inter-layer dielectric，ILD)材料，以及研磨沉積的STI材料。在一些情形下，如用於非平面架構，STI製程可包括凹陷STI材料。在一些情形下，如用於平面架構，擴散區的平面與STI頂部(即，約在10nm)可在名義上為平面。在非平面架構的情形下，如那些使用鰭片式或奈米線/奈米帶電晶體裝置，STI位置可為其中擴散被定義為接著製造以滲 出STI材料之平面的窄結構(即，擴散水平為10nm或水平以上之STI平面)。注意在其他實施方式中，絕緣之其他合適形式(STI以外)可以被使用以分離在半導體基板上之擴散區。
第1圖和第1’圖的方法繼續在半導體基板上 形成104閘極或閘極堆疊。閘極或閘極堆疊可形成為如現有技術那樣，或使用任何合適的習用技術。在一些實施方式中，閘極堆疊可藉由沉積而形成以及接著圖形化閘極介電層和閘極電極層。例如，閘極介電層可使用如化學氣相沉積(chemical vapor deposition，CVD)、原子層沉積(atomic layer deposition，ALD)、塗佈沉積(spin-on deposition，SOD)或物理氣相沉積(physical vapor deposition，PVD)之習知沉積製程來整片沉積(blanket deposition)在基板上。替代的沉積技術也可被使用，例如，熱生長閘極介電層。例如，閘極介電層可從如二氧化矽或高k介電質材料之材料形成。例如，高k介電質材料的範例包括氧化鉿、氧化鉿矽、氧化鑭、氧化鑭鋁、氧化鋯、氧化鋯矽、氧化鉭、氧化鈦、氧化鋇鍶鈦、氧化鋇鈦、氧化鍶鈦、氧化釔、氧化鋁、氧化鉛鈧鉭和鈮酸鉛鋅。在一些範例實施方式中，虛設(dummy)或高k閘極介電層可以是大約5Å至大約200Å厚之間(即，20Å至50Å)。在一般情況下，閘極介電層之厚度應足以將閘極電極與鄰近源極和汲極接觸電性隔離。在進一步的實施方式中，附加的處理可在高k閘極介電層上執行，如退火製 程以改善高k材料的品質。
閘極電極材料可接著使用如前面所述之相同 的沉積技術，如：ALD、CVD或PVD，沉積在閘極介電層。在一些這種具體實施方式中，閘極電極材料可為多晶矽或金屬層，但也可使用其他合適的閘極電極材料。閘極電極材料，其可以為犧牲或虛設的材料在稍後用於取代閘極製程去除，如取代金屬閘極(replacement metal gate，RMG)製程，在一些範例實施方式中，可具有之厚度的範圍為50Å至500Å(即，100Å)。RMG製程將在下面詳細的討論。使用閘極首先/閘極最後、RMG或習知的SiO2/多晶閘極都與本發明兼容的。
第1圖和第1’圖的方法繼續蝕刻106電晶體 結構的源極/汲極區以形成源極/汲極凹洞。蝕刻106以形成源極/汲極凹洞可以執行如習知做法或使用任何數目的合適的製程。在一些範例情形下，其包括離子佈植(ion implantation)至基板鄰近於閘極堆疊的高摻雜部分，接著藉由退火驅動摻雜劑進一步進入基板以改善預期的源極/汲極區之蝕刻速率。乾式蝕刻製程可接著被使用以蝕刻基板的摻雜區以形成源極/汲極凹洞和，在一些情形下，相應的尖端區。在乾式蝕刻完成之後，濕式蝕刻可被使用，例如，以清潔以及進一步蝕刻該區。此種濕式蝕刻(可使用習知或常規的濕式蝕刻化學進行)，可被使用來去除如碳、氟、氟氯碳化物和如氧化矽之氧化物的汙染物以提供一個乾淨的表面使後續製程可以進行。此外，假設 一個單晶矽基板，該濕式蝕刻也可以用於去除基板沿著<111>和<001>結晶形(crystallographic)平面的薄部分以提供一個平滑的表面，其上可發生高品質磊晶(epitaxial)沉積。在一些範例情形下，基板的較薄部分被被蝕刻掉，例如，多達5nm厚且也去除殘餘的汙染物。將可理解的，在一些實施方式中，源極/汲極區不需要凹陷或其它蝕刻。在此種情形下，源極/汲極材料可被形成在半導體基板上而不需任何蝕刻。
第2A圖顯示如前面各種敘述之在基板200上 執行102 STI、在通道區上形成104閘極堆疊(閘極堆疊包括閘極介電層202、閘極電極層204及選擇性硬遮罩206)以及蝕刻106源極/汲極凹洞212/214之後的範例所得結構。該選擇性閘極硬遮罩206可被使用以提供其他益處或使用於處理中，如保護閘極電極204免於後續蝕刻和/或離子佈植製程。硬遮罩206可使用典型硬遮罩材料形成，如二氧化矽、氮化矽和/或其他習知的絕緣材料。
如第2A圖可以看出，間隔物208被形成在分 別鄰近閘極堆疊和包括選擇性尖端區212A/214A之源極/汲極凹洞212/214。間隔物208可使用，例如，氧化矽、氮化矽或其他合適的間隔物材料的習知材料形成。間隔物208的寬度通常可以根據用於形成電晶體之設計需求而選擇。源極/汲極凹洞212/214有效地定義源極/汲極區的位置，在這範例實施方式中，以及，如可以看出，源極/汲極凹洞尖端區212A/214A底切閘極介電質302。
第1圖的方法繼續分別沉積108犧牲的SiGe 層218/220在源極/汲極凹洞212/214，以成長回源極/汲極區，如第2B圖中所示之所得結構，根據本發明一實施方式。回想在第1圖之方法，SiGe層預期作為一個犧牲層在後續處理被去除以暴露Si基板的表面，如將在本文中討論。在其中SiGe層為犧牲的實施方式中，一些情形下，SiGe層可包含15-30%的鍺。雖然，在一些情況下，犧牲層可為10%的鍺至純鍺。此外，犧牲的SiGe層，在一些情形下，也可為未摻雜。雖然，在其他情形下，犧牲層可具有一些數量的p型摻雜。
在第1’圖的方法，SiGe層218’/220’(如第 2B’圖中所示之沉積108’在源極/汲極凹洞212/214內)預期作為一個功能的源極/汲極層。在此種實施方式中，功能的SiGe層可包含30-70%的鍺，在一些情形下(即，因效能理由以最大化應力)。此外，在此種實施方式中，SiGe層為p型摻雜(即，摻雜B)，因為其為功能的源極/汲極層(而不是作為後續被去除的犧牲層)。例如，B濃度可以超過1E20 cm-3或任何其他合適的濃度已允許SiGe層218’/220’為用於p型MOS裝置之功能層。第1’圖的方法繼續沉積109Si披覆層在源極/汲極位置之SiGe層218’/220’上，以形成第2B’圖所示之所得範例結構。
沉積108、108’及109可以被進行，例如，使用選擇性磊晶沉積，但任何合適的沉積製程都可以使用。例如，沉積108和109可以在CVD反應器、LPCVD反應 器或超真空CVD(ultra-high vacuum CVD，UHCVD)中進行。在一些範例情形下，反應器溫度可能落在，例如，介於600℃至800℃之間且反應器壓力可能落在，例如，介於1至760Torr之間。載體氣體(carrier gas)可包括，例如，氫或氦以合適的流速，如介於10至50SLM之間。在一些範例情形下，蝕刻劑可被加入以增加沉積的選擇性。例如，HCl或Cl2可被加入在流速範圍，例如，介於50至300SCCM之間。在p型摻雜的情形下(即，其中SiGe層218’/220’為p型摻雜)，可使用硼之原位(in-situ)摻雜、稀釋B2H6(即，B2H6可在H2下被稀釋至1-20%)。例如，稀釋的B2H6可為3%濃度且以流速範圍介於10至100SCCM之間被使用。在一些情形下，沉積根據材料和/或p型摻雜劑的濃度可為漸變沉積。也可使用其他合適的沉積技術，當根據本發明將顯而易見。
第1圖和第1’圖的方法繼續沉積110絕緣層 230以及接著研磨/平坦化如常見的做法以形成第2C圖所示的結構。注意在第1’圖的情形下，披覆層222將顯示於功能的SiGe層218’/220’之頂部。絕緣層230可使用已知適用於電晶體之絕緣層和積體電路結構的材料，如低k(low-k)介電質(絕緣體)材料來形成。此種絕緣體材料包括，例如，如二氧化矽(SiO2)的氧化物、碳摻雜氧化物(carbon doped oxide，CDO)、氮化矽、如全氟環丁烷或聚四氟乙烯之有機聚合物、氟矽酸鹽玻璃(FSG)以及如倍半矽氧烷(silsesquioxane)、矽氧烷(siloxane) 或有機矽酸鹽(organosilicate)玻璃之有機矽酸鹽。在一些範例配置中，絕緣層可包括孔或其他空洞已進一步降低其介電常數。
第1圖和第1’圖的方法可選擇性的繼續使 用，例如，RMG製程，去除和取代112閘極堆疊，以形成如第2D圖所示之範例所得閘極結構。在這種選擇性情形下，該方法可包括使用如習知做法之蝕刻製程去除閘極堆疊(包括高k閘極介電層202、犧牲/虛設的閘極電極204及硬遮罩層206)。在替代的實施例中，只有犧牲/虛設的閘極電極204(和硬遮罩層206)被去除。假如閘極介電質202被去除，該方法可包括沉積新的閘極介電層進入溝渠開口。任何如前面所述之合適的高k介電材料可在此處使用，如氧化鉿。相同的沉積製程也可被使用。閘極介電質202的取代可被使用，例如，以處理任何在乾式和濕式蝕刻製程之應用中可能發生在原本閘極介電層之損害，和/或以高k或其他所需的閘極介電材料取代低k或犧牲介電材料。該方法可接著繼續沉積金屬閘極電極進入溝渠且在閘極介電層上。習知金屬沉積製程可被使用以形成金屬閘極電極層，如CVD、ALD、PVD、無電電鍍(electroless plating)或電鍍(electroplating)。金屬閘極電極層可包括，例如，p型功函數金屬，如釕、鈀、鉑、鈷、鎳以及如氧化釕的導電金屬氧化物。在一些範例配置中，兩個或多個金屬閘極電極層可被沉積。例如，功函數金屬可接著如鋁之合適的金屬閘極電極填充金屬被沉 積。第2D圖根據一實施方式繪示已經被沉積進入溝渠開口之範例高k閘極介電層203和金屬閘極電極205。注意此種RMG製程可在第1圖和第1’圖之方法中不同時間點進行，如果需要的話。
第1圖和第1’圖的方法可選擇性的繼續如習 知做法遮蔽114n型(即，n-MOS)源極/汲極區(假如存在)以允許接觸圖形化從而從n接觸分離以打開p接觸。 在此種情形下，遮蔽114n型區以在後續p接觸處理中保護它們。這也可提供益處，當n接觸獨立的打開，n型特定的金屬可被使用於降低接觸電阻之原因。此外，可接收的附加益處為p和n接觸金屬不具有被連結的結果，如在習知接觸處理。遮蔽114可被使用於旨在作為具有n-MOS和p-MOS電晶體兩者之CMOS裝置。
第1圖的方法繼續蝕刻116以形成如第2E圖 所示之範例所得結構之源極/汲極接觸溝渠240。也可以看出，由於執行接觸溝渠蝕刻116SiGe層218/220於附加的處理再次暴露。因為SiGe層218/220在第1圖之範例方法為犧牲的，可使用任何合適的乾式和/或濕式蝕刻製程。回想在其中n接觸區被遮蔽114的選擇性情形下，只有p接觸區可在接觸溝渠蝕刻116中再次暴露。
第1’圖的方法繼續蝕刻116’以形成如第2E’ 圖所示之範例所得結構之源極/汲極接觸溝渠240’。也可以看出，由於執行接觸溝渠蝕刻116’Si披覆層222於附加的處理再次暴露。在這範例方法中，可執行接觸溝渠蝕 刻116’從而於後續沉積保留Si披覆層222。在此種情形下，蝕刻阻擋層可被使用以幫助保留Si披覆層222且蝕刻阻擋層(其可以是氮化物、碳化物或任何具有足夠不同於絕緣層230之蝕刻速率的其他材料)可在沉積110絕緣層230之前被沉積。因此，當在其中使用蝕刻阻擋層的情形執行接觸溝渠蝕刻116’時，第一蝕刻可被執行以從p接觸區去除絕緣層230，但有效的停止在蝕刻阻擋層，且接著第二蝕刻可被執行以去除蝕刻阻擋層，但有效的停止在Si披覆層222。
第1圖的方法繼續蝕刻117以從源極/汲極區 去除犧牲的SiGe層218/220，而形成第2F圖所示之範例所得結構。如第2F圖可以看出，再次形成之源極/汲極凹洞212/214可以為如第2A圖所示之源極/汲極凹洞的相同凹洞，或相似。SiGe層218/220(在這實施方式中為犧牲層)可使用選擇對Si和絕緣材料的蝕刻117而被去除(即，它將有效地不去除Si或絕緣材料，或以相比於去除SiGe層218/220的速率更慢的速率去除它們)。此種選擇性蝕刻可包括，例如，包括水、硝酸、有機酸(如，乙酸或檸檬酸)和/或氫氟酸的濕式蝕刻，且該選擇性蝕刻可具有，例如，約300Å/min的可用蝕刻速率。
第1圖和第1’圖的方法繼續在Si表面上之源 極/汲極區沉積p型富含Ge層材料。在第1圖之方法的情形下，富含Ge層224/226沉積在Si基板200的表面上，如第2G圖所示之範例所得結構。在第1’圖之方法的情形 下，富含Ge層224’/226’沉積在Si披覆層222的表面上，如第2G’圖所示之範例所得結構。沉積118可被執行如各種本文所述(即，使用所討論有編號的技術來沉積108和109，或任何其他合適的沉積技術)。在一些範例情形下，沉積118可執行，例如，包括最高溫為550或500度C的製程。在此種情形下，該處理的熱預算限制(thermal budget constraints)可取決於使用於在上述之選擇性RMG製程中的閘極電極的金屬閘極材料。在一些範例情形下，蝕刻117以去除犧牲的SiGe層及沉積118富含Ge層可於原位或沒有空斷(air break)被執行。
在一些實施方式中，富含Ge層材料可包含至 少50%的鍺，因此，富含Ge層可包含鍺的範圍為50-100%。在一些實施方式中，富含Ge層可包括Si(如，SiGe)且可包含鍺的範圍為50-99%。在一些實施方式中，富含Ge層可包括錫(Sn)(如，GeSn)，最多15%的Sn。在一些此種實施方式中，富含Ge層可包括微量級(trace levels)的Si(如，<5%)。回想富含Ge層為p型層且因此為p型摻雜(如，摻雜B)。在一些情形下，p型富含Ge層可為以約2E20 cm-3水平之B摻雜。雖然，在一些情形下，p型富含Ge層可為以約超過5E19 cm-3及最高為5E21 cm-3水平之B摻雜，在一些範例情形下。
第1圖和第1’圖的方法可接著繼續沉積120 源極/汲極金屬接觸插塞(contact plugs)250，導致如第 2H圖和第2H’圖所示之範例結構。在一些實施方式中源極/汲極金屬接觸插塞250可包括鋁或鎢，但任何合適的導電接觸金屬或合金都可以使用，如銀、鎳-鉑或鎳-鋁或鎳和鋁的其它合金、或鈦，使用習知的沉積製程。源極/汲極接觸的金屬化可被進行，例如，使用鍺化(germanidation)製程(通常，沉積接觸金屬及後續的退火)。例如，鍺化鎳、鋁、鎳-鉑或鎳-鋁或鎳和鋁的其它合金或具有或不具有鍺前非晶化植入物的鈦可被使用以形成低電阻鍺。富含Ge層可允許金屬-鍺的形成(即，鎳-鍺)，當根據本發明將顯而易見。
鍺化製程也可允許顯著地降低蕭特基-障礙高 度(Schottky-barrier height)且比習知金屬-矽化物系統改善了接觸電阻。例如，習知電晶體一般使用具有鍺濃度範圍為30-40%之源極/汲極SiGe磊晶(epi)製程。此種習知系統表現出的外部電阻值約為140Ohm-um，受到epi/矽化物介面電阻限制，其值較高且可能妨礙未來閘極間距的尺度。本發明一些實施方式允許p-MOS裝置之外部電阻顯著地改善(即，於給定電壓下產生20-30%電流流動的改善)，其可以更佳地支持p-MOS裝置的尺度。因此，如本文各種敘述之具有包括富含Ge層直接沉積在Si表面上的源極/汲極區之電晶體，相較於習知電晶體可表現出相對較低的外部電阻值(即，較低的接觸電阻)。
非平面配置
一種非平面架構可以被實現，例如，使用鰭 片式或奈米線/奈米帶配置。鰭片式電晶體被建立以圍繞薄帶的半導體材料(一般稱為鰭片)。該電晶體包括標準的場效電晶體(field effect transistor，FET)節點，包括閘極、閘極介電質、源極區及汲極區。該裝置的導電通道位於閘極介電質下方之鰭片之外側上/範圍內。具體地，電流沿著鰭片之兩側壁(垂直於基板表面側)以及沿著鰭片之頂部(平行於基板表面側)流動。因為此種配置的導電通道實質上位於沿著三個不同鰭片的外部平面區，此種鰭片式設計有時被稱為三閘或finFET配置。其他類型的鰭片式配置也可用，如所謂的雙閘極的finFETs，其中導電的通道主要只位於沿著鰭片的兩個側壁(而不是沿著鰭片的頂部)。
第1圖和第1’圖的方法可以應用於非平面電 晶體架構。第3A-3J’圖根據本發明一些實施方式繪示作為用於非平面電晶體架構所執行的(第1個或第1’圖的)方法之範例結構。以上相對於第1-1’及2A-H’圖之先前的討論將可理解的同樣地適用於此處。為了便於說明，類似的編號被使用來辨識在第3A-3J’圖之特徵也被使用於第2A-H’圖，除了第3A-3J’圖包括300系列的編號，而第2A-H’圖包括200系列的編號(如，基板200類似於基板300，閘極電極204類似於閘極電極304等等)。如在第3A圖中可以看出，所示的非平面配置實施具有鰭片式結構，其包括基板300及從基板沿伸通過STI/絕緣層301之鰭片 310。
第3A圖顯示在基板300上執行102 STI後所得的結構，在此範例情形下，包括凹陷STI材料以形成鰭片310。第3B圖顯示第3A圖在形成104閘極堆疊(包括虛設閘極電極304及選擇性的虛設閘極介電質)後的結構，在該範例實施方式中是一個虛設/犧牲閘極堆疊(然而，不一定是這種情形)。注意在此實施方是中間隔物308也形成在閘極堆疊上，這可能使用如上所述之間隔物沉積和蝕刻形成。第3C圖顯示第3B圖在蝕刻106源極/汲極區312/314後的結構。第3D圖顯示第3C圖在沉積108犧牲的SiGe層318/320後的結構。第3D’圖顯示第3C圖在沉積108’功能的SiGe層318’/320’及Si披覆層322後的結構。該犧牲的和功能的SiGe層以及此種層的沉積，已在上面討論
第3E圖顯示第3D圖在沉積110絕緣層330後的結構。第3F圖顯示第3E圖在去除112虛設的閘極堆疊(包括虛設閘極電極304)後再次暴露通道區309的結構。第3G圖顯示第3F圖在新的閘極堆疊(即，具有新的閘極介電質和金屬閘極電極305)取代112虛設閘極堆疊後的結構。注意在一些實施方式中，去除/取代112閘極堆疊可為如前面描述之選擇性的製程。第3H圖顯示第3G圖在執行116用以從將成為p接觸之區域去除絕緣層330之接觸溝渠蝕刻後的結構。第3H圖也顯示選擇性硬遮罩360在閘極堆疊上。注意選擇性遮蔽法遮蔽114n接 觸區(如果存在)可在接觸溝渠蝕刻116之前已被執行，用以僅打開p接觸區。還要注意的是Si披覆層322將被顯示在第3E-H圖之其包括功能的SiGe層318’/320’的實施方式，當根據本發明將顯而易見。
第3I圖顯示第3H圖在從源極/汲極區蝕刻 117去除SiGe層318/320及形成源極/汲極凹洞312/314後的結構。如可在第3I圖看出，再形成之源極/汲極凹洞312/314可為相同的凹洞如，或相似於，第3C圖所示之源極/汲極凹洞。第3J圖顯示第3I圖在沉積118p型富含Ge層324/326後的結構。第3J’圖顯示在p型富含Ge層324’/326’已被沉積在Si披覆層322上(在接觸溝渠蝕刻116’被執行後)之後所得的結構。在此實施方式中，SiGe層318’/320’為如前所述之功能的p型層。金屬插塞(未圖示)可接著沉積120在第3J/J’圖之源極/汲極區中，如本文所述，以提供用於鰭片式p型MOS裝置的接觸。由於佈局和設計規則，將有一些沒有接觸溝渠或金屬插塞不主動電晶體的群體。這些虛設的裝置在產線的最後將保留原先沉積的源極/汲極材料。
例如，用於這些虛設的裝置，如本文各種敘 述的SiGe層(無論犧牲的或功能的及披覆Si層)可存在於源極/汲極區，且沉積在本文各種描述之源極/汲極接觸溝渠蝕刻之後的p型富含Ge層將不存在。
如將進一步理解的，注意一種替代所示的鰭片式非平面配置的是雙閘極架構，其將包括在鰭片310頂 部上的介電質/絕緣層。此外注意任何層(包括SiGe層318/320和318’/320’、Si披覆層322以及富含Ge層324/326和324’/326’)的範例形狀不是用來限制本發明的任何特定的源極/汲極的類型或形成製程，且其他形狀根據本發明將顯而易見(即，圓形、方形或矩型區可被實施)。
第4圖及第4’圖顯示根據本發明一些實施方 式形成之奈米線電晶體結構之透視圖。奈米線電晶體(一些時候被稱為閘極環繞(gate-all-around)FET)被相似的配製程鰭片基(fin-based)電晶體，但代替鰭片，奈米線被使用且閘極材料通常圍繞通道區的所有側。根據具體的設計，一些奈米線電晶體具有，例如，四個有效閘極。可以看出，第4圖顯示具有犧牲的SiGe層而形成的奈米線電晶體結構及第4’圖顯示具有功能的SiGe層而形成的奈米線電晶體結構，如本文各種的描述。第4圖及第4’圖繪示具有兩奈米線410的奈米線通道架構，但其他實施方式可具有任何數目的線。該奈米線410可以，例如，用p型通道矽或鍺或SiGe奈米線而被實現。就像在第3J圖中所示之鰭片的配置，第4圖中所示之奈米線配置包括富含Ge層424/426沉積在Si基板400上之源極/汲極區中。而且就像在第3J’圖所示之鰭片的配置，第4’圖中所示之奈米線架構包括富含Ge層424’/426’沉積在Si披覆層422(其被沉積在功能的p型SiGe層418’/420’上)。
範例系統
第5圖根據本發明一個或多個實施方式繪示之實現具有一個或多個電晶體配置之運算系統1000。可以看出，運算系統1000容納一母板1002。母板1002可以包括多個組件，包括，但不限制於一處理器1004以及至少一通訊晶片1006，其各者都可以物理和電性耦合至母板1002，或以其它方式在此整合。如將理解的，母板1002可為，例如，任何印刷電路板，無論是主板、安裝在主板的子板或系統1000的唯一板等等。
根據其應用，運算系統1000可以包括一個或多個其它組件透過或沒透過物理和電性耦合至母板1002。這些其它組件包括，但不限制於，揮發性記憶體(例如：DRAM)、非揮發性記憶體(即，ROM)、圖形處理器(graphics processor)、數位訊號處理器(digital signal processor)、密碼處理器(crypto processor)、晶片組(chipset)、天線(antenna)、顯示器(display)、觸控螢幕顯示器(touchscreen display)、觸控螢幕控制器(touchscreen controller)、電池(battery)、音頻編解碼器(audio codec)、視頻編解碼器(video codec)、功率放大器(power amplifier)、全球定位系統(global positioning system，GPS)裝置，羅盤(campass)、加速度計(accelerometer)、陀螺儀(gyroscope)、揚聲器(speaker)、相機(camera)、以及大容量存儲裝置(mass storage device)(例如：硬 碟機(hard disk drive)、光碟(compact disk，CD)、數位影音光碟(digital versatile disk，DVD)等等)。任何包括在運算系統1000內之組件可包括根據本文各種敘述之一個或多個半導體裝置結構(如，包括具有富含Ge層直接沉積在Si表面上之源極/汲極區之p-MOS電晶體裝置)。這些電晶體結構可以被使用，例如，以實現電路板上處理器快取(cache)或記憶體陣列(memory array)。 在一些實施方式中，多項功能可以被整合於一個或多個晶片(如，例如，注意通訊晶片1006可以是部分或以其它方式整合到處理器1004)。
通訊晶片1006實現無線通訊用於傳送資料到運算系統1000和從運算系統1000傳送資料。用語"無線"及其衍生用於描述電路、裝置、系統、方法、技術、通訊通道等等，其可以透過使用調變電磁波於非固體介質通訊資料。該用語不是暗示相關裝置不包含有線，儘管一些實施方式可能沒有包含有線。通訊晶片1006可以實現任何數目的無線標準或協議，包括但不限制於Wi-Fi(IEEE802.11系列)、WiMAX(IEEE802.16系列)、IEEE 802.20、長期演進(long term evolution，LTE)、EV-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽(Bluetooth)、它們的衍生物、以及被指定為3G、4G、5G和超越任何其它無線協議。運算系統1000可包括複數個通訊晶片1006。例如，第一通訊晶片1006可專用於短距離無線通訊例如 NFC、Wi-Fi和藍芽以及一第二通訊晶片1006可專用於長範圍的無線通訊如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO、和其它。
運算系統1000的處理器1004包括積體電路 晶粒封裝在處理器1004內。一些實施例中，處理器之積體電路晶粒包括實施一個或多個本文各種敘述之電晶體結構之板上記憶體電路。用語"處理器"可以指任何裝置或裝置的一部分用來處理，例如，來自暫存器及/或記憶體電子資料，轉換該電子資料成可儲存於暫存器及/或記憶體的其它電子資料。
通訊晶片1006也可以包括積體電路晶粒封裝 在通訊晶片1006內。根據一些這種範例實施方式，通訊晶片之積體電路晶粒包括實施一個或多個實現一個或多個本文各種敘述之電晶體結構之裝置(即，晶片上處理器或記憶體)。當根據本發明將顯而易見，需要注意的是多標準無線能力可以直接整合至處理器1004(即，其中任何晶片1006的功能整合至處理器1004，而不是具有分開的通信晶片)。此外需要注意的是處理器1004可為具有這種無線能力的晶片組。簡言之，可以使用任何數目的處理器1004及/或通訊晶片1006。同樣地，任何晶片或晶片組可具有多功能整合於其中。
在各種實施中，運算系統1000可以為膝上型 電腦(laptop)、簡易筆記型電腦(netbook)、筆記型電腦(notebook)、智慧型手機(smartphone)、平板電腦 (tablet)、個人數位助理(personal digital assistant，PDA)、超級行動個人電腦(ultra mobile PC)、行動電話(mobile phone)、桌上型電腦(desktop computer)、伺服器(server)、印表機(printer)、掃描器(scanner)、螢幕(monitor)、機頂盒(set-top box)、娛樂控制單元(entertainment control unit)、數位相機(digital camera)、隨身音樂撥放器(portable music player)或數位錄影機(digital video recorder)。在進一步實施中，系統1000可為用於處理資料或採用本文各種敘述之一個或多個電晶體裝置之任何其他電子裝置。
進一步範例實施方式
下面範例屬於進一步實施方式，從中眾多排列和配置將是顯而易見的。
範例1為一種電晶體裝置，包含：具有通道區的基板；在該通道區上方的閘極電極；以及形成在該基板上和/或內且鄰近於該通道區的源極/汲極區，該源極/汲極區的各者包含p型富含鍺(Ge)層直接沉積在矽(Si)表面上，其中該p型富含Ge層包含至少50%的鍺。
範例2包括範例1之主體，其中在該源極/汲極區之該Si表面為該基板的表面。
範例3包括範例1之主體，其中在該源極/汲極區之該Si表面為沉積在p型矽化鍺(SiGe)層上之Si披覆層的表面。
範例4包括範例3之主體，其中該p型SiGe層包含30-70%的鍺。
範例5包括範例1-4任何一個之主體，其中該p型富含Ge層包含矽化鍺(SiGe)層。
範例6包括範例1-4任何一個之主體，其中該p型富含Ge層包含可達15%的錫之鍺化錫(GeSn)。
範例7包括範例6之主體，其中該p型富含Ge層更包含可達5%的矽。
範例8包括範例1-7任何一個之主體，其中該p型富含Ge層為高於1E20 cm-3水平之摻雜硼(B)。
範例9包括範例1-8任何一個之主體，其中該Si表面為未摻雜或具有低於1E19 cm-3摻雜水平。
範例10包括範例1-9任何一個之主體，更包含金屬-鍺源極/汲極接觸。
範例11包括一種包含n-MOS裝置以及範例1-10任何一個之主體的CMOS裝置。
範例12包括範例1-11任何一個之主體，其中該裝置具有平面式、鰭片式、奈米線或奈米帶配置。
範例13包括一種包含如範例1-12任何一個之主體的積體電路。
範例14包括範例13之主體，更包含附加源極/汲極區，其中該附加源極/汲極區缺少金屬接觸且包含矽化鍺(SiGe)層。
範例15包括範例14之主體，其中該SiGe層 包含15-30%的鍺且為未摻雜。
範例16包括範例14之主體，更包含沉積在 該SiGe層上之Si披覆層，其中該SiGe層包含30-70%的鍺且為p型摻雜。
範例17包括範例1-16任何一個之主體的運 算系統。
範例18為一種形成電晶體裝置的方法，該方 法包含：在具有通道區之矽(Si)基板上執行淺溝渠絕緣(STI)；在該通道區上形成閘極堆疊；在鄰近於該通道區之源極/汲極區中沉積犧牲的矽化鍺(SiGe)層；在該閘極堆疊及源極/汲極區之表面形貌上沉積絕緣材料；執行源極/汲極接觸溝渠蝕刻；從該源極/汲極接觸溝渠蝕刻以去除該犧牲的SiGe層且再次暴露該Si基板的表面；以及在該Si基板之該再次暴露表面上該源極/汲極接觸溝渠中沉積p型富含鍺(Ge)層，其中該p型富含Ge層包含50%的鍺。
範例19包括範例18之主體，更包含執行閘 極取代製程用以在沉積絕緣材料在該閘極堆疊及該源極/汲極區之表面形貌上之後取代該閘極堆疊。
範例20包括範例18-19任何一個之主體，更 包含在執行用以僅暴露p接觸區的源極/汲極接觸溝渠蝕刻之前遮蔽n型區。
範例21包括範例18-20任何一個之主體，更 包含沉積金屬源極/汲極接觸在p型富含Ge層上。
範例22包括範例18-21任何一個之主體，其 中該p型富含Ge層沉積於低於500℃的溫度。
範例23包括範例18-22任何一個之主體，其 中用以去除該犧牲的SiGe層的蝕刻包括使用選擇性的對矽(Si)和絕緣體材料的SiGe蝕刻。
範例24包括範例18-23任何一個之主體，其 中用以去除該犧牲的SiGe層的蝕刻為包括水、硝酸、有機酸和/或氫氟酸的濕式蝕刻。
範例25包括範例18-24任何一個之主體，其 中該電晶體裝置為p-MOS或CMOS裝置。
範例26包括範例18-25任何一個之主體，其 中該裝置具有平面式、鰭片式、奈米線或奈米帶配置。
範例27包括範例18-26任何一個之主體，其 中該SiGe層包含15-30%的鍺且為未摻雜。
範例28包括範例18-27任何一個之主體，其 中該p型富含Ge層包含矽化鍺(SiGe)層。
範例29包括範例18-27任何一個之主體，其 中該p型富含Ge層包含可達15%的錫之鍺化錫(GeSn)。
範例30包括範例29之主體，其中該p型富 含Ge層更包含可達5%的矽。
範例31包括範例18-30任何一個之主體，其 中該p型富含Ge層為高於1E20 cm-3水平之摻雜硼(B)。
範例32為一種形成電晶體裝置的方法，該方 法包含：在具有通道區之基板上執行淺溝渠絕緣(STI)；在該通道區上形成閘極堆疊；在鄰近於該通道區之源極/汲極區中沉積p型矽化鍺(SiGe)層；在該p型SiGe層上沉積矽(Si)披覆層；在該閘極堆疊及源極/汲極區之表面形貌上沉積絕緣材料；執行源極/汲極接觸溝渠蝕刻；以及在該源極/汲極接觸溝渠中之該Si披覆層上沉積p型富含鍺(Ge)層，其中該p型富含Ge層包含50%的鍺。
範例33包括範例32任之主體，更包含執行 閘極取代製程用以在沉積絕緣材料在該閘極堆疊及該源極/汲極區之表面形貌上之後取代該閘極堆疊。
範例34包括範例32-33任何一個之主體，更 包含在執行用以僅暴露p接觸區的源極/汲極接觸溝渠蝕刻之前遮蔽n型區。
範例35包括範例32-34任何一個之主體，更 包含沉積金屬源極/汲極接觸在p型富含Ge層上。
範例36包括範例32-35任何一個之主體，其 中該p型富含Ge層沉積於低於500℃的溫度。
範例37包括範例32-36任何一個之主體，更 包含在沉積該絕緣層之前在該閘極堆疊及源極/汲極區之表面形貌上沉積蝕刻阻擋層，其中該蝕刻阻擋層在源極/汲極接觸溝渠蝕刻過程中幫忙保護該Si披覆層。
範例38包括範例37之主體，其中該蝕刻阻 擋層為氮化物或碳化物材料中的一者。
範例39包括範例32-38任何一個之主體，其 中該電晶體裝置為p-MOS或CMOS裝置。
範例40包括範例32-39任何一個之主體，其 中該裝置具有平面式、鰭片式、奈米線或奈米帶配置。
範例41包括範例32-40任何一個之主體，其 中該SiGe層包含30-70%的鍺。
範例42包括範例32-41任何一個之主體，其 中該p型富含Ge層包含矽化鍺(SiGe)。
範例43包括範例32-42任何一個之主體，其 中該p型富含Ge層包含可達15%的錫之鍺化錫(GeSn)。
範例44包括範例43之主體，其中該p型富 含Ge層更包含可達5%的矽。
範例45包括範例32-44任何一個之主體，其 中該p型富含Ge層為高於1E20 cm-3水平之摻雜硼(B)。
前述描述之範例實施方式已經呈現用於說明和描述的目的。所揭露的精確形式不是來用窮盡或限制本發明。當根據本發明時許多可行的修改及變化將顯而易見。目的是本揭露的範圍不是限制於這些詳細的描述，而是後附之申請專利範圍所界定者為準。將來早於本發明之申請可能以不同方式申請保護所揭露之主體，並且通常可包括如本文各種揭露或其他示例的任何組的一個或更多的 限制。
200‧‧‧基板
202‧‧‧閘極介電層
204‧‧‧閘極電極層
206‧‧‧硬遮罩層
224、226‧‧‧富含Ge層
230‧‧‧絕緣層
250‧‧‧源極/汲極金屬接觸插塞

Claims (25)

  1. 一種電晶體裝置，包含：具有通道區的基板；在該通道區上方的閘極電極；以及形成在該基板上和/或該基板內且鄰近於該通道區的源極/汲極區，該源極/汲極區的各者包含p型富含鍺(Ge)層直接沉積在矽(Si)表面上，其中該p型富含Ge層包含至少50%的鍺。
  2. 如申請專利範圍第1項所述之裝置，其中在該源極/汲極區之該Si表面為該基板的表面。
  3. 如申請專利範圍第1項所述之裝置，其中在該源極/汲極區之該Si表面為沉積在p型矽化鍺(SiGe)層上之Si披覆層的表面。
  4. 如申請專利範圍第3項所述之裝置，其中該p型SiGe層包含30-70%的Ge。
  5. 如申請專利範圍第1項所述之裝置，其中該p型富含Ge層包含矽化鍺(SiGe)層。
  6. 如申請專利範圍第1項所述之裝置，其中該p型富含Ge層包含可達15%的Sn之鍺化錫(GeSn)。
  7. 如申請專利範圍第6項所述之裝置，其中該p型富含Ge層更包含可達5%的Si。
  8. 如申請專利範圍第1項所述之裝置，其中該p型富含Ge層為高於1E20 cm-3水平之摻雜硼(B)。
  9. 如申請專利範圍第1項所述之裝置，其中該Si表 面為未摻雜或具有低於1E19 cm-3摻雜水平。
  10. 如申請專利範圍第1項所述之裝置，更包含金屬-鍺源極/汲極接觸。
  11. 一種CMOS裝置包含n-MOS以及申請專利範圍第1項所述之裝置。
  12. 如申請專利範圍第1項所述之裝置，其中該裝置具有平面式、鰭片式、奈米線或奈米帶配置。
  13. 一種積體電路包含如申請專利範圍第1-12項任一項所述之裝置。
  14. 如申請專利範圍第13項所述之積體電路，更包含附加源極/汲極區，其中該附加源極/汲極區缺少金屬接觸且包含矽化鍺(SiGe)層。
  15. 一種運算系統包含如申請專利範圍第1-12項任一項所述之裝置。
  16. 一種形成電晶體裝置的方法，該方法包含：在具有通道區之矽(Si)基板上執行淺溝渠絕緣(STI)；在該通道區上形成閘極堆疊；在鄰近於該通道區之源極/汲極區中沉積犧牲的矽化鍺(SiGe)層；在該閘極堆疊及源極/汲極區之表面形貌上沉積絕緣材料；執行源極/汲極接觸溝渠蝕刻；從該源極/汲極接觸溝渠蝕刻以去除該犧牲的SiGe層 且再次暴露該Si基板的表面；以及在該源極/汲極接觸溝渠中之該Si基板之該再次暴露表面上沉積p型富含鍺(Ge)層，其中該p型富含Ge層包含至少50%的Ge。
  17. 如申請專利範圍第16項所述之方法，其中該p型富含Ge層沉積於低於500℃的溫度。
  18. 如申請專利範圍第16項所述之方法，其中用以去除該犧牲的SiGe層的蝕刻包括使用選擇性的對矽(Si)和絕緣體材料的SiGe蝕刻。
  19. 如申請專利範圍第16項所述之方法，其中用以去除該犧牲的SiGe層的蝕刻為包括水、硝酸、有機酸和/或氫氟酸的濕式蝕刻。
  20. 如申請專利範圍第16-19項任一項所述之方法，其中該SiGe層包含15-30%的Ge且為未摻雜。
  21. 一種形成電晶體裝置的方法，該方法包含：在具有通道區之基板上執行淺溝渠絕緣(STI)；在該通道區上形成閘極堆疊；在鄰近於該通道區之源極/汲極區中沉積p型矽化鍺(SiGe)層；在該p型SiGe層上沉積矽(Si)披覆層；在該閘極堆疊及源極/汲極區之表面形貌上沉積絕緣材料；執行源極/汲極接觸溝渠蝕刻；以及在該源極/汲極接觸溝渠中之該Si披覆層上沉積p型 富含鍺(Ge)層，其中該p型富含Ge層包含至少50%的Ge。
  22. 如申請專利範圍第21項所述之方法，其中該p型富含Ge層沉積於低於500℃的溫度。
  23. 如申請專利範圍第21項所述之方法，更包含在沉積該絕緣層之前在該閘極堆疊及源極/汲極區之表面形貌上沉積蝕刻阻擋層，其中該蝕刻阻擋層在源極/汲極接觸溝渠蝕刻過程中幫忙保護該Si披覆層。
  24. 如申請專利範圍第23項所述之方法，其中該蝕刻阻擋層為氮化物或碳化物材料中的一者。
  25. 如申請專利範圍第21-24項中任一項所述之方法，其中該SiGe層包含30-70%的Ge。
TW104104385A 2014-03-21 2015-02-10 整合富含鍺之ｐ－ｍｏｓ源極／汲極接觸之技術 TWI673871B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/US2014/031486 WO2015142357A1 (en) 2014-03-21 2014-03-21 Techniques for integration of ge-rich p-mos source/drain contacts
??PCT/US14/31486 2014-03-21

Publications (2)

Publication Number Publication Date
TW201543676A true TW201543676A (zh) 2015-11-16
TWI673871B TWI673871B (zh) 2019-10-01

Family

ID=54145116

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104104385A TWI673871B (zh) 2014-03-21 2015-02-10 整合富含鍺之ｐ－ｍｏｓ源極／汲極接觸之技術

Country Status (6)

Country Link
US (3) US9859424B2 (zh)
EP (1) EP3120388A4 (zh)
KR (1) KR102167519B1 (zh)
CN (1) CN106062962A (zh)
TW (1) TWI673871B (zh)
WO (1) WO2015142357A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10121675B2 (en) 2016-12-29 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device and a method for fabricating the same

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015142357A1 (en) 2014-03-21 2015-09-24 Intel Corporation Techniques for integration of ge-rich p-mos source/drain contacts
US10269968B2 (en) * 2015-06-03 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
CN108028279A (zh) * 2015-09-25 2018-05-11 英特尔公司 在晶体管隔片下的电阻降低
US10978568B2 (en) 2015-09-25 2021-04-13 Intel Corporation Passivation of transistor channel region interfaces
EP3394896A4 (en) 2015-12-24 2019-12-18 Intel Corporation METHODS OF FORMING DOPED SOURCE / DRAIN CONTACTS AND STRUCTURES FORMED IN THIS WAY
US11088033B2 (en) 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
EP3312883B1 (en) * 2016-10-19 2021-12-29 IMEC vzw Semiconductor devices with increased charge carrier concentration
WO2018080513A1 (en) * 2016-10-28 2018-05-03 Intel Corporation Local interconnect for group iv source/drain regions
WO2018125035A1 (en) * 2016-12-27 2018-07-05 Intel Corporation Transistors including final source/drain material processed after replacement gate processing
US10347581B2 (en) 2017-03-22 2019-07-09 International Business Machines Corporation Contact formation in semiconductor devices
US10319722B2 (en) 2017-03-22 2019-06-11 International Business Machines Corporation Contact formation in semiconductor devices
US10692973B2 (en) 2017-04-01 2020-06-23 Intel Corporation Germanium-rich channel transistors including one or more dopant diffusion barrier elements
US20190348501A1 (en) * 2017-04-01 2019-11-14 Intel Corporation Germanium-rich channel transistors including carbon-based dopant diffusion barrier
KR102391512B1 (ko) 2017-08-17 2022-04-27 삼성전자주식회사 반도체 소자
US10164041B1 (en) * 2017-10-23 2018-12-25 Globalfoundries Inc. Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby
CN107991599B (zh) * 2017-11-24 2020-04-14 长江存储科技有限责任公司 一种用于叉指状栅goi结构漏电点精确定位的方法
US10153159B1 (en) 2017-11-30 2018-12-11 International Business Machines Corporation Source and drain formation using self-aligned processes
CN111133587A (zh) * 2017-12-26 2020-05-08 英特尔公司 用以降低锗nmos晶体管的掺杂剂扩散的非选择性外延源极/漏极沉积
US11404578B2 (en) * 2018-06-22 2022-08-02 Intel Corporation Dielectric isolation layer between a nanowire transistor and a substrate
US11374100B2 (en) * 2018-06-28 2022-06-28 Intel Corporation Source or drain structures with contact etch stop layer
US11342411B2 (en) 2018-06-29 2022-05-24 Intel Corporation Cavity spacer for nanowire transistors
US11552169B2 (en) * 2019-03-27 2023-01-10 Intel Corporation Source or drain structures with phosphorous and arsenic co-dopants
US10978344B2 (en) * 2019-08-23 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Melting laser anneal of epitaxy regions
CN111029406A (zh) * 2019-11-14 2020-04-17 中国科学院微电子研究所 一种半导体器件及其制备方法
CN114334830B (zh) * 2021-12-31 2023-09-29 无锡物联网创新中心有限公司 一种肖特基结源漏CMOS finFET及其制作方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7195969B2 (en) 2004-12-31 2007-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Strained channel CMOS device with fully silicided gate electrode
US7884002B2 (en) * 2005-11-28 2011-02-08 Nxp B.V. Method of fabricating self aligned Schottky junctions for semiconductor devices
JP2007214481A (ja) 2006-02-13 2007-08-23 Toshiba Corp 半導体装置
JP5141029B2 (ja) * 2007-02-07 2013-02-13 富士通セミコンダクター株式会社 半導体装置とその製造方法
US7544997B2 (en) * 2007-02-16 2009-06-09 Freescale Semiconductor, Inc. Multi-layer source/drain stressor
US20090302348A1 (en) 2008-06-10 2009-12-10 International Business Machines Corporation Stress enhanced transistor devices and methods of making
FR2947384B1 (fr) * 2009-06-25 2012-03-30 Commissariat Energie Atomique Procede de realisation d'un transistor a source et drain metalliques
JP2011066042A (ja) * 2009-09-15 2011-03-31 Panasonic Corp 半導体装置とその製造方法
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8901537B2 (en) * 2010-12-21 2014-12-02 Intel Corporation Transistors with high concentration of boron doped germanium
US20120205716A1 (en) * 2011-02-16 2012-08-16 International Business Machines Corporation Epitaxially Grown Extension Regions for Scaled CMOS Devices
TWI556439B (zh) 2011-12-20 2016-11-01 英特爾股份有限公司 用於ｐｍｏｓ整合之第ｉｖ族電晶體
US10535735B2 (en) * 2012-06-29 2020-01-14 Intel Corporation Contact resistance reduced P-MOS transistors employing Ge-rich contact layer
CN103594495A (zh) 2012-08-16 2014-02-19 中国科学院微电子研究所 半导体器件及其制造方法
US8710632B2 (en) * 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
US9190418B2 (en) * 2014-03-18 2015-11-17 Globalfoundries U.S. 2 Llc Junction butting in SOI transistor with embedded source/drain
WO2015142357A1 (en) 2014-03-21 2015-09-24 Intel Corporation Techniques for integration of ge-rich p-mos source/drain contacts

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10121675B2 (en) 2016-12-29 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device and a method for fabricating the same
TWI656602B (zh) * 2016-12-29 2019-04-11 台灣積體電路製造股份有限公司 半導體元件及其製造方法
US10546755B2 (en) 2016-12-29 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US10872781B2 (en) 2016-12-29 2020-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US11581193B2 (en) 2016-12-29 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same

Also Published As

Publication number Publication date
WO2015142357A1 (en) 2015-09-24
KR102167519B1 (ko) 2020-10-19
US20190109234A1 (en) 2019-04-11
US10147817B2 (en) 2018-12-04
US20170012124A1 (en) 2017-01-12
US10541334B2 (en) 2020-01-21
EP3120388A4 (en) 2017-11-29
TWI673871B (zh) 2019-10-01
US9859424B2 (en) 2018-01-02
KR20160136285A (ko) 2016-11-29
CN106062962A (zh) 2016-10-26
EP3120388A1 (en) 2017-01-25
US20180145174A1 (en) 2018-05-24

Similar Documents

Publication Publication Date Title
US10541334B2 (en) Techniques for integration of Ge-rich p-MOS source/drain
TWI742142B (zh) 用於兩側金屬化之半導體裝置的背側源極／汲極替換
KR101891458B1 (ko) Iii-v 반도체 재료 층을 갖는 반도체 디바이스
TWI643342B (zh) 用於ｐｍｏｓ整合之第ｉｖ族電晶體
KR102216424B1 (ko) 유효 게이트 길이를 증가시킴으로써 트랜지스터 채널에 걸쳐 게이트 제어를 개선하는 기술들
CN104011870B (zh) 减小的接触电阻的自对准接触金属化
US10790393B2 (en) Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning
TW201724274A (zh) 在電晶體間隔件下之電阻降低
US20230073078A1 (en) Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure
TW201824549A (zh) 在ｍｏｓ電晶體中用以降低子通道洩漏的外延緩衝
US11081570B2 (en) Transistors with lattice matched gate structure
TWI556439B (zh) 用於ｐｍｏｓ整合之第ｉｖ族電晶體
US20230037957A1 (en) Gate-to-gate isolation for stacked transistor architecture via non-selective dielectric deposition structure
TW201810612A (zh) 氮化鎵及自對齊薄體第iv族電晶體之共整合技術