TWI656602B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI656602B
TWI656602B TW106136206A TW106136206A TWI656602B TW I656602 B TWI656602 B TW I656602B TW 106136206 A TW106136206 A TW 106136206A TW 106136206 A TW106136206 A TW 106136206A TW I656602 B TWI656602 B TW I656602B
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Taiwan
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layer
source
drain epitaxial
opening
gate
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TW106136206A
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English (en)
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TW201824448A (zh
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李振銘
楊復凱
王美勻
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台灣積體電路製造股份有限公司
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Abstract

在製造半導體元件的方法中，層間介電層形成於底層結構之上。底層結構包含複數個閘極結構，各具有金屬閘極及帽蓋絕緣層配置於金屬閘極上；複數個源極/汲極磊晶層配置於兩相鄰閘極結構之間；以及蝕刻停止層覆蓋此些源極/汲極磊晶層。蝕刻以形成開口於層間介電層中。介電填充層形成於此開口中。藉由濕式蝕刻，移除配置於此些源極/汲極磊晶層上方的層間介電層。移除配置於此些源極/汲極磊晶層上的蝕刻停止層，藉此至少暴露出部分此些源極/汲極磊晶層。形成導電材料於此些暴露的源極/汲極磊晶層上。

Description

半導體元件及其製造方法
本發明實施例係關於一種半導體的製造方法，特別是關於一種位在閘極、源極/汲極區域及/或基板上之導電層的結構及其製造方法。
隨著半導體元件尺寸的縮小，導電層之間的分離或絕緣變得更為重要的同時，降低電阻(例如接觸電阻)亦變得更為重要。
本揭露一實施態樣為一種半導體元件的製造方法，此方法中，形成層間介電層於底層結構之上。底層結構包含：複數個閘極結構，各具有金屬閘極及帽蓋絕緣層配置於金屬閘極之上；複數個源極/汲極磊晶層配置於兩相鄰的閘極結構之間；以及蝕刻停止層覆蓋此些源極/汲極磊晶層。藉由蝕刻以形成開口於層間介電層中。形成介電填充層於此開口中。利用濕式蝕刻以移除此些源極/汲極磊晶層上方的層間介電層。移除配置於此些源極/汲極磊晶層上的蝕刻停止層，藉此至少暴露出部分此些源極/汲極磊晶層。形成導電材料於此些暴露的源極/汲極磊晶層之上。
本揭露一實施態樣為一種製造半導體元件的方法，此方法中，形成層間介電層於底層結構之上。底層結構包含：第一至第四閘極結構，各具有金屬閘極、複數個側壁間隔物配置於金屬閘極相對兩側及帽蓋絕緣層配置於金屬閘極之上，且第一至第四閘極結構以此順序沿著第一方向排列；第一源極/汲極磊晶層與第二源極/汲極磊晶層皆配置於第二閘極結構與第三閘極結構之間；以及蝕刻停止層覆蓋第一與第二源極/汲極磊晶層。藉由蝕刻在該層間介電層中之一領域形成第一開口，該領域包括第一與第二源極/汲極磊晶層之間之區域。形成介電填充層於第一開口中。利用濕式蝕刻，移除配置於第一與第二源極/汲極磊晶層上方的層間介電層，藉此分別形成第二開口和第三開口，以及移除配置於第一閘極結構與第二閘極結構之間的層間介電層，而形成第四開口。移除配置於第一及第二源極/汲極磊晶層之上的蝕刻停止層，藉此至少部分地暴露出第一及第二源極/汲極磊晶層。形成導電材料於暴露的第一與第二源極/汲極磊晶層之上，藉此形成第一源極/汲極接觸於第一源極/汲極磊晶層上以及第二 源極/汲極接觸於第二源極/汲極磊晶層上，以及形成於第四開口中，藉此形成接觸條。
本揭露一實施態樣為一種半導體元件，包含隔離絕緣層、複數個鰭狀結構、複數個閘極結構、第一源極/汲極磊晶層及第二源極/汲極磊晶層、第一導電接觸以及第二導電接觸、分離隔離區、絕緣層。複數個鰭狀結構自隔離絕緣層凸出。複數個閘極結構各具有金屬閘極與帽蓋絕緣層配置於金屬閘極上。第一源極/汲極磊晶層與第二源極/汲極磊晶層皆配置於相鄰兩閘極結構之間。第一導電接觸配置於第一源極/汲極磊晶層上，以及第二導電接觸配置於第二源極/汲極磊晶層上。分離隔離區配置於第一與第二導電接觸之間。絕緣層配置於分離隔離區與隔離絕緣層之間，其中分離隔離區係由異於絕緣層的材料所製成。
5‧‧‧鰭狀結構、通道層
10‧‧‧金屬閘極結構、閘極結構
12‧‧‧閘極介電層、介電層
14‧‧‧功函數調整層
15‧‧‧隔離絕緣層
16‧‧‧金屬材料、金屬材料層
20‧‧‧帽蓋絕緣層、閘極帽蓋層
30‧‧‧側壁間隔物
33‧‧‧底部接觸蝕刻停止層
40‧‧‧層間介電層
41‧‧‧層間介電層
42‧‧‧部分
50‧‧‧源極/汲極磊晶層、源極/汲極磊晶區域、源極/汲極區
60‧‧‧遮罩層
62‧‧‧下層、下方介電層
64‧‧‧中層
65‧‧‧開口
66‧‧‧上層、上方介電層
67‧‧‧遮罩開口圖案
67'‧‧‧遮罩開口圖案
67"‧‧‧遮罩開口圖案
70‧‧‧介電填充層
80‧‧‧源極/汲極接觸
81‧‧‧金屬層
82‧‧‧矽化物層
84‧‧‧導電材料層、導電材料
300‧‧‧基板
310‧‧‧鰭狀結構
315‧‧‧通道區
320‧‧‧隔離絕緣層
330‧‧‧金屬閘極結構340‧‧‧帽蓋絕緣層
350‧‧‧側壁間隔物
360‧‧‧源極/汲極、源極/汲極磊晶區
370‧‧‧層間介電層
當結合附圖閱讀以下詳細描述時將更好地理解本揭露內容之態樣。但須注意依照本產業的標準做法，各種特徵未按照比例繪製。事實上，各種特徵的尺寸為了清楚的討論而可被任意放大或縮小。
依據本揭露一些實施例，第1A圖繪示一種半導體元件的平面圖，第1B圖為此半導體元件之一閘極 結構的剖視圖，以及第1C圖為此半導體元件的透視圖。
第2A圖及第2B圖係依據本揭露一些實施例，分別繪示一種半導體元件於一系列製造操作中的各種階段之一。
第3A圖及第3B圖係依據本揭露一些實施例，分別繪示一種半導體元件於一系列製造操作中的各種階段之一。
第4A圖、第4B圖、第4C圖、第4D圖及第4E圖係依據本揭露一些實施例，分別繪示一種半導體元件於一系列製造操作中的各種階段之一。
第5A圖及第5B圖係依據本揭露一些實施例，分別繪示一種半導體元件於一系列製造操作中的各種階段之一。
第6A圖及第6B圖係依據本揭露一些實施例，分別繪示一種半導體元件於一系列製造操作中的各種階段之一。
第7A圖、第7B圖、第7C圖、第7D圖及第7E圖係依據本揭露一些實施例分別繪示一種半導體元件於一系列製造操作中的各種階段之一。
第7F圖及第7G圖係依據本揭露一些實施例，繪示一種半導體元件的剖視圖。
本揭露接下來將會提供許多不同的實施方式或實施例以實施本揭露中不同的特徵。各特定實施例中的組成及配置將會在以下作描述以簡化本揭露。這些為實施例僅作為式範並非用於限定本揭露。例如，一第一元件形成於一第二元件「上方」或「之上」可包含實施例中的第一元件與第二元件直接接觸，亦可包含第一元件與第二元件之間更有其他額外元件使第一元件與第二元件無直接接觸。此外，在本揭露各種不同的範例中，將重複地使用元件符號及/或字母。此重複乃為了簡化與清晰的目的，而其本身並不決定各種實施例及/或結構配置之間的關係。此外，各種特徵乃為了簡化與清晰可能會依不同比例做繪製。
更進一步，像是「之下」、「下面」、「較低」、「上面」、「較高」、以及其他類似之相對空間關係的用語，可用於此處以便描述圖式中一元件或特徵與另一元件或特徵之間的關係。該等相對空間關係的用語乃為了涵蓋除了圖式所描述的方向以外，裝置於使用或操作中之各種不同的方向。舉例來說，若於圖中的裝置被翻轉過來，原先被描述為在其他元件或特徵「之下」或「下面」的元件則變成在其他元件或特徵「上面」。因此，範例用語「之下」皆能包含上面及之下之方位。上述裝置可另有其他導向方式(旋轉90度或朝其他方向)，此時的空間相 對關係也可依上述方式解讀。此外，術語「由...製成」可意味著「包含」或「由...組成」。
由於閘極與閘極的間隔(<10奈米(nm))越來越小，在兩源極/汲極磊晶層之間層間介電層(interlayer dielectric layer,ILD)的蝕刻逐漸成為一跨越5奈米節點的關鍵製程。乾式蝕刻製程中，自我對準接觸(self-aligned contact,SAC)製程係利用聚合物以增加層間介電層(如SiO2)對金屬閘極的帽蓋絕緣層(如Si3N4)的蝕刻選擇性。此為層間介電層其蝕刻穿透能力與金屬閘極帽蓋層及側壁間隔物之損失之間的衡權。當層間介電層其蝕刻穿透能力增加時，金屬閘極帽蓋層及側壁間隔物的蝕刻量就會增加，從而一部分的金屬閘極帽蓋層及側壁間隔物被移除。在本揭露的實施例中，提供了許多透過層間介電層去形成接觸時的操作及結構以增加蝕刻選擇性。
根據本揭露一些實施例，第1A圖繪示一種半導體元件的平面圖。第1B圖為沿著第1A圖線段X2-X2，半導體元件之閘極結構的剖示圖。第1C圖為半導體元件的透視圖。
第1A圖至第1C圖繪示在金屬閘極結構及第一層間介電層形成後，鰭式場效電晶體(fin field effect transistor,FinFET)元件的數種結構。鰭狀結構5可例如由矽所製成，配置並朝方向X延伸。金屬 閘極結構10朝方向Y延伸且源極/汲極磊晶層50配置於相鄰的金屬閘極之間。在第1A圖中，一些位於金屬閘極結構10之間無源極/汲極磊晶層50的鰭狀結構被暴露出來，但本發明實施例不限於此種配置。
金屬閘極結構10形成於一或多個通道層之上，例如部分鰭狀結構5。鰭狀結構5配置於基板上並自隔離絕緣層(例如：淺溝槽隔離(shallow trench isolation,STI))15(參照第2A圖)凸出。在第1A圖，四個鰭狀結構5沿著方向Y進行配置，而四個金屬閘極結構10沿著方向X進行配置。然而，鰭狀/閘極結構的數目並不限於四個。
側壁間隔物30設置在金屬閘極結構10的側壁上。在一些實施例中，側壁間隔物底部的側壁間隔物30之膜厚度為約3奈米至約15奈米，而在其他實施例中，為約4奈米至約10奈米。金屬閘極結構10及側壁間隔物30的組合可被視為一閘極結構。更進一步地，形成源極/汲極磊晶區域50相鄰於閘極結構。
第一層間介電層40(參照第2A及2B圖)填充於閘極結構間的間距。在本揭露中，源極及汲極可被交替使用且實質上並無結構的差異。術語「一源極/汲極」(源/汲極)係指含一源極及一汲極之一組。
第1B圖為金屬閘極結構的剖面放大圖。 金屬閘極結構10包含一或多層金屬材料16，例如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TaN、NiSi、CoSi或任何其他適合的導電材料。配置於通道層5及金屬閘極結構之間的閘極介電層12包含一或多層金屬氧化物，例如高介電常數(high-k)的金屬氧化物。舉例而言，用於高介電常數的金屬氧化物包含Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、T、Yb、Lu及/或其混合物，或任何其他適合的介電材料。在一些實施例中，由SiO2製成的界面層具有厚度為約1-3奈米，形成於通道層5與高介電常數閘極介電層12之間。
在一些實施例中，一或多層功函數調整層14配置於閘極介電層12與金屬材料16之間。功函數調整層14由導電材料製成，例如單層的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或二種或多種此些材料之多層，或任何其他適合的導電材料。對n通道場效電晶體而言，功函數調整層係為一或多種TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi，或任何其他適合的導電材料。對p通道場效電晶體而言，功函數調整層係為一或多種TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co，或任何其他適合的導電材料。
在本實施例中，鰭式場效電晶體(FinFET) 係採用閘極置換製程(gate-replacement process)所製造。然而，此處所揭露的技術可應用於其他電子元件，例如平面式場效電晶體、環繞式閘極場效電晶體、多閘極式場效電晶體、電容器、二極體及電阻器。
第1C圖係依據本揭露各種實施例，繪示鰭式場效電晶體結構的透視圖。鰭式場效電晶體結構可以下述操作進行製造。
首先，鰭狀結構310製造於基板300之上。鰭狀結構可以任何適合的方法進行圖案化。舉例而言，鰭狀結構可利用一或多種微影製程進行圖案化，包含雙圖案(double-patterning)或多圖案(multi-patterning)製程。普遍來說，雙圖案或多圖案製程結合微影技術及自我對準製程，例如可使得所獲得的圖案化其間距小於使用單一、直接的微影製程。舉例而言，在一實施例中，犧牲層形成於基板之上並利用微影製程進行圖案化。利用自我對準製程，透過圖案化犧牲層沿邊形成間隔。接著移除犧牲層，而剩餘的間隔或心軸(mandrel)後續可用於對鰭狀結構進行圖案化。
鰭狀結構包含底部區域及做為通道區315的上方區域。舉例而言，基板為p型矽基板，雜質濃度為約1×1015立方公分(cm-3)至約1×1018立方公分。在其他實施例中，基板為n型矽基板，雜質濃 度為約1×1015立方公分至約1×1018立方公分。或者，基板可包含其他基本半導體，例如鍺；複合半導體包含四四族複合半導體例如SiC及SiGe，三五族複合半導體例如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP或任何其他適合的半導體材料；或其組合。在一實施例中，基板為絕緣體上矽基板(silicon-on-insulator,SOI)之矽層。
在形成鰭狀結構310之後，隔離絕緣層320形成於鰭狀結構310之上。隔離絕緣層320包含一或多層絕緣材料，例如氧化矽、氮氧化矽或氮化矽，且藉由LPCVD、電漿CVD或流動式CVD形成。隔離絕緣層可藉旋塗式玻璃(spin-on-glass,SOG)、SiO、SiON、SiOCN及/或摻氟矽玻璃(fluorine-doped silicate glass,FSG)或任何其他適合的介電材料形成。
形成隔離絕緣層320於鰭狀結構上之後，執行平坦化操作以移除部分隔離絕緣層320。平坦化操作可包含化學機械研磨(chemical mechanical polishing,CMP)及/或回蝕製程。接著，進一步移除(凹陷)隔離絕緣層320使得鰭狀結構的上方區域暴露出來。
虛設閘極結構形成於暴露的鰭狀結構之上。虛設閘極結構包含由多晶矽製成的虛設閘極電極層及虛設閘極介電層。具有一或多層絕緣材料的側壁間隔物350亦形成於虛設閘極電極層之複數個側壁之上。形成虛設閘極結構之後，未被虛設閘極結構覆蓋的鰭狀結構310被凹陷至低於隔離絕緣層320之上表面。接著，透過磊晶成長方法將源極/汲極區360形成於凹陷的鰭狀結構上。源極/汲極區可包含應變材料施加應力至通道區315。
然後，層間介電層370形成於虛設閘極及源極/汲極區之上。層間介電層370包含一或多層氧化矽、SiOC、SiOCN或SiCN或其他低介電常數(low-k)材料，或多孔材料，或任何其他適合的介電材料。在平坦化操作後，移除虛設閘極以便形成閘極空間。在此閘極空間中，形成包含金屬閘極電極及閘極介電層(例如高介電常數介電層)之金屬閘極結構330。
進一步地，在一些實施例中，帽蓋絕緣層340形成於金屬閘極結構330上以獲得如第1C圖所示之鰭式場效電晶體結構。
在第1C圖中，部分金屬閘極結構330、部分帽蓋絕緣層340、部分側壁間隔物350及部分層間介電層370省略以顯示下方結構。在一些實施例中，相鄰的源極/汲極磊晶區360彼此合併，且在合併之源極/汲極區上形成矽化物層。
第1C圖中的金屬閘極結構330、帽蓋絕緣 層340、側壁間隔物350、源極/汲極360及層間介電層370實質上分別對應至第1A、1B及2A圖中的金屬閘極結構10、帽蓋絕緣層20(參照第2A圖)、側壁間隔物30、源極/汲極區50及第一層間介電層40。
第2A圖至第7E圖係依據本揭露之一實施例，繪示一系列半導體元件製程的各種階段。在第2A圖至第7E圖中，「A」圖(例如2A、3A...)繪示剖面圖對應至第1A圖中之線段X1-X1，以及「B」圖(例如2B、3B...)繪示剖面圖對應至第1A圖中之線段Y1-Y1。應理解的是，額外的操作可用於第2A圖至第7E圖所示的製程之前、期間及之後，且下述一些操作可被取代或刪除以用於此方法之其他實施例，而操作/製程的順序可交替使用。
在第2A圖及第2B圖中，帽蓋絕緣層20配置於金屬閘極結構10之上。
在一些實施例中，從高介電常數介電層12之上表面至帽蓋絕緣層20之底部的金屬閘極結構10之厚度為15奈米至50奈米。在一些實施例中，帽蓋絕緣層20的厚度為約10奈米至約30奈米，而在其他實施例中為約15奈米至約20奈米。在一些實施例中，帽蓋絕緣層20配置於側壁間隔物30之上，而在其他實施例中，側壁間隔物30配置於帽蓋絕緣層20的側壁上。
進一步地，如第2A圖及第2B圖所示，形成層間介電層40之前，底部接觸蝕刻停止層33形成於閘極結構及源極/汲極磊晶區50之上。在一些實施例中，底部接觸蝕刻停止層33的膜厚度為約1奈米至約20奈米。
帽蓋絕緣層20包含一或多層絕緣材料，例如氮化矽基材料，包含SiN、SiON、SiCN、SiOCN或任何其他適合的介電材料。
側壁間隔物30由異於帽蓋絕緣層20的材料製成且包含一或多層絕緣材料，例如氮化矽基材料，包含SiN、SiON、SiCN、SiOCN或任何其他適合的介電材料。底部接觸蝕刻停止層33由異於帽蓋絕緣層20及側壁間隔物30的材料製成，且包含一或多層絕緣材料，例如氮化矽基材料，包含SiN、SiON、SiCN、SiOCN或任何其他適合的介電材料。第一層間介電層40包含一或多層氧化矽、SiOC、SiOCN或SiCN或其他低介電常數材料，或多孔材料，或任何其他適合的介電材料。第一層間介電層40可藉由低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)、電漿CVD、流動式CVD或其他適合的膜形成方法來形成。
底層接觸蝕刻停止層33的材料、側壁間隔物30、帽蓋絕緣層20的材料及第一層間介電層40的材料可彼此相異，使得此些層體可被選擇性蝕刻。在一些實施例中，底層接觸蝕刻停止層33由SiN 或SiCN製成；側壁間隔物30由SiO2、SiOCN、SiCN或SiON製成；帽蓋絕緣層20由SiN或SiON製成；以及第一層間介電層40由SiO2製成。
接著，如第3A圖及第3B圖所示，遮罩層60形成於第2A圖及第2B圖中的結構之上。遮罩層60可為單層或多層，且可包含阻層、介電層、導電層、金屬層及/或多晶或非晶層(例如：多晶/非晶矽)。在一些實施例中，遮罩層60包含下方介電層62、中層64及上方介電層66。在某些實施例中，下層62為氧化矽層，中層64為TiN層及上層66為氧化矽層。遮罩層60之各層可藉由CVD、物理氣相沉積(physical vapor deposition,PVD)(例如濺鍍)，或原子層沉積(atomic layer deposition,ALD)或任何其他適合的膜形成方法來形成。
然後，如第4A圖及第4B圖所示，透過微影技術及蝕刻操作對上層66進行圖案化，並利用圖案化的上層66對中層64進行圖案化。進一步地，以圖案化的中層64做為蝕刻遮罩，對下層62及層間介電層40進行圖案化，藉此形成開口65。以X方向來看，開口65的寬度W1等於或大於相鄰金屬閘極結構10之間的距離。以Y方向來看，開口65的寬度W2等於或小於相鄰源極/汲極磊晶區50之間的距離。
第4C圖及第4E圖繪示用於微影操作中製造開口65的遮罩開口圖案67之平面圖。在第4C圖 中，其實質上係對應至第2A圖至第7E圖中對實施例所做的解釋，三個遮罩開口圖案67分別配置以部分重疊源極/汲極磊晶區50及金屬閘極結構10。在其他實施例中，如第4D圖所示，遮罩開口圖案67'配置以重疊相鄰閘極結構10及源極/汲極磊晶區50之兩個間距。在其他實施例中，如第4E圖所示，遮罩開口圖案67"亦覆蓋到源極/汲極磊晶區未形成於鰭狀結構5的區域。在一些實施例中，多於一個開口圖案67、67'及/或67"可被合併使用。
在蝕刻層間介電層40的期間，帽蓋絕緣層20的上方及/或側邊部分亦會受到蝕刻，導致V形開口朝方向Z形成於開口65的頂部附近。在一些實施例中，側壁間隔物30及/或底部接觸蝕刻停止層33亦受部分蝕刻。
在一些實施例中，如第4B圖所示，層間介電層40的蝕刻實質上止於覆蓋在源極/汲極磊晶層50上的底部接觸蝕刻停止層33。尤其，當相鄰源極/汲極磊晶層50之間的間距小時，蝕刻作用停止於底部接觸蝕刻停止層33。在此情況下，部分層間介電層40殘留於開口65的底部。在一些實施例中，當相鄰源極/汲極磊晶層50之間的間距大時，蝕刻繼續進行並停止在配置於隔離絕緣層15上的底部接觸蝕刻停止層33。在其他實施例中，無層間介電層40殘留於後續形成的介電填充層70與隔離絕緣層15之 間。
然後，如第5A圖及第5B圖所示，介電填充層70形成於開口65中。舉例而言，介電填充層70由SiN或SiCN製成，其在稀釋氫氟酸濕式蝕刻中對SiO2具有高蝕刻選擇性(高於約10或約100)。
介電填充層70可藉由CVD、PVD(例如濺鍍)，或ALD或任何其他適合的膜形成方法來形成。執行平坦化操作(例如：化學機械研磨(CMP))以移除層間介電層40上多餘的材料。如第5A圖及第5B圖所示，介電填充層70填補被蝕刻的帽蓋絕緣層20。若側壁間隔物30及/或底部接觸蝕刻停止層33在蝕刻層間介電層時亦受到蝕刻，介電填充層70可填補被蝕刻的側壁間隔物30及/或底部接觸蝕刻停止層33。
如第5B圖所示及上述所提，當相鄰源極/汲極磊晶層50之間的間距小時，部分層間介電層41殘留在介電填充層70的底部。
然後，如第6A圖及第6B圖所示，層間介電層40藉由濕式蝕刻移除。在一些實施例中，蝕刻溶液為稀釋氫氟酸(DHF)。在一些實施例中，氫氟酸在稀釋氫氟酸中的濃度為約1wt%。與乾式蝕刻不同的是，採用稀釋氫氟酸濕式蝕刻不會有聚合物的形成。因此，即使在小空間/區域中，氫氟酸濕式蝕刻可移除第一層間介電層40。
在本發明實施例中，層間介電層40由SiO2 或氧化矽基材料所製成，而閘極帽蓋層20、底部接觸蝕刻停止層33及介電填充層70由SiN或SiCN製成。
1wt%稀釋氫氟酸中，SiO2及SiN間的蝕刻選擇性為約10，而SiO2及SiCN間的蝕刻選擇性為約100或更高。據此，層間介電層40可被稀釋氫氟酸完全移除而不會使閘極帽蓋層20、底部接觸蝕刻停止層33及/或介電填充層70受到損害。
接著，如第7A圖至第7E圖所示，利用乾式蝕刻及/或濕式蝕刻移除配置於源極/汲極磊晶層50上的底部接觸蝕刻停止層33以形成接觸開口，並接著沉積用於矽化物形成的金屬層81。金屬層81可藉由CVD、PVD或ALD，或任何其他適合的膜形成方法來形成。形成金屬層81之後，執行熱操作(例如：快速熱退火操作)以自源極/汲極磊晶區域50的組成分(例如：Si)及金屬層81的金屬(例如：W、Ni、Co、Ti及/或Mo)形成矽化物層82。在一些實施例中，由於在形成金屬層81的期間可形成矽化物，故不進行熱操作。如第7B圖所示，在一些實施例中，金屬層81殘留在介電填充層70的側邊而無形成矽化物層。
形成矽化物層82之後，導電材料84填充於接觸開口中，藉此形成源極/汲極接觸80。
在一些實施例中，導電材料層84包含主體金屬層之黏附(膠)層之包覆層。黏附層包含一或多層導電材料。在一些實施例中，黏附層可包含TiN層形成於Ti層之上。任何其他適合的導電材料都可被使用。在一些實施例中，TiN層及Ti層各自的厚度為約1奈米至約5奈米。黏附層可藉由CVD、PVD、ALD、電鍍或其組合，或其他適合的膜形成方法來形成。黏附層係用於防止主體金屬層剝落。在一些實施例中，主體金屬層係直接形成於接觸開口中而無使用黏附層。在此情況下，主體金屬層係直接接觸矽化物層82。
在一些實施例中，主體金屬層為Co、W、Mo及Cu其中之一，或任何其他適合的導電材料。在一實施例中，使用Cu作為主體金屬材料層。主體金屬層可藉由CVD、PVD、ALD、電鍍或其組合，或其他適合的膜形成方法來形成。
形成導電材料層84之後，執行平坦化操作(如CMP)或回蝕操作以便移除多餘的材料。
第7C圖至第7E圖繪示對應至第4C圖至第4E圖之平面圖。介電填充層70沿方向Y將相鄰的源極/汲極接觸80分隔開來。如第7B圖至第7E圖所示，在平面圖中，介電填充層70為條形、島形或L形。在其他實施例中，就平面圖而言，介電填充層70為T形或H形。沿方向Y來看，介電填充層70可分隔(物理性或電性)一對源極/汲極接觸80且亦能覆蓋部分不應形成源極/汲極接觸80的地方。舉例而言，介電填充層70配置於相鄰兩源極/汲極磊晶層間的空間及/或上方無形成源極/汲極磊晶層的鰭狀結構。
應理解的是，第7A圖至第7E圖中所示的元件可進一步透過互補式金屬氧化半導體(CMOS)製程形成各種特徵，例如互連金屬層、介電層、鈍化層等等。
第7F圖及第7G圖係依據本揭露其他實施例，繪示半導體元件的剖視圖。
如前述所提，用於形成開口65的蝕刻操作止於不同層且部分層間介電層40可或不可殘留於後續形成的介電填充層70與隔離絕緣層15之間。
舉例而言，在第7F圖中，層間介電層40之部分42殘留在源極/汲極磊晶層50的下方部分，而介電填充層70則直接接觸底部接觸蝕刻停止層33。在第7G圖中，介於兩相鄰源極/汲極磊晶層50之間的介電層40藉由用於形成開口65的蝕刻作用而被完全移除，隨後介電填充層70填滿充源極/汲極磊晶層50的下方部分並直接接觸源極/汲極磊晶層50及底部接觸蝕刻停止層33。
此處所述的各種實施例或實施方式提供若干優於現存技術的優點。舉例來說，透過濕式蝕刻，可從諸如直徑約10奈米或更小的深接觸孔之小間距中移除層間介電層材料(SiO2)。進一步地，因蝕 刻作用而損失的金屬閘極之帽蓋絕緣層可藉介電填充層修補，其可增強金屬閘極周圍的電性分隔(絕緣)。
應將理解的是，本文沒有必要討論所有的優點，所有實施例或實施方式無需特定優點，並且其他實施例或實施方式可提供不同的優點。
根據本揭露之一實施態樣，製造半導體元件的方法中，層間介電層形成於底層結構之上。底層結構包含：複數個閘極結構，各具有金屬閘極及帽蓋絕緣層配置於金屬閘極之上；複數個源極/汲極磊晶層配置於兩相鄰的閘極結構之間；以及蝕刻停止層覆蓋此些源極/汲極磊晶層。透過蝕刻作用，開口形成於層間介電層中。介電填充層形成於開口中。透過濕式蝕刻，移除此些源極/汲極磊晶層上方的層間介電層。移除配置於此些源極/汲極磊晶層上的蝕刻停止層，藉此至少暴露出部分此些源極/汲極磊晶層。導電材料形成於此些暴露的源極/汲極磊晶層之上。
在本揭露另一實施態樣中，製造半導體元件的方法中，層間介電層形成於底層結構之上。底層結構包含：第一至第四閘極結構，各具有金屬閘極、複數個側壁間隔物配置於金屬閘極的相對兩側及帽蓋絕緣層配置於金屬閘極之上，且第一至第四閘極結構以此順序沿著第一方向排列。底層結構 進一步包含第一源極/汲極磊晶層與第二源極/汲極磊晶層，皆配置於第二閘極結構與第三閘極結構之間；以及蝕刻停止層覆蓋第一與第二源極/汲極磊晶層。藉由蝕刻在層間介電層中之一領域形成第一開口，此領域包括第一與第二源極/汲極磊晶層之間之區域。介電填充層形成於第一開口中。透過濕式蝕刻，移除配置於第一與第二源極/汲極磊晶層上方的層間介電層，藉此分別形成第二開口和第三開口，以及移除配置於第一閘極結構與第二閘極結構之間的層間介電層，而形成第四開口。移除配置於第一及第二源極/汲極磊晶層之上的蝕刻停止層，藉此至少部分地暴露出第一及第二源極/汲極磊晶層。形成導電材料於暴露的第一與第二源極/汲極磊晶層之上，藉此形成第一源極/汲極接觸於第一源極/汲極磊晶層上以及第二源極/汲極接觸於第二源極/汲極磊晶層上，以及形成於第四開口中，藉此形成接觸條。
在本揭露另一實施態樣中，半導體元件包含：隔離絕緣層；複數個鰭狀結構自隔離絕緣層凸出；複數個閘極結構，各具有金屬閘極及帽蓋絕緣層配置於金屬閘極上；第一源極/汲極磊晶層與第二源極/汲極磊晶層，皆配置於兩相鄰的此些閘極結構之間；第一導電接觸配置於第一源極/汲極磊晶層上，以及第二導電接觸配置於第二源極/汲極磊晶層上；分離隔離區配置於第一與第二導電接觸之間； 以及絕緣層配置於分離隔離區與隔離絕緣層之間。分離隔離區係由異於絕緣層的材料所製成。
前文概述數個實施例之特徵以使得熟習該項技術者可更好地理解本揭露之態樣。熟習該項技術者應瞭解，可容易地將本揭露內容用作設計或修改用於實現相同目的及/或達成本文引入之實施例的相同優點之其他製程及結構之基礎。熟習該項技術者亦應認識到，此類等效物構造不違背本揭露內容之精神及範疇，且可在不違背本揭露內容之精神及範疇之情況下於此作出各種變化、替代以及變更。

Claims (10)

  1. 一種半導體元件的製造方法，包含：形成一層間介電層於一底層結構之上，該底層結構包含：複數個閘極結構，各具有一金屬閘極及一帽蓋絕緣層配置於該金屬閘極之上；複數個源極/汲極磊晶層，配置於兩相鄰的該些閘極結構之間；以及一蝕刻停止層，覆蓋該些源極/汲極磊晶層；藉由蝕刻以形成一開口於該層間介電層中；形成一介電填充層於該開口中；利用濕式蝕刻以移除該些源極/汲極磊晶層上方的該層間介電層；移除配置於該些源極/汲極磊晶層上的該蝕刻停止層，藉此至少暴露出部分該些源極/汲極磊晶層；以及形成一導電材料於該些暴露的源極/汲極磊晶層之上。
  2. 如申請專利範圍第1項所述之方法，其中：各該閘極結構進一步包含複數個側壁間隔物，形成於該金屬閘極的相對兩側上；且該些側壁間隔物係為選自由SiCN及SiOCN所組成之群組中的至少一者所製成。
  3. 如申請專利範圍第1項所述之方法，其中在形成該開口的步驟中，該帽蓋絕緣層被部分地移除，且該介電填充層被形成於該帽蓋絕緣層之一部分上，其位於該帽蓋絕緣層被部分地移除之處。
  4. 如申請專利範圍第3項所述之方法，其中：各該閘極結構進一步包含複數個側壁間隔物形成於該金屬閘極的相對兩側上；以及形成該開口的步驟中，該蝕刻停止層及該些側壁間隔物被部分地移除，且該介電填充層形成以接觸該些側壁間隔物。
  5. 如申請專利範圍第1項所述之方法，其中：形成該開口後，部分的該層間介電層殘留在該開口下方；且該介電填充層係形成於該開口內之殘留的該層間介電層的上方。
  6. 一種製造半導體元件的方法，包含：形成一層間介電層於一底層結構之上，該底層結構包含：第一至第四閘極結構，各具有一金屬閘極、複數個側壁間隔物配置於該金屬閘極相對兩側及一帽蓋絕緣層配置於該金屬閘極之上，且該第一至第四閘極結構以此順序沿著一第一方向排列；一第一源極/汲極磊晶層與一第二源極/汲極磊晶層，皆配置於該第二閘極結構與該第三閘極結構之間；以及一蝕刻停止層，覆蓋該第一與第二源極/汲極磊晶層；藉由蝕刻在該層間介電層中之一領域形成一第一開口，該領域包括該第一與該第二源極/汲極磊晶層之間之一區域；形成一介電填充層於該第一開口中；利用濕式蝕刻，移除配置於該第一與第二源極/汲極磊晶層上方的該層間介電層，藉此分別形成一第二開口和一第三開口，以及移除配置於該第一閘極結構與該第二閘極結構之間的該層間介電層，而形成一第四開口；移除配置於該第一及該第二源極/汲極磊晶層之上的該蝕刻停止層，藉此至少部分地暴露出該第一及第二源極/汲極磊晶層；以及形成一導電材料於暴露的該第一及該第二源極/汲極磊晶層之上，藉此形成一第一源極/汲極接觸於該第一源極/汲極磊晶層上以及一第二源極/汲極接觸於該第二源極/汲極磊晶層上，以及形成於該第四開口中，藉此形成一接觸條。
  7. 如申請專利範圍第6項所述之方法，其中形成該第一開口的步驟中，該帽蓋絕緣層被部分地移除，且該介電填充層被形成於該帽蓋絕緣層被移除的一部分上。
  8. 如申請專利範圍第7項所述之方法，其中形成該第一開口的步驟中，該蝕刻停止層以及該第二和該第三閘極結構的該些側壁間隔物被部分地移除，且該介電填充層被形成以接觸該第二和該第三閘極結構的該些側壁間隔物。
  9. 如申請專利範圍第6項所述之方法，其中：在形成該第一開口之後，部分的該層間介電層殘留在該第一開口下方；且該介電填充層係形成在該第一開口中之殘留的該層間介電層的上方。
  10. 一種半導體元件，包含：一隔離絕緣層；複數個鰭狀結構，自該隔離絕緣層凸出；複數個閘極結構，各具有一金屬閘極及一帽蓋絕緣層配置於該金屬閘極上；一第一源極/汲極磊晶層及一第二源極/汲極磊晶層，皆配置於兩相鄰的該些閘極結構之間；一第一導電接觸，配置於該第一源極/汲極磊晶層上，以及一第二導電接觸配置於該第二源極/汲極磊晶層上；一分離隔離區，配置於該第一與該第二導電接觸之間；以及一絕緣層，配置於該分離隔離區與該隔離絕緣層之間，其中該分離隔離區係由異於該絕緣層的材料所製成。
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CN108257871B (zh) 2021-09-03
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US20200243344A1 (en) 2020-07-30
US10121675B2 (en) 2018-11-06
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US20190013208A1 (en) 2019-01-10
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