CN108257871A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN108257871A
CN108257871A CN201710979479.1A CN201710979479A CN108257871A CN 108257871 A CN108257871 A CN 108257871A CN 201710979479 A CN201710979479 A CN 201710979479A CN 108257871 A CN108257871 A CN 108257871A
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layer
source
drain extensions
drain
dielectric
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CN108257871B (zh
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李振铭
杨复凯
王美匀
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在制造半导体器件的方法中，在下面的结构上方形成层间介电(ILD)层。下面的结构包括栅极结构(每个均具有金属栅极和设置在金属栅极上方的覆盖绝缘层)、设置在两个邻近的栅极结构之间的源极/漏极外延层以及覆盖源极/漏极外延层的蚀刻停止层(ESL)。通过蚀刻在ILD层中形成开口。在开口中形成介电填充层。通过使用湿蚀刻，去除设置在源极/漏极外延层之上的ILD层。去除设置在源极/漏极外延层上的ESL，从而至少部分地暴露源极/漏极外延层。在暴露的源极/漏极外延层上方形成导电材料。本发明的实施例还涉及半导体器件。

Description

半导体器件及其制造方法
技术领域
本发明涉及用于制造半导体器件的方法，并且更具体地，涉及用于栅极、源极/漏极区域和/或衬底上方的导电层的结构和制造方法。
背景技术
随着半导体器件尺寸的减小，导电层之间的分离或绝缘变得更加重要，同时降低电阻(例如，接触电阻)变得更加重要。
发明内容
本发明的实施例提供了一种制造半导体器件的方法，所述方法包括：在下面的结构上方形成层间介电(ILD)层，所述下面的结构包括：栅极结构，每个均具有金属栅极和设置在所述金属栅极上方的覆盖绝缘层；源极/漏极外延层，设置在两个邻近的所述栅极结构之间；和蚀刻停止层(ESL)，覆盖所述源极/漏极外延层；通过蚀刻在所述层间介电层中形成开口；在所述开口中形成介电填充层；通过使用湿蚀刻，去除设置在所述源极/漏极外延层之上的所述层间介电层；去除设置在所述源极/漏极外延层上的所述蚀刻停止层，从而至少部分地暴露所述源极/漏极外延层；以及在暴露的源极/漏极外延层上方形成导电材料。
本发明的另一实施例提供了一种制造半导体器件的方法，所述方法包括：在下面的结构上方形成层间介电(ILD)层，所述下面的结构包括：第一栅极结构至第四栅极结构，每个均具有金属栅极、设置在所述金属栅极的相对侧上的侧壁间隔件以及设置在所述金属栅极上方的覆盖绝缘层，所述第一栅极结构至所述第四栅极结构沿着第一方向以这种顺序布置；第一源极/漏极(S/D)外延层和第二源极/漏极外延层，两个均设置在第二栅极结构和第三栅极结构之间；和蚀刻停止层(ESL)，覆盖所述第一源极/漏极外延层和所述第二源极/漏极外延层；通过蚀刻在包括所述第一源极/漏极外延层和所述第二源极/漏极外延层之间的区域的区上方的所述层间介电层中形成第一开口；在所述第一开口中形成介电填充层；通过使用湿蚀刻，去除设置在所述第一源极/漏极外延层和所述第二源极/漏极外延层之上的所述层间介电层，从而分别形成第二开口和第三开口，并且去除设置在所述第一栅极结构和所述第二栅极结构之间的所述层间介电层，从而形成第四开口；去除设置在所述第一源极/漏极外延层和所述第二源极/漏极外延层上的所述蚀刻停止层，从而至少部分地暴露所述第一源极/漏极外延层和所述第二源极/漏极外延层；以及在暴露的所述第一源极/漏极外延层和所述第二源极/漏极外延层上方形成导电材料，从而在所述第一源极/漏极外延层上形成第一源极/漏极接触件并且在所述第二源极/漏极外延层上形成第二源极/漏极接触件，并且从而在所述第四开口中形成接触条。
本发明的又一实施例提供了一种半导体器件，包括：隔离绝缘层；鳍结构，突出于所述隔离绝缘层；栅极结构，每个均具有金属栅极和设置在所述金属栅极上方的覆盖绝缘层；第一源极/漏极外延层和第二源极/漏极外延层，设置在两个邻近的所述栅极结构之间；第一导电接触件和第二导电接触件，所述第一导电接触件设置在所述第一源极/漏极外延层上，并且所述第二导电接触件设置在所述第二源极/漏极外延层上；分离隔离区域，设置在所述第一导电接触件和所述第二导电接触件之间；以及绝缘层，设置在所述分离隔离区域和所述隔离绝缘层之间，其中，所述分离隔离区域由与所述绝缘层不同的材料制成。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A示出了根据本发明的实施例的半导体器件的平面图，图1B示出了根据本发明的实施例的半导体器件的栅极结构的截面图，并且图1C示出了根据本发明的实施例的半导体器件的立体图。
图2A和图2B分别示出了根据本发明的实施例的用于半导体器件的顺序制造操作的各个阶段的一个。
图3A和图3B分别示出了根据本发明的实施例的用于半导体器件的顺序制造操作的各个阶段的一个。
图4A、图4B、图4C、图4D和图4E分别示出了根据本发明的实施例的用于半导体器件的顺序制造操作的各个阶段的一个。
图5A和图5B分别示出了根据本发明的实施例的用于半导体器件的顺序制造操作的各个阶段的一个。
图6A和图6B分别示出了根据本发明的实施例的用于半导体器件的顺序制造操作的各个阶段的一个。
图7A、图7B、图7C、图7D和图7E分别示出了根据本发明的实施例的用于半导体器件的顺序制造操作的各个阶段的一个。图7F和图7G分别示出了根据本发明的其它实施例的半导体器件的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，元件的尺寸不限于公开的范围或值，但是可能依赖于工艺条件和/或器件所需的性能。此外，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，各个部件可以以不同的比例任意地绘制。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。此外，术语“由…制成”可能意味着“包括”或者“由…组成”。
由于栅极至栅极间隔(＜10nm)变得越来越小，因此位于两个源极/漏极(S/D)外延层之间的层间介电(ILD)层的蚀刻变成超过5nm节点的关键工艺。干蚀刻工艺中的自对准接触(SAC)工艺使用聚合物以增加ILD层(例如，SiO2)与金属栅极(MG)的覆盖绝缘层(例如，Si3N4)的蚀刻选择性。在ILD层的蚀刻穿过能力以及MG覆盖层和侧壁间隔件的损失之间存在折衷。当ILD蚀刻穿过能力增加时，MG覆盖层和侧壁间隔件的蚀刻量增加，并且去除了MG覆盖层和侧壁间隔件的部分。在本实施例中，提供穿过ILD层形成接触件时增加蚀刻选择性的操作和结构。
图1A示出了根据本发明的实施例的半导体器件的平面图，图1B是根据本发明的实施例的对应于图1A的线X2-X2的半导体器件的栅极结构的截面图并且图1C是根据本发明的实施例的半导体器件的立体图。
图1A至图1C示出了在形成金属栅极结构和第一层间介电(ILD)层之后的半导体鳍式场效应晶体管(FinFET)器件的结构。由例如Si制成的鳍结构5设置在X方向上并且在X方向上延伸。金属栅极结构10在Y方向上延伸并且源极/漏极(S/D)外延层50设置在邻近的金属栅极之间。在图1A中，在没有S/D外延层50的金属栅极结构10之间暴露一些鳍结构，但是本实施例不限于这种配置。
在一个或多个沟道层(例如，鳍结构5的一部分)上方形成金属栅极结构10。鳍结构5设置在衬底上方并且突出于隔离绝缘层(例如，浅沟槽隔离(STI))15(见图2A)。在图1A中，沿着Y方向设置四个鳍结构5并且沿着X方向设置四个金属栅极结构10。然而，鳍/栅极结构的数量不限于四个。
在金属栅极结构10的侧壁上提供侧壁间隔件30。在一些实施例中，侧壁间隔件的底部处的侧壁间隔件30的膜厚度在从约3nm至约15nm的范围内，并且在其它实施例中，在从约4nm至约10nm的范围内。金属栅极结构10和侧壁间隔件30的组合可以统称为栅极结构。此外，S/D外延区域50形成为邻近于栅极结构。
用第一层间介电(ILD)层40(见图2A和图2B)填充栅极结构之间的间隔。在本发明中，源极/漏极可互换使用并且基本没有结构差异。术语“源极/漏极”指的是源极和漏极的一个。
图1B是金属栅极结构的放大的截面图。金属栅极结构10包括金属材料的一层或多层16，金属材料诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi、CoSi或任何其它合适的导电材料。设置在沟道层5和金属栅极结构之间的栅极介电层12包括诸如高k金属氧化物的金属氧化物的一层或多层。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物和/或它们的混合物或任何其它合适的介电材料。在一些实施例中，在沟道层5和高k栅极介电层12之间形成由SiO2(具有1-3nm厚度)制成的界面层。
在一些实施例中，一个或多个功函调整层14插入在栅极介电层12和金属材料16之间。功函调整层14由诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或这些材料的两种或多种的多层的导电材料或任何其它合适的导电材料制成。对于n沟道FET，TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi的一种或多种或任何其它合适的导电材料用作功函调整层，并且对于P沟道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co的一种或多种或任何其它合适的导电材料用作功函调整层。
在本实施例中，采用由栅极替换工艺制造的鳍式场效应晶体管(FinFET)。然而，本文公开的技术可以应用于其它电子器件，诸如平面FET、全环栅FET、多栅极FET、电容器、二极管和电阻器。
图1C示出了根据本发明的实施例的FinFET结构的立体图。FinFET结构可以以下操作制造。
首先，在衬底300上方制造鳍结构310。可以通过任何合适的方法图案化鳍结构。例如，可以使用一种或多种光刻工艺(包括双重图案化或多重图案化工艺)图案化鳍结构。通常，双重图案化或多重图案化工艺结合光刻和自对准工艺，允许创建具有例如小于使用单个直接的光刻工艺可获得的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并且使用光刻工艺图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。之后去除牺牲层，并且之后剩余的间隔件或芯轴可以用于图案化鳍结构。
鳍结构包括底部区域和用作沟道区域315的上部区域。衬底是例如具有在从约1×1015cm-3至约1×1018cm-3的范围内的杂质浓度的p型硅衬底。在其它实施例中，该衬底是具有在从约1×1015cm-3至约1×1018cm-3的范围内的杂质浓度的n型硅衬底。可选地，该衬底可以包括另一元素半导体，诸如锗；化合物半导体，包括诸如SiC和SiGe的IV-IV族化合物半导体、诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V族化合物半导体，或任何其它合适的半导体材料；或它们的组合。在一个实施例中，该衬底是SOI(绝缘体上硅)衬底的硅层。
在形成鳍结构310之后，在鳍结构310上方形成隔离绝缘层320。隔离绝缘层320包括通过LPCVD、等离子体CVD或可流动CVD形成的诸如氧化硅、氮氧化硅或氮化硅的绝缘材料的一层或多层。可以由旋涂玻璃(SOG)、SiO、SiON、SiOCN和/或氟掺杂的硅酸盐玻璃(FSG)或任何其它合适的介电材料的一层或多层形成隔离绝缘层。
在鳍结构上方形成隔离绝缘层320之后，实施平坦化操作以去除隔离绝缘层320的一部分。平坦化操作可以包括化学机械抛光(CMP)和/或回蚀刻工艺。之后，进一步去除(凹进)隔离绝缘层320从而暴露鳍结构的上部区域。
在暴露的鳍结构上方形成伪栅极结构。伪栅极结构包括由多晶硅制成的伪栅电极层和伪栅极介电层。包括绝缘材料的一层或多层的侧壁间隔件350也形成在伪栅电极层的侧壁上。在形成伪栅极结构之后，使未由伪栅极结构覆盖的鳍结构310凹进至隔离绝缘层320的上表面之下。之后，通过使用外延生长方法在凹进的鳍结构上方形成源极/漏极区域360。源极/漏极区域可以包括应变材料以对沟道区域315施加应力。
之后，在伪栅极结构和源极/漏极区域上方形成层间介电层(ILD)370。ILD 370包括氧化硅、SiOC、SiOCN或SiCN或其它低k材料或多孔材料或任何其它合适的介电材料的一层或多层。在平坦化操作之后，去除伪栅极结构以制成栅极间隔。之后，在栅极间隔中，形成包括金属栅电极和栅极介电层(诸如高k介电层)的金属栅极结构330。
此外，在一些实施例中，在金属栅极结构330上方形成覆盖隔离层340，以获得图1C所示的FinFET结构。
在图1C中，切割金属栅极结构330、覆盖隔离层340、侧壁间隔件350和ILD 370的一部分以显示下面的结构。在一些实施例中，邻近的源极/漏极外延区域360彼此合并，并且在合并的源极/漏极区域上形成硅化物层。
图1C的金属栅极结构330、覆盖隔离层340、侧壁间隔件350、源极/漏极360和ILD370分别基本对应于图1A、图1B和图2A的金属栅极结构10、覆盖绝缘层20(见图2A)、侧壁间隔件30、源极/漏极区域50和第一层间介电层(ILD)40。
图2A至图7E示出了根据本发明的一个实施例的顺序半导体器件制造工艺的各个阶段。在图2A至图7E中，“A”图(图2A、图3A…)示出了对应于图1A的线X1-X1的截面图，并且“B”图(图2B、图3B…)示出了对应于图1A的线Y1-Y1的截面图。应该理解，可以在图2A至图7E所示的工艺之前、期间和之后提供额外的操作，并且对于方法的额外实施例，可以替换或消除一下描述的一些操作。操作/工艺的顺序可以互换。
在图2A和图2B中，覆盖绝缘层20分别设置在金属栅极结构10上方。
在一些实施例中，从高k介电层12的上表面至覆盖绝缘层20的底部的金属栅极结构10的厚度在从约15nm至50nm的范围内。在一些实施例中，覆盖绝缘层20的厚度在从约15nm至约30nm的范围内，并且在其它实施例中，在从约15nm至约20nm的范围内。在一些实施例中，覆盖绝缘层20设置在侧壁间隔件30上方，并且在其它实施例中，侧壁间隔件30设置在覆盖绝缘层20的侧壁上。
此外，如图2A和图2B所示，在形成ILD层40之前，在栅极结构和S/D外延区域50上方形成底部接触蚀刻停止层(B-CESL)33。在一些实施例中，B-CESL 33的膜厚度在从约1nm至约20nm的范围内。
覆盖绝缘层20包括诸如硅氮化物基材料(包括SiN、SiON、SiCN和SiOCN)或任何其它合适的介电材料的绝缘材料的一层或多层。侧壁间隔件30由与覆盖绝缘层20不同的材料制成并且包括诸如硅氮化物基材料(包括SiN、SiON、SiCN和SiOCN)或任何其它合适的介电材料的绝缘材料的一层或多层。B-CESL 33由与覆盖绝缘层20和侧壁间隔件30不同的材料制成，并且包括诸如硅氮化物基材料(包括SiN、SiON、SiCN和SiOCN)或任何其它合适的介电材料的绝缘材料的一层或多层。第一ILD层40包括氧化硅、SiOC、SiOCN或SiCN或其它低k材料或多孔材料或任何其它合适的介电材料的一层或多层。可以通过LPCVD(低压化学汽相沉积)、等离子体CVD、可流动CVD或其它合适的膜形成方法来形成第一ILD层40。
B-CESL 33的材料、侧壁间隔件30的材料、覆盖绝缘层20的材料和第一ILD层40的材料可以彼此不同，从而可以选择性地蚀刻这些层的每个。在一些实施例中，B-CESL 33由SiN或SiCN制成；侧壁间隔件30由SiO2、SiOCN、SiCN或SiON制成；覆盖绝缘层20由SiN或SiON制成；并且第一ILD层40由SiO2制成。
随后，如图3A和图3B所示，在图2A和图2B的结构上方形成掩模层60。掩模层60可以是单层或多层，并且可以包括光刻胶层、介电层、导电层、金属层和/或多晶或非晶层(例如，多晶/非晶Si)。在一些实施例中，掩模层60包括下介电层62、中层64和上介电层66。在某些实施例中，下层62是氧化硅层，中层64是TiN层并且上层66是氧化硅层。可以通过CVD、包括溅射的物理汽相沉积(PVD)或原子层沉积(ALD)或任何其它合适的膜形成方法来形成掩模层60的每层。
之后，如图4A和图4B所示，通过使用光刻和蚀刻操作，图案化上层66，并且通过使用图案化的上层66，图案化中层64。此外，通过使用图案化的中层64作为蚀刻掩模，图案化下层62和ILD层40，从而形成开口65。开口65在X方向上的宽度W1等于或大于邻近的金属栅极结构10之间的距离。开口65在Y方向上的宽度W2等于或小于邻近的S/D外延区域50之间的距离。
图4C至图4E是示出通过光刻操作制成开口65的掩模开口图案67的平面图。在图4C中，图4C基本对应于用图2A至图7E说明的实施例，三个掩模开口图案67分别设置为与S/D外延区域50和金属栅极结构10部分地重叠。在其它实施例中，如图4D所示，掩模开口图案67’设置为与邻近的栅极结构10和邻近的S/D外延区域50之间的两个间隔重叠。在其它实施例中，如图4E所示，掩模开口图案67”也设置为覆盖未在鳍结构5上形成S/D外延区域的区。在一些实施例中，可以一起使用多于一个开口图案67、67’和/或67”。
在ILD层40的蚀刻期间，也蚀刻了覆盖绝缘层20的上和/或侧部，在开口65的顶部附近产生在Z方向上延伸的V形状的开口。在一些实施例中，也部分地蚀刻了侧壁间隔件30和/或B-CESL 33。
在一些实施例中，如图4B所示，ILD层40的蚀刻基本停止在覆盖S/D外延层50的B-CESL 33处。具体地，当邻近的S/D外延层50之间的间隔较小时，蚀刻停止在B-CESL 33处。在这种情况下，ILD层40的部分保留在开口65的底部处。在一些实施例中，当邻近的S/D外延层50之间的间隔较大时，持续蚀刻并且停止在设置在隔离绝缘层15上的B-CESL 33处。在其它实施例中，没有ILD层40保留在随后形成的介电填充层70和隔离绝缘层15之间。
之后，图5A和图5B所示，在开口65中形成介电填充层70。介电填充层70由例如在稀释的HF湿蚀刻中对SiO2具有高蚀刻选择性(大于约10或约100)的SiN或SiCN制成。
可以通过CVD、包括溅射的PVD或ALD或任何其它合适的膜形成方法来形成介电填充层70。实施诸如化学机械抛光(CMP)的平坦化操作以去除位于ILD 40上方的过量的材料。如图5A和图5B所示，介电填充层70弥补了蚀刻的覆盖绝缘层20。如果在ILD蚀刻中也蚀刻了侧壁间隔件30和/或B-CESL 33，则介电填充层70可以弥补蚀刻的侧壁间隔件30和/或B-CESL 33。
如图5B所示，如上所述，当邻近的S/D外延层50之间的间隔较小时，则ILD层的部分41保留在介电填充层70的底部处。
之后，如图6A和图6B所示，通过使用湿蚀刻去除ILD层40。在一些实施例中，蚀刻溶液是稀释的HF(DHF)。在一些实施例中，DHF中HF的浓度为约1％。与干蚀刻不同，通过DHF湿蚀刻不会形成聚合物。因此，即使在较小的间隔/区中，DHF湿蚀刻也可以去除第一ILD层40。
在本实施例中，ILD层40由SiO2或硅氧化物基材料制成，而覆盖绝缘层20、B-CESL33和介电填充层70由SiN或SiCN制成。SiO2和SiN之间的1wt％-DHF的蚀刻选择性为约10，并且SiO2和SiCN之间的选择性为约100或更多。因此，可以通过DHF湿蚀刻完全地去除ILD层40而没有引起覆盖绝缘层20、B-CESL 33和/或介电填充层70的损坏。
下一步，如图7A至图7E所示，通过干蚀刻和/或湿蚀刻去除设置在S/D外延层50上方的B-CESL 33以形成接触开口，并且之后沉积用于硅化物形成的金属层81。可以通过CVD、PVD或ALD或任何其它合适的膜形成方法来形成金属层81。在形成金属层81之后，实施诸如快速热退火操作的热操作以由S/D外延区域50的组分(例如，Si)和金属层81的金属(例如，W、Ni、Co、Ti和/或Mo)形成硅化物层82。在一些实施例中，因为可以在金属层81的形成期间形成硅化物层，因此没有实施热操作。如图7B所示，在一些实施例中，金属层81保留在介电填充层70的侧部处而没有形成硅化物层。
在形成硅化物层82之后，在接触开口中填充导电材料84，从而形成S/D接触件80。
在一些实施例中，导电材料层84包括粘合(胶)层的毯式层和主体金属层。粘合层包括导电材料的一层或多层。在一些实施例中，粘合层包括在Ti层上形成的TiN层。可以使用任何合适的导电材料。在一些实施例中，TiN和Ti层的每个的厚度均在从约1nm至约5nm的范围内。可以通过CVD、PVD、ALD、电镀或它们的组合或其它合适的膜形成方法来形成粘合层。粘合层用于防止主体金属层剥离。在一些实施例中，没有使用粘合层并且直接在接触开口中形成主体金属层。在这种情况下，主体金属层与硅化物层82直接接触。
在一些实施例中，主体金属层是Co、W、Mo和Cu或任何其它合适的导电材料的一种。在一个实施例中，Cu用作主体金属层。可以通过CVD、PVD、ALD、电镀或它们的组合或其它合适的膜形成方法来形成主体金属层。
在形成导电材料层84之后，实施诸如化学机械抛光(CMP)或回蚀刻操作的平坦化操作，以去除过量的材料。
图7C至图7E示出了分别对应于图4C至图4E的平面图。介电填充层70沿着Y方向分隔开邻近的S/D接触件80。如图7C至图7E所示，介电填充层70在平面图中具有条状、岛状或L形状。在其它实施例中，介电填充层70在平面图中具有T形状或H形状。介电填充层70可以分隔开(物理或电)沿着Y方向布置的一对S/D接触件80，并且也可以覆盖不应形成S/D接触件80的部分。例如，介电填充层70设置在邻近的两个S/D外延层之间的间隔上方和/或其上没有形成S/D外延层的鳍结构上方。
应该理解，图7A至图7E中示出的器件经受进一步CMOS工艺以形成诸如互连金属层、介电层、钝化层等的各个部件。
图7F和图7G示出了根据本发明的其它实施例的半导体器件的截面图。
如上所述，用于形成开口65的蚀刻操作可以停止在不同的层处，并且ILD层40的一部分可以或可以不保留在随后形成的介电填充层70和隔离绝缘层15之间。
例如，在图7F中，ILD层40的一部分42保留在S/D外延层50下方的部分处，而介电填充层70与B-CESL 33直接接触。在图7G中，通过用于制成开口65的蚀刻完全地去除了两个邻近的S/D外延层50之间的ILD层40，并且介电填充层70完全地填充了S/D外延层50下方的部分并且与S/D外延层50和B-CESL 33直接接触。
本文描述的各个实施例或实例提供了超越现有技术的若干优势。例如，通过使用湿蚀刻，可以从诸如具有约10nm或更小直径的深接触孔的较小间隔中去除ILD材料(SiO2)。此外，可以通过介电填充层来修补由金属栅极的覆盖绝缘层的蚀刻引起的损失，可以增加金属栅极周围的电分离(绝缘)。
应该理解，不是所有优势都已经在此处讨论，没有特定的优势对于所述实施例或实例都是需要的，并且其它实施例或实例可以提供不同的优势。
根据本发明的一个方面，在制造半导体器件的方法中，在下面的结构上方形成层间介电(ILD)层。下面的结构包括栅极结构(每个均具有金属栅极和设置在金属栅极上方的覆盖绝缘层)、设置在两个邻近的栅极结构之间的源极/漏极外延层以及覆盖源极/漏极外延层的蚀刻停止层(ESL)。通过蚀刻在ILD层中形成开口。在开口中形成介电填充层。通过使用湿蚀刻，去除设置在源极/漏极外延层之上的ILD层。去除设置在源极/漏极外延层上的ESL，从而至少部分地暴露源极/漏极外延层。在暴露的源极/漏极外延层上方形成导电材料。
在上述方法中，其中，用于所述蚀刻停止层、所述覆盖绝缘层和所述介电填充层的介电材料与用于所述层间介电层的介电材料不同。
在上述方法中，其中，用于所述蚀刻停止层、所述覆盖绝缘层和所述介电填充层的介电材料与用于所述层间介电层的介电材料不同，用于所述蚀刻停止层的介电材料与用于所述介电填充层的介电材料相同。
在上述方法中，其中：所述蚀刻停止层由选自SiN和SiCN组成的组的至少一种制成，所述覆盖绝缘层由选自SiN和SiON组成的组的至少一种制成，所述介电填充层由选自SiN和SiCN组成的组的至少一种制成，以及所述层间介电层由SiO2制成。
在上述方法中，其中：所述蚀刻停止层由选自SiN和SiCN组成的组的至少一种制成，所述覆盖绝缘层由选自SiN和SiON组成的组的至少一种制成，所述介电填充层由选自SiN和SiCN组成的组的至少一种制成，以及所述层间介电层由SiO2制成，所述栅极结构的每个均还包括形成在所述金属栅极的相对侧上的侧壁间隔件，以及所述侧壁间隔件由选自SiCN和SiOCN组成的组的至少一种制成。
在上述方法中，其中，所述湿蚀刻使用稀释的HF。
在上述方法中，其中，在形成所述开口中，部分地去除所述覆盖绝缘层，并且在部分地去除所述覆盖绝缘层的所述覆盖绝缘层的部分上形成所述介电填充层。
在上述方法中，其中，在形成所述开口中，部分地去除所述覆盖绝缘层，并且在部分地去除所述覆盖绝缘层的所述覆盖绝缘层的部分上形成所述介电填充层，所述栅极结构的每个均还包括形成在所述金属栅极的相对侧上的侧壁间隔件，以及在形成所述开口中，部分地去除所述蚀刻停止层和所述侧壁间隔件，并且形成与所述侧壁间隔件接触的所述介电填充层。
在上述方法中，其中，通过使用包括TiN层的硬掩模图案的干蚀刻形成所述开口。
在上述方法中，其中：在形成所述开口之后，所述层间介电层的一部分保留在所述开口下方，以及在保留的层间介电层之上的所述开口中形成所述介电填充层。
在本发明的另一方面，在制造半导体器件的方法中，在下面的结构上方形成层间介电(ILD)层。下面的结构包括第一栅极结构至第四栅极结构，第一栅极结构至第四栅极结构的每个均具有金属栅极、设置在金属栅极的相对侧上的侧壁间隔件以及设置在金属栅极上方的覆盖绝缘层，其中，第一栅极结构至第四栅极结构沿着第一方向以这种顺序布置。下面的结构还包括第一源极/漏极(S/D)外延层和第二S/D外延层(两个均设置在第二栅极结构和第三栅极结构之间)以及覆盖第一S/D外延层和第二S/D外延层的蚀刻停止层(ESL)。通过蚀刻在包括第一S/D外延层和第二S/D外延层之间的区域的区上方的ILD层中形成第一开口。在第一开口中形成介电填充层。通过使用湿蚀刻，去除设置在第一S/D外延层和第二S/D外延层之上的ILD层，从而分别形成第二开口和第三开口，并且去除设置在第一栅极结构和第二栅极结构之间的ILD层，从而形成第四开口。去除设置在第一S/D外延层和第二S/D外延层上的ESL，从而至少部分地暴露第一S/D外延层和第二S/D外延层。在暴露的第一S/D外延层和第二S/D外延层上方形成导电材料，从而在第一S/D外延层上形成第一S/D接触件并且在第二S/D外延层上形成第二S/D接触件，并且从而在第四开口中形成接触条。
在上述方法中，其中，用于所述蚀刻停止层、所述覆盖绝缘层、所述侧壁间隔件和所述介电填充层的介电材料与用于所述层间介电层的介电材料不同。
在上述方法中，其中：所述蚀刻停止层由选自SiN和SiCN组成的组的至少一种制成，所述覆盖绝缘层由选自SiN和SiON组成的组的至少一种制成，所述侧壁间隔件由选自SiCN和SiOCN组成的组的至少一种制成，所述介电填充层由选自SiN和SiCN组成的组的至少一种制成，以及所述层间介电层由SiO2制成。
在上述方法中，其中，所述湿蚀刻使用稀释的HF。
在上述方法中，其中，在形成所述第一开口中，部分地去除所述覆盖绝缘层并且在所述覆盖绝缘层的去除部分上形成所述介电填充层。
在上述方法中，其中，在形成所述第一开口中，部分地去除所述覆盖绝缘层并且在所述覆盖绝缘层的去除部分上形成所述介电填充层，在形成所述第一开口中，部分地去除所述蚀刻停止层与所述第二栅极结构和所述第三栅极结构的侧壁间隔件，并且形成与所述第二栅极结构和所述第三栅极结构的侧壁间隔件接触的所述介电填充层。
17.根据权利要求11所述的方法，其中，通过使用包括TiN层的硬掩模图案的干蚀刻形成所述第一开口。
在上述方法中，其中：在形成所述第一开口之后，所述层间介电层的一部分保留在所述第一开口下方，以及在保留的层间介电层之上的所述第一开口中形成所述介电填充层。
在本发明的另一方面，半导体器件包括：隔离绝缘层；突出于隔离绝缘层的鳍结构；栅极结构，每个均具有金属栅极和设置在金属栅极上方的覆盖绝缘层；设置在两个邻近的栅极结构之间的第一源极/漏极外延层和第二源极/漏极外延层；以及设置在第一源极/漏极外延层上的第一导电接触件和设置在第二源极/漏极外延层上的第二导电接触件；设置在第一导电接触件和第二导电接触件之间的分离隔离区域；以及设置在分离隔离区域和隔离绝缘层之间的绝缘层。分离隔离区域由与绝缘层不同的材料制成。
在上述半导体器件中，其中，所述分离隔离区域由SiN和SiCN的一层或多层制成。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
在下面的结构上方形成层间介电(ILD)层，所述下面的结构包括：
栅极结构，每个均具有金属栅极和设置在所述金属栅极上方的覆盖绝缘层；
源极/漏极外延层，设置在两个邻近的所述栅极结构之间；和
蚀刻停止层(ESL)，覆盖所述源极/漏极外延层；
通过蚀刻在所述层间介电层中形成开口；
在所述开口中形成介电填充层；
通过使用湿蚀刻，去除设置在所述源极/漏极外延层之上的所述层间介电层；
去除设置在所述源极/漏极外延层上的所述蚀刻停止层，从而至少部分地暴露所述源极/漏极外延层；以及
在暴露的源极/漏极外延层上方形成导电材料。
2.根据权利要求1所述的方法，其中，用于所述蚀刻停止层、所述覆盖绝缘层和所述介电填充层的介电材料与用于所述层间介电层的介电材料不同。
3.根据权利要求2所述的方法，其中，用于所述蚀刻停止层的介电材料与用于所述介电填充层的介电材料相同。
4.根据权利要求1所述的方法，其中：
所述蚀刻停止层由选自SiN和SiCN组成的组的至少一种制成，
所述覆盖绝缘层由选自SiN和SiON组成的组的至少一种制成，
所述介电填充层由选自SiN和SiCN组成的组的至少一种制成，以及
所述层间介电层由SiO2制成。
5.根据权利要求4所述的方法，其中：
所述栅极结构的每个均还包括形成在所述金属栅极的相对侧上的侧壁间隔件，以及
所述侧壁间隔件由选自SiCN和SiOCN组成的组的至少一种制成。
6.根据权利要求1所述的方法，其中，所述湿蚀刻使用稀释的HF。
7.根据权利要求1所述的方法，其中，在形成所述开口中，部分地去除所述覆盖绝缘层，并且在部分地去除所述覆盖绝缘层的所述覆盖绝缘层的部分上形成所述介电填充层。
8.根据权利要求7所述的方法，其中：
所述栅极结构的每个均还包括形成在所述金属栅极的相对侧上的侧壁间隔件，以及
在形成所述开口中，部分地去除所述蚀刻停止层和所述侧壁间隔件，并且形成与所述侧壁间隔件接触的所述介电填充层。
9.一种制造半导体器件的方法，所述方法包括：
在下面的结构上方形成层间介电(ILD)层，所述下面的结构包括：
第一栅极结构至第四栅极结构，每个均具有金属栅极、设置在所述金属栅极的相对侧上的侧壁间隔件以及设置在所述金属栅极上方的覆盖绝缘层，所述第一栅极结构至所述第四栅极结构沿着第一方向以这种顺序布置；
第一源极/漏极(S/D)外延层和第二源极/漏极外延层，两个均设置在第二栅极结构和第三栅极结构之间；和
蚀刻停止层(ESL)，覆盖所述第一源极/漏极外延层和所述第二源极/漏极外延层；
通过蚀刻在包括所述第一源极/漏极外延层和所述第二源极/漏极外延层之间的区域的区上方的所述层间介电层中形成第一开口；
在所述第一开口中形成介电填充层；
通过使用湿蚀刻，去除设置在所述第一源极/漏极外延层和所述第二源极/漏极外延层之上的所述层间介电层，从而分别形成第二开口和第三开口，并且去除设置在所述第一栅极结构和所述第二栅极结构之间的所述层间介电层，从而形成第四开口；
去除设置在所述第一源极/漏极外延层和所述第二源极/漏极外延层上的所述蚀刻停止层，从而至少部分地暴露所述第一源极/漏极外延层和所述第二源极/漏极外延层；以及
在暴露的所述第一源极/漏极外延层和所述第二源极/漏极外延层上方形成导电材料，从而在所述第一源极/漏极外延层上形成第一源极/漏极接触件并且在所述第二源极/漏极外延层上形成第二源极/漏极接触件，并且从而在所述第四开口中形成接触条。
10.一种半导体器件，包括：
隔离绝缘层；
鳍结构，突出于所述隔离绝缘层；
栅极结构，每个均具有金属栅极和设置在所述金属栅极上方的覆盖绝缘层；
第一源极/漏极外延层和第二源极/漏极外延层，设置在两个邻近的所述栅极结构之间；
第一导电接触件和第二导电接触件，所述第一导电接触件设置在所述第一源极/漏极外延层上，并且所述第二导电接触件设置在所述第二源极/漏极外延层上；
分离隔离区域，设置在所述第一导电接触件和所述第二导电接触件之间；以及
绝缘层，设置在所述分离隔离区域和所述隔离绝缘层之间，
其中，所述分离隔离区域由与所述绝缘层不同的材料制成。
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US20200243344A1 (en) 2020-07-30
US10546755B2 (en) 2020-01-28
US10872781B2 (en) 2020-12-22
US10121675B2 (en) 2018-11-06
US20180190504A1 (en) 2018-07-05
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CN108257871B (zh) 2021-09-03
US20190013208A1 (en) 2019-01-10

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