TW201732897A - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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TW201732897A
TW201732897A TW105141858A TW105141858A TW201732897A TW 201732897 A TW201732897 A TW 201732897A TW 105141858 A TW105141858 A TW 105141858A TW 105141858 A TW105141858 A TW 105141858A TW 201732897 A TW201732897 A TW 201732897A
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insulating layer
layer
gate structure
gate
gate electrode
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TW105141858A
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Hsiang-Ku Shen
Yu-Lien Huang
Yen-Chieh Huang
Hui-Chi Chen
Jeng-Ya David Yeh
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Taiwan Semiconductor Mfg
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Abstract

一種半導體裝置包含第一閘極結構設置於基板上。第一閘極結構包含第一閘電極、第一覆蓋絕緣層設置於第一閘電極上，以及第一側壁間隔物設置於第一閘電極和第一覆蓋絕緣層的側表面上。半導體裝置更包含第一保護層形成於第一覆蓋絕緣層和至少一個第一側壁間隔物之上。第一保護層包含由氮氧化鋁(AlON)，氮化鋁(AlN)及非晶矽所組成的群組中選擇其中至少一種。

Description

半導體裝置的製造方法
本揭示實施例關於一種半導體裝置的製造方法，且特別係關於導電層位於源極/汲極區上之半導體的製造方法。
隨著半導體產業引進了具有更高效能及更強大功能性的新一代積體電路(IC)，目前已經採用了多層金屬佈線結構設置於下層電子裝置例如電晶體的上方。為了滿足更高速以及良好可靠性的需求，已經開發了形成金屬線的先進的方法及其結構。
根據本揭示實施例之一態樣，一種製造半導體裝置之方法，該方法包含：先形成一第一閘極結構及一第二閘極結構於一基板上，其中該第一閘極結構包含一第一閘電極，一第一覆蓋絕緣層設置於該第一閘電極上，以及一第一側壁間隔物設置於該第一閘電極以及該第一覆蓋絕緣層的側表面上，該第二閘極結構包含一第二閘電極，一第二覆蓋 絕緣層設置於該第二閘電極上，以及一第二側壁間隔物設置於該第二閘電極以及該第二覆蓋絕緣層的側表面上；接著，形成一第一源極/汲極區於該第一閘極結構以及該第二閘極結構之間的一區域內；形成一第一絕緣層於該第一源極/汲極區上以及該第一閘極結構及該第二閘極結構之間；形成該第一絕緣層後，使該第一及第二覆蓋絕緣層凹陷，以及使該第一及第二側壁間隔物凹陷，從而形成一第一隔間於該凹陷的第一覆蓋絕緣層及該凹陷的第一側壁間隔物上，以及一第二隔間於該凹陷的第二覆蓋絕緣層及該凹陷的第二側壁間隔物上；最後形成一第一保護層於該第一隔間中，及一第二保護層於該第二隔間中，其中該第一及第二保護層包含從以過渡金屬氮化物為基底的材料及非晶矽的組成中選擇至少一種。
5‧‧‧通道層
10‧‧‧金屬閘極結構
100‧‧‧第三層間介電層
105‧‧‧蝕刻停止層
110‧‧‧通孔塞
115‧‧‧通孔塞
12‧‧‧閘極介電層
120‧‧‧第一金屬線
125‧‧‧第二金屬線
14‧‧‧功函數調整層
16‧‧‧一層或多層
20‧‧‧覆蓋絕緣層
25‧‧‧凹陷間隔
30‧‧‧側壁間隔層
300‧‧‧基板
310‧‧‧鰭片結構
315‧‧‧通道區
320‧‧‧隔離絕緣層
330‧‧‧金屬閘極結構
340‧‧‧覆蓋絕緣層
35‧‧‧凹陷間隔
350‧‧‧層
360‧‧‧源極/汲極
370‧‧‧層間介電層
40‧‧‧第一層間介電層
50‧‧‧源極/汲極區
70‧‧‧保護層
80‧‧‧第二層間介電層
85‧‧‧接觸孔
90‧‧‧導電材料
95‧‧‧源極/汲極接觸
D1、D2‧‧‧深度
當結合隨附圖式進行閱讀時，本揭示之詳細描述將能被充分地理解。應注意，根據業界標準實務，各特徵並非按比例繪製且僅用於圖示目的。事實上，出於論述清晰之目的，可任意增加或減小各特徵之尺寸。
第1A圖繪示了根據本揭示一實施例於各階段之製造半導體裝置的平面示意圖(俯視圖)。第1B圖繪示了第1A圖之沿X1-X1線之剖面示意圖。第1C圖繪示了閘極結構放大圖。第1D圖繪示了根據本揭示一實施例於各階段之製造半導體裝置的透視示意圖。
第2圖至第8圖繪示了對應第1A圖之沿X1-X1線之於各階段製造半導體裝置的剖面示意圖。
第9圖至第10圖繪示了根據本揭示另一實施例之剖面示意圖。
第11圖至第12圖繪示了根據本揭示另一實施例之剖面示意圖。
應理解，以下揭示內容提供許多不同實施例或實例，以便實施本揭示之不同特徵。下文描述組件及排列之特定實施例或實例以簡化本揭示。當然，此等實例僅為示例性且並不欲為限制性。舉例而言，元件之尺寸並不受限於所揭示之範圍或值，但可取決於製程條件及/或裝置之所欲特性。此外，以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例，且亦可包括可在第一特徵與第二特徵之間插入形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。為了簡明性及清晰性，可以不同尺度任意繪製各特徵。
另外，為了便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述諸圖中所圖示之一元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所描繪之定向外，空間相對性術語意欲包含使用或操作中裝置之不同定向。設備可經其他方式定向(旋轉90度或處 於其他定向上)且因此可同樣解讀本文所使用之空間相對性描述詞。另外，術語「由……製成」可意謂「包含」或「由……組成」中任一者。
第1A圖及第1B圖顯示了根據本揭示之一實施例，其於半導體裝置之製造程序中的一階段示意圖。第1A圖繪示一平面(上視)圖，而第1B圖繪示第1A圖中沿線X1-X1的剖面圖。
第1A圖及第1B圖顯示了在形成金屬閘極結構後的半導體裝置結構。在第1A圖及第1B圖中，金屬閘極結構10形成於通道層5之上，例如為鰭結構的一部分，並且於金屬閘極結構10上形成一覆蓋絕緣層20。在一些實施例中，金屬閘極結構10的厚度範圍介於15奈米至50奈米。在一些實施例中，覆蓋絕緣層20的厚度範圍介於10奈米至30奈米，且在其他實施例中，其厚度範圍介於15奈米至20奈米。側壁間隔層30設置在金屬閘極結構10與覆蓋絕緣層20的側壁上。在一些實施例中，位於底部的側壁間隔層30的薄膜厚度範圍介於3奈米至15奈米，且在其他實施例中，其厚度範圍介於4奈米至10奈米。金屬閘極結構10、覆蓋絕緣層20以及側壁間隔層30的組合可以統稱為閘極結構。此外，在鄰近閘極結構形成源極/汲極區50，並且於閘極結構之間的間隙填充第一層間介電層(interlayer dielectric，ILD)40。
第1C圖是閘極結構的放大圖。金屬閘極結構10包含一層或多層16的金屬材料，例如Al，Cu，W，Ti，Ta， TiN，TiAl，TiAlC，TiAlN，TaN，NiSi，CoSi或其他導電材料。設置在通道層5與金屬閘極之間的閘極介電層12包含一層或多層金屬氧化物，例如高k金屬氧化物。用於高k介電質的金屬氧化物示例性的包含Li，Be，Mg，Ca，Sr，Sc，Y，Zr，Hf，Al，La，Ce，Pr，Nd，Sm，Eu，Gd，Tb，Dy，Ho，Er，Tm，Yb，Lu，以及/或其混和的氧化物。
在一些實施例中，一個或多個功函數調整層14介於閘極介電層12以及金屬材料16之間。功函數調整層14由導電材料製成，例如單層的TiN，TaN，TaAlC，TiC，TaC，Co，Al，TiAl，HfTi，TiSi，TaSi或TiAlC，或者上述材料中的兩種或更多種的多層。對於N型通道場效電晶體(n-channel FET)，使用TaN，TaAlC，TiN，TiC，Co，TiAl，HfTi，TiSi和TaSi中的一種或多種作為功函數調整層，對於P型通道場效電晶體(p-channel FET)，使用TiAlC，Al，TiAl，TaN，TaAlC，TiN，TiC和Co中的一種或多種作為功函數調整層。
覆蓋絕緣層20包含一個或多個絕緣材料層，例如包含以氮化矽為基礎的SiN，SiCN和SiOCN材料。側壁間隔層30與覆蓋絕緣層20是由不同的材料製成，且側壁間隔層包含一個或多層材料層，例如包含以氮化矽為基礎的SiN，SiON，SiCN和SiOCN材料。第一ILD層40包含一層或多層的絕緣材料，例如以氧化矽為基礎的材料，例如氧化矽(SiO2)以及SiON。
側壁間隔層30、覆蓋絕緣層20以及第一ILD層40彼此的材料皆不相同，使得這些層可以選擇性地被蝕刻。在一些實施例中，側壁間隔層30是由SiOCN，SiCN或SiON所製成，覆蓋絕緣層20是由SiN所製成，以及第一ILD層40是由所SiO2製成。
在一些實施例中，是採用閘極置換流程製造鰭式場效電晶體(fin field effect transistors，Fin FETs)。
第1D圖顯示了Fin FET結構的示例性透視圖。
首先，在一基板300上製造一鰭片結構310。鰭片結構310包含一底部區域與一頂部區域當作通道區315。舉例來說，基板是一具有雜質濃度範圍介於1×1015cm-3至1×1018cm-3的P型矽基板。在其他實施例中，基板是一具有雜質濃度範圍介於1×1015cm-3至1×1018cm-3的N型矽基板。又或者，基板可以包含其他元素的半導體，例如鍺；半導體化合物包含第IV-IV族的半導體化合物例如SiC及SiGe，第III-V族的半導體化合物例如GaAs，GaP，GaN，InP，InAs，InSb，GaAsP，AlGaN，AlInAs，AlGaAs，GaInAs，GaInP，以及/或GaInAsP；或其組合。在一實施例中，基板是絕緣層覆矽(silicon-on-insulator，SOI)基板的矽層。
在形成鰭片結構310後，在鰭片結構310上形成隔離絕緣層320。隔離絕緣層320包含通過低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)，電漿-CVD或可流動CVD而形成一層或多層的絕緣材料，例 如氧化矽，氮氧化矽或氮化矽。隔離絕緣層可以由一層或多層旋塗玻璃(spin-on-glass，SOG)，SiO，SiON，SiOCN，和/或氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass，FSG)而形成。
在鰭片結構上形成隔離絕緣層320之後，執行平坦化操作以移除隔離絕緣層320的一部分。平坦化操作可以包含化學機械拋光(chemical mechanical polishing，CMP)和/或回蝕刻(etch-back)製程。接著，進一步去除(凹陷)隔離絕緣層320，使得鰭片結構的上部區域得以露出。
在暴露的鰭片結構上方形成假性閘極結構。假性閘極結構包含由多晶矽製成的假性閘電極層以及假性閘極介電層。在假性閘電極層的側壁上形成包含一層或多層絕緣材料的側壁間隔層350。在形成假性閘極結構之後，尚未被假性閘極結構覆蓋的鰭片結構310凹陷在隔離絕緣層320上表面的下方。然後，通過使用外延生長法(epitaxial growth method)將源極/汲極區形成於凹陷的鰭片結構上。源極/汲極區可以包含應變材料以向通道區315施加應力。
接著，在假性閘極結構和源極/汲極區的上方形成層間介電層(ILD)370。經過平坦化操作之後，去除假性閘極結構以便形成閘極間隔。然後，在閘極間隔中，形成包含金屬閘電極和閘極介電層，例如高k介電層的金屬閘極結構330。此外，覆蓋絕緣層340形成於金屬閘極結構330的上方，以獲得如第1D圖所示之鰭式場效電晶體結構。在第 1D圖中，金屬閘極結構330，覆蓋絕緣層340，側壁330以極ILD370的一部分被切割以顯示下層的結構。
第1D圖中的金屬閘極結構330，覆蓋絕緣層340，側壁330，源極/汲極360以極ILD370實質上分別對應至第1A圖和第1B圖中的金屬閘極結構10，覆蓋絕緣層20，側壁間隔層30，源極/汲極區50以及第一層間介電層(ILD)40。
第2至10圖顯示出對應於第1A圖沿X1-X1線的示例性剖面圖。第1A圖繪示了根據本揭示之一實施例於各階段依序製造半導體裝置的示意圖。應當理解的是，可以提供額外的操作於第2至10圖之前，之間或之後，且部分如下描述的操作可以被該方法所附加之實施例進行置換或刪除。操作/製程的順序是可以相互交換的。
參照第2圖，藉由使用乾式和/或濕式蝕刻製程使覆蓋絕緣層20凹陷。由於構成覆蓋絕緣層20所使用的材料與側壁間隔層30及第一ILD層40不同，使得實質上可以選擇性蝕刻覆蓋絕緣層20。在一些實施例中，從第一ILD層40上表面量測的凹陷間隔25的深度D1在3奈米至10奈米的範圍內，並且在其他實施例中深度D1在4奈米至8奈米的範圍內。
參照第3圖，藉由使用乾式和/或濕式蝕刻製程使側壁間隔層30凹陷。由於構成側壁間隔層30所使用的材料與覆蓋絕緣層20及第一ILD層40不同，使得實質上可以選擇性蝕刻側壁間隔層30。在一些實施例中，從第一ILD 層40上表面量測的深度D2在3奈米至10奈米的範圍內，並且在其他實施例中深度D2在4奈米至8奈米的範圍內。
深度D1實質上與深度D2相同，並且如果不同，則差值在1奈米以內。應當注意的是，覆蓋絕緣層20可以在側壁間隔層30凹陷之後凹陷。
接著，如第4圖所示，保護層70形成於凹陷間隔35內。一層或多層的平坦層形成於如第3圖的結構上，並且執行平坦化操作，例如回蝕刻(etch-back)製程和/或化學機械拋光(CMP)製程。在平坦化操作之後，保護層70的厚度在一些實施例中從3奈米至10奈米的範圍內，並且在其他實施例中從4奈米至8奈米的範圍內。
保護層70是由相較於氧化矽基底材料具有高蝕刻電阻率的材料製成。在一些實施例中，使用過渡金屬氮化物基底材料，非晶矽或多晶矽作為保護層70。作為過渡金屬氮化物基底材料是使用AlON，AlN，TiN或TaN。此外，也可以使用鋁，鉭，鈦，鋯和鉿的氧化物作為保護層70。
參照第5圖，在形成保護層70之後，藉由合適的蝕刻製程去除第一ILD層40。
接著，參照第6圖，形成第二ILD80於第5圖的結構上。第二ILD80包含一個或多個絕緣材料層，其包含氧化矽基底材料，例如氧化矽(SiO2)和SiON或低k介電材料。
在形成第二ILD層80之後，通過使用微影製程及蝕刻製程形成接觸孔85，以暴露至少一個源極/汲極區 50。如第7圖所示，在蝕刻接觸孔期間，保護層70的一部分和側壁間隔層30的一部分也被蝕刻。然而，在蝕刻(氧化蝕刻)接觸孔期間由於保護層70相較於側壁間隔層具有較高的蝕刻電阻率，所以可以使側壁間隔層30被蝕刻掉一部分的量最小化。此外，由於保護層70，覆蓋絕緣層20在蝕刻接觸孔期間不會被蝕刻，因此，覆蓋絕緣層20的上端實質上保持直角。由於覆蓋絕緣層20部會被蝕刻，因此可以避免金屬閘極20與源極/汲極接觸95(參照第9及10圖)之間發生短路。
形成接觸孔85之後，形成導電材料90於第5圖的結構上。如第8圖所示，在第7圖的結構上形成一或多層的導電材料90，例如鎢，鈦，鈷，鉭，銅，鋁或鎳，或上述之矽化物，或其他合適的材料。繼續執行如CMP製程的平坦化操作，以獲得如第7圖的結構。兩個閘極結構之間由導電材料填充，從而形成與源極/汲極區50接觸的源極/汲極接觸95。
在此實施例中，保護層70不被移除並保留如第9圖所示。在這種情形下，在CMP製程中保護層70具有拋光停止層的功能，並且由諸如AlON或AlN的絕緣材料製成。
這些源極/汲極接觸95接觸源極/汲極區50。應注意的是，覆蓋絕緣層20的上表面，第二ILD層80的上表面(頂部)和源極/汲極接觸95實質上彼此齊平，亦即在同一平面上。
形成源極/汲極接觸95之後，在第9圖的結構上形成蝕刻停止層(etching-stop layer，ESL)105和第三ILD層100。接著，執行圖案化操作以形成通孔。通孔用一種或多種導電材料填充以形成通孔塞110、115，並且分別在通孔塞110、115上形成如第10圖所示之第一金屬線120和第二金屬線120。第一和第二金屬線及通孔塞可以通過雙鑲嵌法形成。在一些實施例中，不形成ESL105。
可以理解的是，如第10圖所示之裝置更進一步經歷CMOS製程以形成各種特徵，例如互連金屬層，介電層，鈍化層等。
第11及12圖繪示出根據本揭示之另一實施例的示例性剖面圖。
在上述的實施例中，保護層70保留在金屬閘極上方。在此實施例中，去除保護層70。
在形成如第8圖所示之導電材料90後，參照第11圖，執行平坦化操作以去除導電材料90和保護層70的上部。在這種情形下，覆蓋絕緣層20可以在CMP製程中當作拋光停止層。
接著，類似於第10圖，在形成源極/汲極接觸95之後，形成CESL105和第三ILD層100，並執行圖案化製程以形成通孔。通孔用一種或多種導電材料填充以形成通孔塞110、115，並且分別在通孔塞110及115上形成如第12圖所示之第一金屬線120和第二金屬線125。
可以理解的是，如第10圖所示之裝置更進一步經歷CMOS製程以形成各種特徵，例如互連金屬層，介電層，鈍化層等。
本文所描述之各實施例或實例提供優於現有技術的若干優勢。舉例而言，在本揭示實施例中，由於在金屬閘極，側壁間隔層和覆蓋絕緣層上形成保護層70，因此可避免在接觸孔蝕刻期間使得覆蓋絕緣層被蝕刻，從而防止金屬閘極和源極/汲極接觸。
應將理解，並非所有優勢皆需要在本文中論述，並非所有實施例或實例皆必須有特定優勢，而其他實施例或實例可提供不同優勢。
根據本揭示之一態樣，製造半導體裝置之方法包括：形成一第一閘極結構及一第二閘極結構於一基板上，其中該第一閘極結構包含一第一閘電極，一第一覆蓋絕緣層設置於該第一閘電極上，以及一第一側壁間隔物設置於該第一閘電極以及該第一覆蓋絕緣層的側表面上，該第二閘極結構包含一第二閘電極，一第二覆蓋絕緣層設置於該第二閘電極上，以及一第二側壁間隔物設置於該第二閘電極以及該第二覆蓋絕緣層的側表面上；形成一第一源極/汲極區於該第一閘極結構以及該第二閘極結構之間的一區域內；形成一第一絕緣層於該第一源極/汲極區上以及該第一閘極結構及該第二閘極結構之間；形成該第一絕緣層後，使該第一及第二覆蓋絕緣層凹陷，以及使該第一及第二側壁間隔物凹陷，從而形成一第一隔間於該凹陷的第一覆蓋絕緣層及該凹陷 的第一側壁間隔物上，以及一第二隔間於該凹陷的第二覆蓋絕緣層及該凹陷的第二側壁間隔物上；形成一第一保護層於該第一隔間中，及一第二保護層於該第二隔間中，其中該第一及第二保護層包含從以過渡金屬氮化物為基底的材料及非晶矽的組成中選擇至少一種。
上文概述若干實施例或實例之特徵，以使熟習此項技術者可更好地理解本揭示之態樣。熟習此項技術者應瞭解，可輕易使用本揭示作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施例或實例的相同目的及/或達成相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭示之精神及範疇，且可在不脫離本揭示之精神及範疇的情況下產生本文的各種變化、替代及更改。
5‧‧‧通道層
10‧‧‧金屬閘極結構
20‧‧‧覆蓋絕緣層
30‧‧‧側壁間隔層
40‧‧‧第一層間介電層
50‧‧‧源極/汲極區

Claims (1)

  1. 一種製造半導體裝置之方法，該方法包含：形成一第一閘極結構及一第二閘極結構於一基板上，該第一閘極結構包含一第一閘電極，一第一覆蓋絕緣層設置於該第一閘電極上，以及一第一側壁間隔物設置於該第一閘電極以及該第一覆蓋絕緣層的側表面上，該第二閘極結構包含一第二閘電極，一第二覆蓋絕緣層設置於該第二閘電極上，以及一第二側壁間隔物設置於該第二閘電極以及該第二覆蓋絕緣層的側表面上；形成一第一源極/汲極區於該第一閘極結構以及該第二閘極結構之間的一區域內；形成一第一絕緣層於該第一源極/汲極區上以及該第一閘極結構及該第二閘極結構之間；形成該第一絕緣層後，使該第一及第二覆蓋絕緣層凹陷，以及使該第一及第二側壁間隔物凹陷，從而形成一第一隔間於該凹陷的第一覆蓋絕緣層及該凹陷的第一側壁間隔物上，以及一第二隔間於該凹陷的第二覆蓋絕緣層及該凹陷的第二側壁間隔物上；以及形成一第一保護層於該第一隔間中，及一第二保護層於該第二隔間中，其中該第一及第二保護層包含從以過渡金屬氮化物為基底的材料及非晶矽的組成中選擇至少一種。
TW105141858A 2016-03-04 2016-12-16 半導體裝置的製造方法 TW201732897A (zh)

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10755926B2 (en) * 2017-11-20 2020-08-25 International Business Machines Corporation Patterning directly on an amorphous silicon hardmask
US10777455B2 (en) * 2019-01-29 2020-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-etching process for forming via opening in semiconductor device structure
US11652127B2 (en) * 2020-04-17 2023-05-16 Taiwan Semiconductor Manufacturing Company Limited Image sensor device and methods of forming the same
US11894435B2 (en) 2020-10-15 2024-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Contact plug structure of semiconductor device and method of forming same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US7910453B2 (en) 2008-07-14 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Storage nitride encapsulation for non-planar sonos NAND flash charge retention
US8310013B2 (en) 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8399931B2 (en) 2010-06-30 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout for multiple-fin SRAM cell
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8466027B2 (en) 2011-09-08 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation and associated devices
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8377779B1 (en) 2012-01-03 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices and transistors
US8735993B2 (en) 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8716765B2 (en) 2012-03-23 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8736056B2 (en) 2012-07-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Device for reducing contact resistance of a metal
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9153498B2 (en) * 2013-07-22 2015-10-06 Globalfoundries Inc. Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
US9076816B2 (en) * 2013-11-15 2015-07-07 Globalfoundries Inc. Method and device for self-aligned contact on a non-recessed metal gate
US9634115B2 (en) * 2014-06-11 2017-04-25 Globalfoundries Inc. Methods of forming a protection layer on a semiconductor device and the resulting device
US9312182B2 (en) * 2014-06-11 2016-04-12 Globalfoundries Inc. Forming gate and source/drain contact openings by performing a common etch patterning process
US9685532B2 (en) * 2015-03-24 2017-06-20 International Business Machines Corporation Replacement metal gate structures
US10163704B2 (en) * 2015-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US11088030B2 (en) * 2015-12-30 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same

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