CN107452795A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN107452795A
CN107452795A CN201710248982.XA CN201710248982A CN107452795A CN 107452795 A CN107452795 A CN 107452795A CN 201710248982 A CN201710248982 A CN 201710248982A CN 107452795 A CN107452795 A CN 107452795A
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Prior art keywords
layer
gate electrode
interval
electrode layer
recessed
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沈香谷
吕志伟
陈蕙祺
叶震亚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Inorganic Chemistry (AREA)

Abstract

在制造半导体器件的方法中，形成第一和第二栅极结构。第一(第二)栅极结构包括第一(第二)栅电极层和设置在第一(第二)栅电极层的两侧面上的第一(第二)侧壁间隔件。凹进第一和第二栅电极层并且凹进第一和第二侧壁间隔件，从而分别在凹进的第一和第二栅电极层和第一和第二侧壁间隔件上方形成第一间隔和第二间隔。在第一和第二间隔中分别形成第一和第二保护层。在第一和第二保护层中分别形成第一和第二蚀刻停止层。第一间隔的在第一侧壁间隔件之上的第一深度不同于第一间隔的在第一栅电极层之上的第二深度。本发明实施例涉及用于制造半导体器件的方法，更具体地，涉及用于位于栅电极和源极/漏极区域上方的绝缘层的结构及制造方法。

Description

半导体器件及其制造方法
技术领域
本发明实施例涉及一种用于制造半导体器件的方法，并且更具体地，涉及一种用于位于栅电极和源极/漏极区域上方的绝缘层的结构及制造方法。
背景技术
随着半导体器件的尺寸的减小，例如，自对准接触件(SAC)广泛地用于制造更靠近场效应晶体管(FET)中的栅极结构布置的源极/漏极(S/D)接触件。通常，通过图案化层间介电(ILD)层来制造SAC，在该层间介电层下面，接触蚀刻停止层(CESL)形成在具有侧壁间隔件的栅极结构上方。ILD层的最初的蚀刻停止在CESL处，并且然后，蚀刻CESL以形成SAC。随着器件密度增加(即，半导体器件的尺寸减小)，侧壁间隔件的厚度变得更薄，这可能导致S/D接触件与栅电极之间的短路。因此，需要提供具有S/D接触件与栅电极之间的改进的电隔离的SAC结构及制造工艺。
发明内容
根据本发明的一个实施例，提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成第一栅极结构和第二栅极结构，所述第一栅极结构包括第一栅电极层和设置在所述第一栅电极层的两侧面上的第一侧壁间隔件，所述第二栅极结构包括第二栅电极层和设置在所述第二栅电极层的两侧面上的第二侧壁间隔件；在所述第一栅极结构和所述第二栅极结构之间形成第一绝缘层；在形成所述第一绝缘层后，凹进所述第一栅电极层和所述第二栅电极层，并且凹进所述第一侧壁间隔件和所述第二侧壁间隔件，从而在凹进的所述第一栅电极层和凹进的所述第一侧壁间隔件上方形成第一间隔以及在凹进的所述第二栅电极层和凹进的所述第二侧壁间隔件上方形成第二间隔；在所述第一间隔中共形地形成第一保护层以及在所述第二间隔中共形地形成第二保护层；以及在所述第一保护层上形成第一蚀刻停止层以及在所述第二保护层上形成第二蚀刻停止层，其中，所述第一间隔的在所述第一侧壁间隔件之上的第一深度不同于所述第一间隔的在所述第一栅电极层之上的第二深度。
根据本发明的另一实施例，还提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成第一栅极结构和第二栅极结构，所述第一栅极结构包括第一栅电极层和设置在所述第一栅电极层的两侧面上的第一侧壁间隔件，所述第二栅极结构包括第二栅电极层和设置在所述第二栅电极层的两侧面上的第二侧壁间隔件；在所述第一栅极结构和所述第二栅极结构之间的区域中形成第一源极/漏极区域；在所述第一源极/漏极区域上方以及在所述第一栅极结构和所述第二栅极结构之间形成第一绝缘层；在形成所述第一绝缘层后，凹进所述第一栅电极层和所述第二栅电极层，以及凹进所述第一侧壁间隔件和所述第二侧壁间隔件，从而在凹进的所述第一栅电极层和凹进的所述第一侧壁间隔件上方形成第一间隔并且在所述凹进的所述第二栅电极层和凹进的所述第二侧壁间隔件上方形成第二间隔；在所述第一间隔中共形地形成第一保护层以及在所述第二间隔中共形地形成第二保护层；在所述第一保护层上形成第一蚀刻停止层以及在所述第二保护层上形成第二蚀刻停止层；去除设置在所述第一源极/漏极区域上方的所述第一绝缘层，从而形成源极/漏极间隔；用导电材料填充所述源极/漏极间隔；凹进填充的所述导电材料，从而形成源极/漏极接触层；以及在所述源极/漏极接触层上方形成第三蚀刻停止层。
根据本发明的又一实施例，还提供了一种半导体器件，包括：栅极结构，所述栅极结构包括：栅电极层；设置在所述栅电极层上方的第一盖绝缘层；设置在所述第一盖绝缘层上方的第二盖绝缘层；以及设置在所述栅电极层的两侧面上的第一侧壁间隔件，其中，所述第一盖绝缘层在所述第一侧壁间隔件上方延伸并且所述第一盖绝缘层设置在所述第一侧壁间隔件上。
附图说明
当结合附图进行阅读时，从以下详细描述可更好地理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A示出了根据本发明的一个实施例的示出半导体器件的顺序制造工艺的各个阶段的其中一个的示例性平面图(从上面观看)。
图1B示出了沿着图1A的线X1-X1的示例性截面图。
图1C是栅极结构的放大视图。
图1D示出的根据本发明的一个实施例的示出半导体器件的顺序制造工艺的各个阶段的其中一个的示例性立体图。
图2至图16示出了根据本发明的一个实施例的对应于图1A的线X1-X1的示例性截面图，示出了半导体器件的顺序制造工艺的各个阶段。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等间隔相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，间隔相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的间隔相对描述符可以同样地作出相应的解释。
图1A和图1B示出了根据本发明的一个实施例的示出半导体器件的顺序制造工艺的其中一个阶段。图1A示出了平面(顶视)图并且图1B示出了沿着图1A的线X1-X1的截面图。
图1A和图1B示出了在形成金属栅极结构后半导体器件的结构。在图1A和图1B中，金属栅极结构10形成在沟道层5上方，例如，金属栅极结构10是鳍结构的部分。在一些实施例中，金属栅极结构10的厚度在从约15nm至约50nm的范围内。侧壁间隔件30提供在金属栅极结构10的侧壁上。在一些实施例中，侧壁间隔件30的在侧壁间隔件底部处的薄膜厚度在从约3nm至约15nm的范围内，并且在其它实施例中，该薄膜厚度在从约4nm至约10nm的范围内。金属栅极结构10和侧壁间隔件30的组合可以统称为栅极结构。此外，邻近于栅极结构形成源极/漏极区域50或者在栅极结构之间形成源极/漏极区域50，并且以第一层间介电(ILD)层40填充在栅极结构之间的间隔。在本发明中，源极和栅极可以交换使用，并且源极/漏极(或者S/D)可以指的是源极和漏极的其中一个或者两个。
图1C是栅极结构的放大视图。金属栅极结构10包括金属材料的一层或多层16，金属材料诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi、CoSi、其它导电材料。栅极介电层12设置在沟道层5和金属栅极之间，金属栅极包括诸如高k金属氧化物的金属氧化物的一层或者多层。用于高k介电质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物和/或它们的混合物。
在一些实施例中，一个或多个功函调整层14插在栅极介电层12和金属材料16之间。功函数调整层14由导电材料制成，导电材料诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或者TiAlC的单层，或者这些材料的两层或者多层。对于n沟道FET，TaN、TiAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种用作功函调整层，而对于p沟道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种用作功函调整层。
侧壁间隔件30包括绝缘材料的一层或者多层。绝缘材料诸如基于氧化硅的材料或者基于氮化硅的材料，包括SiO2、SiN、SiON、SiCN以及SiOCN。第一ILD层40包括诸如基于氧化硅的材料(诸如二氧化硅(SiO2)和SiON)的绝缘材料的一层或者多层。
侧壁间隔件30的材料和第一ILD层40的材料是互相不同的，使得每层可以选择性蚀刻。在一个实施例中，侧壁间隔件30由SiOCN、SiCN或者SiON制成，而第一ILD层40由SiO2制成。
在这个实施例中，可以通过采用栅极替代工艺制造鳍式场效应晶体管(FinFET)。
图1D示出了FinFET结构的示例性立体图。
首先，在衬底300上方制造鳍结构310。鳍结构包括底部区域和作为沟道区315的上部区域。例如，衬底是具有在从约1×1015cm-3至约1×1018cm-3的范围内的杂质浓度的p型硅衬底。在其他的实施例中，衬底是具有在从约1×1015cm-3至约1×1018cm-3的范围内的杂质浓度的n型硅衬底。可选地，衬底可以包括诸如锗的其他元素半导体、化合物半导体或者它们的组合，化合物半导体包括诸如SiC和SiGe的IV-IV族化合物半导体，诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V族化合物半导体。在一个实施例中，衬底是SOI(绝缘体上硅)衬底的硅层。
在形成鳍结构310之后，在鳍结构310上方形成隔离绝缘层320。隔离绝缘层320包括通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的绝缘材料(如氧化硅、氮氧化硅或氮化硅)的一层或多层。隔离绝缘层可以由旋涂玻璃(SOG)、SiO、SiON、SiOCN和/或掺杂氟的硅酸盐玻璃(FSG)的一层或多层形成。
在鳍结构上方形成隔离绝缘层320后，实施平坦化操作以移除隔离绝缘层320的部分。平坦化操作可以包括化学机械抛光(CMP)和/或回蚀刻工艺。然后，进一步去除(凹进)隔离绝缘层320，使得暴露鳍结构的上部区域。
伪栅极结构GATE形成在暴露的鳍结构上方。伪栅极结构包括由多晶硅制成的伪栅电极层以及包括伪栅极介电层。侧壁间隔件350包括绝缘材料的一层或者多层，侧壁间隔件350也形成在伪栅电极层的侧壁上。在形成伪栅极结构之后，使未被伪栅极结构覆盖的鳍结构310凹进至隔离绝缘层320的上表面的下方。然后，通过使用外延生长方法在凹进的鳍结构上方形成源极/漏极区域360。源极/漏极区域可以包括应变材料以施加应力到沟道区315。
然后，层间介电(ILD)层370形成在伪栅极结构和源极/漏极区域上方。在平坦化操作之后，去除伪栅极结构以用作栅极间隔。然后，在栅极间隔中，形成包括金属栅电极以及包括诸如高k介电层的栅极介电层的金属栅极结构330，以获得在图1D中示出的FinFET结构。在图1D中，切割(cut)金属栅极结构330、侧壁330以及ILD层370的部分以示出下部的结构。
图1D的金属栅极结构330、侧壁330、源极/漏极360以及ILD层370基本上分别对应于图1A和图1B的金属栅极结构10、侧壁间隔件30、源极/漏极区域50以及第一ILD层40。
图2至图16根据本发明的一个实施例示出的沿着图1A的线X1-X1的示例性截面图，描述了半导体器件的顺序制造工艺的各个阶段。应该理解，可以在通过图2至图16示出的工艺之前、期间和之后提供额外的操作，并且对于该方法的额外实施例，下文描述的一些操作可以被替换或消除。操作/工艺的顺序可以互换。
如图2中示出的，通过使用干和/或湿蚀刻工艺凹进栅电极层10。在一些实施例中，在从第一ILD层40的上表面测量的凹进间隔25的在栅电极10之上的深度D1在从约10nm至约25nm的范围内，并且在其它实施例中，该深度D1在从约15nm至约20nm的范围内。
如图3中示出的，通过使用干和/或湿蚀刻工艺凹进侧壁间隔件30以加宽凹进间隔25。由于侧壁间隔件30由不同于第一ILD层40的材料制成，可以基本上可选择性地蚀刻侧壁间隔件层30。在一些实施例中，在从第一ILD层40的上表面测量的凹进间隔25的在侧壁间隔件30之上的深度D2在从约5nm至约20nm的范围内，并且在其它实施例中，该深度D2在从约8nm至约15nm的范围内。
深度D2不同于深度D1。在一些实施例中，深度D2小于深度D1。换句话说，在图3中，侧壁间隔件30的顶部高于栅电极10的顶部。在一些实施例中，在深度D2和深度D1(即侧壁间隔件30和栅电极10的高度的不同)之间的高度差在从约5nm至约15nm的范围内，并且在其它实施例中，该高度差在从约8nm至约12nm的范围内。
需要注意的是，可以在凹进侧壁间隔件30后凹进栅电极层10。
然后，如图4中示出，保护层60共形地形成在凹进间隔25中。保护层60在随后的蚀刻操作中保护侧壁间隔件30。此外，设置在栅电极10上方的保护层60用作栅极结构中的盖绝缘层。绝缘材料的一层或者多层毯状层共形地形成在图3中示出的结构上方。如图4中示出的，保护层60部分地填充间隔25。在一些实施例中，保护层60的厚度在从约3nm至约5nm的范围内。
在形成保护层60后，第一蚀刻停止层(ESL)70形成在保护层60上。绝缘材料的一层或者多层毯状层共形地形成在保护层60上。然后，如图6中示出的，施加诸如回蚀工艺和/或化学机械抛光(CMP)工艺的平坦化操作以去除保护层60的上部和第一ESL 70的上部。
在一些实施例中，在平坦化操作之后，第一ESL 70在从约40nm至约50nm的范围内，并且在特定的实施例中，第一ESL 70在从约20nm至约30nm的范围内。
保护层60和第一ESL 70由不同的绝缘材料制成。保护层60由对基于硅的绝缘材料具有高抗蚀刻性的材料制成。在一些实施例中，诸如AlO、AlON和/或AlN的基于铝的绝缘材料用作保护层60，并且诸如SiN和/或SiON的基于氮化硅的材料用作第一ESL 70。设置在栅电极10上方的第一ESL 70用作栅极结构中的另一盖绝缘层。
如图7中示出的，在平坦化操作之后，通过使用合适的蚀刻操作去除设置在源极/漏极结构50上方的第一ILD层40。
随后，在图7的结构的上方形成导电材料。在图7的结构的上方形成诸如钨、钛、钴、钽、铜、铝、镍或者它们的硅化物或者其它合适的材料的导电材料的一层或者多层。然后，实施诸如CMP工艺的平坦化操作以获得图8的结构。在两个栅极结构之间的间隔填充导电材料，从而形成了与源极/漏极区域50接触的源极/漏极接触层80。
然后，如图9中示出的，通过使用合适的蚀刻操作凹进源极/漏极接触层80。如图10中示出的，用绝缘材料填充通过凹进源极/漏极接触层80形成的间隔，从而形成第二ESL90。
第二ESL 90包括诸如SiC和/或SiOC的基于碳化硅的绝缘材料的一层或多层。绝缘材料的毯状层形成在图9的结构的上方，并且然后实施诸如CMP工艺的平坦化操作以获得图10的结构。
此外，如图11中示出的，在图10的结构的上方形成第二ILD 100。第二ILD层100包括绝缘材料的一层或者多层，绝缘材料包括诸如二氧化硅(SiO2)和SiON的基于氧化硅的材料或者低k介电材料。在一些实施例中，例如，在形成第二ILD层100之前形成第三ESL 105，第三ESL 105由SiN、SiON和/或SiOCN制成。
在形成第二ILD层100后，在第二ILD层100上方形成第一掩模图案110，第一掩模图案110具有位于栅电极10上方的开口。如图12中示出的，通过使用第一掩模图案110作为蚀刻掩模，使用蚀刻操作蚀刻第二ILD层100、第三ESL105以及第一ESL 70以形成接触孔112。在该蚀刻操作中，在栅电极10上形成的保护层60用作蚀刻停止层，并且第一ESL 70的蚀刻基本上停止在保护层60处。第一掩模图案110包括抗蚀图案和硬掩膜图案的至少一种。硬掩模图案可以包括一种或者多种介电材料、诸如TiN或者TaN的金属氮化物或者诸如TiO2的金属氧化物。
随后，如图13中示出的，进一步蚀刻保护层60以完成形成接触孔112。在一些实施例中，保护层60的蚀刻包括湿蚀刻工艺。然后，去除第一掩模图案110。在一些实施例中，在保护层60的蚀刻之前，去除第一掩模层110。
如图14中示出的，第二掩模图案115形成在第二ILD层100上方，第二掩模图案115具有位于源极/漏极接触层80上方的开口。如图14中示出的，通过使用第二掩模图案115作为蚀刻掩模，使用蚀刻操作蚀刻第二ILD层100、第三ESL105以及第二ESL 90以形成接触孔117。在该蚀刻操作中，基本上不蚀刻保护层60(和侧壁间隔件30)，因此可以以自对准方式形成接触孔117。第二掩模图案115包括抗蚀图案和硬掩膜图案的至少一种。硬掩模图案可以包括一种或者多种介电材料、诸如TiN或者TaN的金属氮化物或者诸如TiO2的金属氧化物。然后，如图15中示出的，去除第二掩模图案115。在一些实施例中，在第二ESL 90的蚀刻期间，去除第二掩模层115。
在一些实施例中，在形成接触孔117后形成接触孔112。
如图16中示出的，随后以一种或者多种导电材料填充接触孔112和117以形成通孔插塞120和122。随后，在图15的结构的上方形成导电材料的毯状层，并且然后对毯状层施加诸如CMP的平坦化操作。
应该理解，图16所示的器件还经受CMOS工艺以形成诸如互连金属层、介电层、钝化层等的各种部件。
本文描述的各个实施例或实例提供若干优于现有技术的优点。例如，在本发明中，利用简化的制造操作在栅电极上方形成两个盖层是可能的，并且两个盖层用作接触蚀刻停止层。此外，两个盖层的其中一个也作为保护层以用于侧壁间隔件，这也可以简化制造操作。通过使用用于保护层、第一蚀刻停止层(盖层)以及第二蚀刻停止层的不同的材料，在接触孔蚀刻操作期间增加蚀刻选择性是可能的。
应该理解，本文不必讨论所有优点，没有特定优势是所有实施例或实例都必需的，并且其他实施例或实例可提供不同优点。
根据本发明的一个方面，在制造半导体器件的方法中，在衬底上方形成了第一栅极结构和第二栅极结构。第一栅极结构包括第一栅电极层和设置在第一栅电极层的两侧面上的第一侧壁间隔件，第二栅极结构包括第二栅电极层和设置在第二栅电极层的两侧面上的第二侧壁间隔件。在第一栅极结构和第二栅极结构之间形成第一绝缘层。在形成第一绝缘层后，凹进第一和第二栅电极层，并且凹进第一和第二侧壁间隔件，从而在凹进的第一栅电极层和凹进的第一侧壁间隔件上方形成第一间隔并且在凹进的第二栅电极层和凹进的第二侧壁间隔件上方形成第二间隔。在第一间隔中共形地形成第一保护层同时在第二间隔中共形地形成第二保护层。在第一保护层上形成第一蚀刻停止层同时在第二保护层上形成第二蚀刻停止层。第一间隔的在第一侧壁间隔件之上的第一深度不同于第一间隔的在第一栅电极层上方之上的第二深度。
根据本发明的另一个方面，在制造半导体器件的方法中，在衬底上方形成了第一栅极结构和第二栅极结构。第一栅极结构包括第一栅电极层和设置在第一栅电极层的两侧面上的第一侧壁间隔件，第二栅极结构包括第二栅电极层和设置在第二栅电极层的两侧面上的第二侧壁间隔件。在第一栅极结构和第二栅极结构之间的区域中形成第一源极/漏极区域。在第一栅极结构和第二栅极结构之间和在第一源极/漏极区域上方形成第一绝缘层。在形成第一绝缘层后，凹进第一和第二栅电极层，并且凹进第一和第二侧壁间隔件，从而形成在凹进的第一栅电极层和凹进的第一侧壁间隔件上方的第一间隔并且在凹进的第二栅电极层和凹进的第二侧壁间隔件上方的第二间隔。在第一间隔中均匀形成第一保护层同时在第二间隔中均匀形成第二保护层。在第一保护层上形成第一蚀刻停止层同时在第二保护层上形成第二蚀刻停止层。去除设置在第一源极/漏极区域上方的第一绝缘层，从而形成源极/漏极间隔。以导电材料填充源极/漏极间隔。凹进填充的导电材料，从而形成源极/漏极接触层。在源极/漏极接触层上方形成第三蚀刻停止层。
根据本发明的另一方面，一种半导体器件，包括栅极结构。栅极结构，栅极结构包括：栅电极层；设置在栅电极层上方的第一盖绝缘层；设置在第一盖绝缘层上方的第二盖绝缘层；以及设置在栅电极层的两侧面上的第一侧壁间隔件。第一盖绝缘层在第一侧壁间隔件上方延伸并且第一盖绝缘层设置在第一侧壁间隔件上。
根据本发明的一个实施例，提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成第一栅极结构和第二栅极结构，所述第一栅极结构包括第一栅电极层和设置在所述第一栅电极层的两侧面上的第一侧壁间隔件，所述第二栅极结构包括第二栅电极层和设置在所述第二栅电极层的两侧面上的第二侧壁间隔件；在所述第一栅极结构和所述第二栅极结构之间形成第一绝缘层；在形成所述第一绝缘层后，凹进所述第一栅电极层和所述第二栅电极层，并且凹进所述第一侧壁间隔件和所述第二侧壁间隔件，从而在凹进的所述第一栅电极层和凹进的所述第一侧壁间隔件上方形成第一间隔以及在凹进的所述第二栅电极层和凹进的所述第二侧壁间隔件上方形成第二间隔；在所述第一间隔中共形地形成第一保护层以及在所述第二间隔中共形地形成第二保护层；以及在所述第一保护层上形成第一蚀刻停止层以及在所述第二保护层上形成第二蚀刻停止层，其中，所述第一间隔的在所述第一侧壁间隔件之上的第一深度不同于所述第一间隔的在所述第一栅电极层之上的第二深度。
在上述方法中，所述第一间隔的在所述第一侧壁间隔件之上的所述第一深度小于所述第一间隔的在所述第一栅电极层之上的所述第二深度。
在上述方法中，所述第一深度和所述第二深度之间的差值在从5nm至15nm范围内。
在上述方法中，首先凹进所述第一栅电极层和所述第二栅电极层，以及然后凹进所述第一侧壁间隔件和所述第二侧壁间隔件。
在上述方法中，其中：所述第一保护层和所述第二保护层由第一绝缘材料制成，并且所述第一蚀刻停止层和所述第二蚀刻停止层由不同于所述第一绝缘材料的第二绝缘材料制成。
在上述方法中，在形成所述第一保护层和所述第二保护层以及形成所述第一蚀刻停止层和所述第二蚀刻停止层中：共形地形成所述第一绝缘材料的毯状层以部分地填充所述第一间隔和所述第二间隔；在所述第一绝缘材料的所述毯状层上形成所述第二绝缘材料的毯状层以完全填充所述第一间隔和所述第二间隔；以及实施平坦化操作以去除所述第一绝缘材料的所述毯状层的上部和所述第二绝缘材料的所述毯状层的上部。
在上述方法中，其中：所述第一保护层和所述第二保护层由基于铝的绝缘材料制成，以及所述第一蚀刻停止层和所述第二蚀刻停止层由基于氮化硅的绝缘材料制成。
在上述方法中，其中：所述第一保护层设置在所述第一侧壁间隔件和所述第一栅电极层上，并且所述第一蚀刻停止层设置在所述第一栅电极层之上。
根据本发明的另一实施例，还提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成第一栅极结构和第二栅极结构，所述第一栅极结构包括第一栅电极层和设置在所述第一栅电极层的两侧面上的第一侧壁间隔件，所述第二栅极结构包括第二栅电极层和设置在所述第二栅电极层的两侧面上的第二侧壁间隔件；在所述第一栅极结构和所述第二栅极结构之间的区域中形成第一源极/漏极区域；在所述第一源极/漏极区域上方以及在所述第一栅极结构和所述第二栅极结构之间形成第一绝缘层；在形成所述第一绝缘层后，凹进所述第一栅电极层和所述第二栅电极层，以及凹进所述第一侧壁间隔件和所述第二侧壁间隔件，从而在凹进的所述第一栅电极层和凹进的所述第一侧壁间隔件上方形成第一间隔并且在所述凹进的所述第二栅电极层和凹进的所述第二侧壁间隔件上方形成第二间隔；在所述第一间隔中共形地形成第一保护层以及在所述第二间隔中共形地形成第二保护层；在所述第一保护层上形成第一蚀刻停止层以及在所述第二保护层上形成第二蚀刻停止层；去除设置在所述第一源极/漏极区域上方的所述第一绝缘层，从而形成源极/漏极间隔；用导电材料填充所述源极/漏极间隔；凹进填充的所述导电材料，从而形成源极/漏极接触层；以及在所述源极/漏极接触层上方形成第三蚀刻停止层。
在上述方法中，所述第一间隔的在所述第一侧壁间隔件之上的第一深度小于所述第一间隔的在所述第一栅电极层之上的第二深度。
在上述方法中，其中：所述第一保护层和所述第二保护层由第一绝缘材料制成，所述第一蚀刻停止层和所述第二蚀刻停止层由不同于所述第一绝缘材料的第二绝缘材料制成，以及所述第三蚀刻停止层由不同于所述第一绝缘材料和所述第二绝缘材料的第三绝缘材料制成。
在上述方法中，在形成所述第一保护层和所述第二保护层以及在形成所述第一蚀刻停止层和所述第二蚀刻停止层中：共形地形成所述第一绝缘材料的毯状层以部分地填充所述第一间隔和所述第二间隔；在所述第一绝缘材料的所述毯状层上形成所述第二绝缘材料的毯状层以完全填充所述第一间隔和所述第二间隔；以及实施平坦化操作以去除所述第一绝缘材料的所述毯状层的上部和所述第二绝缘材料的所述毯状层的上部。
在上述方法中，其中：所述第一保护层和所述第二保护层由AlO、AlON和AlN的至少一种制成，所述第一蚀刻停止层和所述第二蚀刻停止层由SiN和SiON的至少一种制成，以及所述第三蚀刻停止层由SiC和SiOC的至少一种制成。
在上述方法中，首先凹进所述第一栅电极层和所述第二栅电极层，并且然后凹进所述第一侧壁间隔件和所述第二侧壁间隔件。
在上述方法中，还包括在形成所述第三蚀刻停止层之后形成第二绝缘层。
在上述方法中，还包括：通过使用第一蚀刻工艺图案化所述第二绝缘层和所述第一蚀刻停止层；以及通过使用第二蚀刻工艺图案化所述第一保护层，从而在所述第一栅电极层上方形成接触孔，其中，所述第一保护层用作蚀刻停止层以用于所述第一蚀刻工艺。
在上述方法中，所述第二蚀刻工艺包括湿蚀刻工艺。
在上述方法中，还包括图案化所述第二绝缘层和所述第三绝缘层，从而在所述源极/漏极接触层上方形成接触孔。
根据本发明的又一实施例，还提供了一种半导体器件，包括：栅极结构，所述栅极结构包括：栅电极层；设置在所述栅电极层上方的第一盖绝缘层；设置在所述第一盖绝缘层上方的第二盖绝缘层；以及设置在所述栅电极层的两侧面上的第一侧壁间隔件，其中，所述第一盖绝缘层在所述第一侧壁间隔件上方延伸并且所述第一盖绝缘层设置在所述第一侧壁间隔件上。
在上述半导体器件中，所述第一盖绝缘层由基于铝的绝缘材料制成，以及所述第二盖绝缘层由基于氮化硅的绝缘材料制成。上面论述了若干实施例的部件，以便本领域技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (1)

1.一种制造半导体器件的方法，所述方法包括：
在衬底上方形成第一栅极结构和第二栅极结构，所述第一栅极结构包括第一栅电极层和设置在所述第一栅电极层的两侧面上的第一侧壁间隔件，所述第二栅极结构包括第二栅电极层和设置在所述第二栅电极层的两侧面上的第二侧壁间隔件；
在所述第一栅极结构和所述第二栅极结构之间形成第一绝缘层；
在形成所述第一绝缘层后，凹进所述第一栅电极层和所述第二栅电极层，并且凹进所述第一侧壁间隔件和所述第二侧壁间隔件，从而在凹进的所述第一栅电极层和凹进的所述第一侧壁间隔件上方形成第一间隔以及在凹进的所述第二栅电极层和凹进的所述第二侧壁间隔件上方形成第二间隔；
在所述第一间隔中共形地形成第一保护层以及在所述第二间隔中共形地形成第二保护层；以及
在所述第一保护层上形成第一蚀刻停止层以及在所述第二保护层上形成第二蚀刻停止层，
其中，所述第一间隔的在所述第一侧壁间隔件之上的第一深度不同于所述第一间隔的在所述第一栅电极层之上的第二深度。
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