TWI650869B - 半導體裝置與其形成方法 - Google Patents
半導體裝置與其形成方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims description 34
- 239000010410 layer Substances 0.000 claims abstract description 183
- 125000006850 spacer group Chemical group 0.000 claims abstract description 89
- 239000011241 protective layer Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 23
- 239000000203 mixture Substances 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 description 28
- 239000002184 metal Substances 0.000 description 28
- 238000005530 etching Methods 0.000 description 11
- 239000011810 insulating material Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910010038 TiAl Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
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- 229910010041 TiAlC Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
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- 229910004191 HfTi Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
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- 229910008484 TiSi Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
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- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910052689 Holmium Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052765 Lutetium Inorganic materials 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910052777 Praseodymium Inorganic materials 0.000 description 1
- 229910052772 Samarium Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910052771 Terbium Inorganic materials 0.000 description 1
- 229910052775 Thulium Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
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- 230000009969 flowable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
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- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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Abstract
半導體裝置,包括第一閘極結構位於基板上,並沿著第一方向延伸。第一閘極結構包括第一閘極、第一絕緣蓋層位於第一閘極上、多個第一側壁間隔物位於第一閘極與第一絕緣蓋層之相反兩側面上、以及多個第二側壁間隔物位於第一側壁間隔物上。半導體裝置亦包括第一保護層形成於第一絕緣蓋層、第一側壁間隔物、與第二側壁間隔物上。第一保護層沿著第二方向的剖面為π形,其具有頂部與兩個腳部,且第二方向垂直於第一方向。
Description
本揭露實施例關於半導體裝置的形成方法,更特別關於源極/汲極區上的自對準接點結構與其形成方法。
為縮小半導體裝置尺寸,常採用自對準接點(SAC)以形成源極/汲極(S/D)接點,其設置於靠近場效電晶體(FET)中的閘極結構。SAC的形成方法一般為圖案化層間介電(ILD)層,而ILD層下形成有接點蝕刻停止層(CESL),且CESL位於具有側壁間隔物的閘極結構上。對ILD層進行的初始蝕刻將止於CESL,接著再蝕刻CESL以形成SAC。當裝置密度增加時(比如半導體裝置的尺寸縮小),側壁間隔物的厚度將變薄而導致S/D接點與閘極之間的短路。綜上所述,目前亟需SAC結構及其形成方法,其於S/D接點與閘極之間具有改良的電性絕緣。
本揭露一實施例提供之半導體裝置的形成方法,包括:形成第一閘極結構於基板上,第一閘極結構包括第一閘極、第一絕緣蓋層位於第一閘極上、多個第一側壁間隔物位於第一閘極與第一絕緣蓋層的相反兩側面上、以及多個第二側壁間隔物位於第一側壁間隔物上,且第一閘極結構沿著第一方向延伸;形成第一源極/汲極區;形成第一絕緣層於第一源極/汲
極區上;在形成第一絕緣層後,使第一絕緣蓋層與第二側壁間隔物凹陷,並使第一側壁間隔物凹陷,以形成第一凹陷空間;以及形成第一保護層於第一凹陷空間中,其中第一凹陷空間沿著第二方向的剖面為π形,其具有頂部位於第一絕緣蓋層與第二側壁間隔物上,以及兩個腳部位於第一側壁間隔物上,其中第二方向垂直於該第一方向,以及第一保護層沿著第二方向的剖面為π形,其具有頂部與兩個腳部。
本揭露一實施例提供之半導體裝置的形成方法,包括:形成第一閘極結構與第二閘極結構於基板上,第一閘極結構包括第一閘極、第一絕緣蓋層位於第一閘極上、多個第一側壁間隔物位於第一閘極與第一絕緣蓋層之相反兩側面上、以及多個第一蝕刻停止層位於第一側壁間隔物上,第二閘極結構包括第二閘極、第二絕緣蓋層位於第二閘極上、多個第二側壁間隔物位於第二閘極與第二絕緣蓋層之相反兩側面上、以及多個第二蝕刻停止層位於第二側壁間隔物上,且第一閘極結構與第二閘極結構沿著第一方向延伸;形成第一源極/汲極區於第一閘極結構與第二閘極結構之間的區域中;形成第一絕緣層於第一源極/汲極區上以及第一閘極結構與第二閘極結構之間;在形成第一絕緣層後,使第一絕緣蓋層、第二絕緣蓋層、第一蝕刻停止層、與第二蝕刻停止層凹陷,並使第一側壁間隔物與第二側壁間隔物凹陷,以形成第一凹陷空間於第一閘極上,與第二凹陷空間於第二閘極上;以及形成第一保護層於第一凹陷空間中,以及第二保護層於第二凹陷空間中,其中第一凹陷空間與第二凹陷空間沿著第二方向的剖面各自為π形,其具有頂
部與兩個腳部,且第二方向垂直於第一方向;以及第一保護層與第二保護層沿著第二方向的剖面各自為π形,其具有頂部與兩個腳部。
本揭露一實施例提供之半導體裝置,包括:第一閘極結構,包括第一閘極、第一絕緣蓋層位於第一閘極上、多個第一側壁間隔物位於第一閘極與第一絕緣蓋層之相反兩側面上、以及多個第二側壁間隔物位於第一側壁間隔物上,且第一閘極結構沿著第一方向延伸;以及第一保護層,形成於第一絕緣蓋層、第一側壁間隔物、與第二側壁間隔物上,其中第一保護層沿著第二方向的剖面為π形,其具有頂部與兩個腳部,且第二方向垂直於第一方向。
D1、D2‧‧‧深度
H1、H2、H3‧‧‧高度
T1、T2‧‧‧厚度
X1-X1‧‧‧剖線
5‧‧‧通道層
10、330‧‧‧金屬閘極結構
12‧‧‧界面介電層
14‧‧‧閘極介電層
16‧‧‧功函數調整層
18‧‧‧層狀物
20、340‧‧‧絕緣蓋層
25、26、37‧‧‧凹陷空間
30、350‧‧‧側壁間隔物
35‧‧‧CESL
40‧‧‧第一ILD層
50、360‧‧‧源極/汲極區
61、63、73、75‧‧‧腳部
62、72‧‧‧頂部
70‧‧‧保護層
85‧‧‧接點孔
90‧‧‧導電材料
95‧‧‧源極/汲極接點
100‧‧‧S/D絕緣蓋層
105‧‧‧ESL
108‧‧‧第三ILD層
110、115‧‧‧通孔插塞
120‧‧‧第一金屬線路
125‧‧‧第二金屬線路
300‧‧‧基板
310‧‧‧鰭狀結構
315‧‧‧通道區
320‧‧‧隔離絕緣層
370‧‧‧ILD層
第1A圖係本揭露一實施例中,半導體裝置於一製程階段的上視圖。
第1B圖係第1A圖中剖線X1-X1的剖視圖。
第1C圖係第1B圖中的閘極結構之放大圖。
第1D圖係本揭露一實施例中,半導體裝置於一製程階段的透視圖。
第2至10圖係本揭露一實施例中,半導體裝置於多個製程階段中,沿著第1A圖中剖線X1-X1的剖視圖。
可以理解的是,下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以
簡化本發明而非侷限本發明。舉例來說,單元尺寸並不限於揭露的範圍或數值,而可依製程條件及/或裝置所需的性質而定。此外,形成第一構件於第二構件上的敘述包含兩者直接接觸,或兩者之間隔有其他額外構件而非直接接觸。為了簡化與清楚說明,可依不同比例任意繪示多種結構。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。元件亦可轉動90°或其他角度,因此方向性用語僅用以說明圖示中的方向。此外,用語「之組成為」指的是「包括」或者「由...組成」。
第1A與1B圖係本揭露一實施例中,半導體裝置於一製程階段的圖式。第1A圖係上視圖,而第1B圖係第1A圖中剖線X1-X1的剖視圖。
第1A與1B圖係形成金屬閘極結構後的半導體裝置結構。在第1A與1B圖中,金屬閘極結構10形成於通道層5(比如部份的鰭狀結構)上,而絕緣蓋層20在Z方向位於金屬閘極結構10上。金屬閘極結構10沿著Y方向延伸,並沿著X方向排列。在某些實施例中,金屬閘極結構10的厚度介於約15nm至約50nm之間。在某些實施例中,絕緣蓋層20之厚度介於約10nm至約30nm之間。在其他實施例中,絕緣蓋層20之厚度介於約15nm至約20nm之間。側壁間隔物30(可稱作第一側壁)位於金屬閘極結構10與絕緣蓋層20的側壁上。在某些實施例中,側壁
間隔物30其底部的膜厚介於約3nm至約15nm之間。在其他實施例中,側壁間隔物30其底部的膜厚介於約4nm至約8nm之間。金屬閘極結構10、絕緣蓋層20、與側壁間隔物0之組合可統稱為閘極結構。此外,源極/汲極區50與閘極結構相鄰,且閘極結構之間的空間填有第一ILD(層間介電)層40。此外,CESL(接點蝕刻停止層)35形成於側壁間隔物30上,如第1A與1B圖所示。CESL 35亦可稱作第二側壁。在某些實施例中,CESL 35之膜厚介於約3nm至約15nm之間。在其他實施例中,CESL 35介於約4nm至約8nm之間。
第1C圖係閘極結構的放大圖。金屬閘極結構10包含一或多層的層狀物18,其可為金屬材料如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi、CoSi、或其他導電材料。閘極介電層14位於通道層5與金屬閘極之間,其包含一或多層的金屬氧化物如高k的金屬氧化物。用於高k介電物的金屬氧化物包含下述金屬之氧化物:Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、及或上述之混合物。在某些實施例中,界面介電層12可形成於通道層5與閘極介電層14之間,其組成可為氧化矽。
在某些實施例中,一或多個功函數調整層16夾設於閘極介電層14與層狀物18之間。功函數調整層16之組成可為導電材料,比如單層的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi、或TiAlC;或者上述材料之多層結構。對n型通道FET而言,功函數調整層16可為一或多層的
TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi、或TaSi。對p型通道FET而言,功函數調整層16可為一或多層的TiAlC,Al,TiAl、TaN、TaAlC、TiN、TiC、或Co。
絕緣蓋層20包含一或多層的絕緣材料如氮化矽為主的材料,比如SiN、SiCN、或SiOCN。側壁間隔物30與絕緣材蓋層20之材料組成不同,且可包含一或多層的絕緣材料如氧化矽為主的材料(比如SiOC與SiOCN)或介電常數介於約3至約4之間的低k材料。在某些實施例中,CESL 35與絕緣蓋層20之材料組成不同,且可包含一或多層的絕緣材料如氮化矽為主的材料,比如SiN、SiCN、或SiOCN。在某些實施例中,CESL 35與絕緣蓋層20之材料組成相同。第一ILD層40包含一或多層的絕緣材料如氧化矽為主的材料,比如二氧化矽或SiON。
在此實施例中,側壁間隔物30之材料與CESL 35、絕緣蓋層20、及第一ILD層40之材料不同,因此可選擇性地蝕刻個別層狀物。在一實施例中,側壁間隔物30之組成為SiOC或SiOCN,絕緣蓋層20與CESL 35之組成為SiN,且第一ILD層之組成為SiO2。
在此實施例中,採用閘極置換製程形成鰭狀場效電晶體(FinFET)。
第1D圖係FinFET結構的透視圖。
首先,鰭狀結構310係形成於基板300上。鰭狀結構310包含底部區與較上區(如通道區315)。舉例來說,基板300可為p型矽基板,其掺雜濃度介於約1×1015cm-3至約1×1018cm-3之間。在其他實施例中,基板300可為n型基板,其掺雜濃度介
於約1×1015cm-3至約1×1018cm-3之間。在其他實施例中,基板300可包含另一半導體元素如鍺,亦可為包含IV-IV族的半導體化合物如SiC或SiGE,包含III-V族的半導體化合物如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP,或上述之組合。在一實施例中,基板300為SOI(絕緣層上矽)基板的矽層。
在形成鰭狀結構310後,形成隔離絕緣層320於鰭狀結構310上。隔離絕緣層320包含一或多層的絕緣材料如氧化矽、氮氧化矽、或氮化矽,其形成方法可為LPCVD(低壓化學氣相沉積)、電漿CVD、或可流動CVD。隔離絕緣層可為一或多層的旋轉塗佈玻璃(SOG)、氧化矽、SiON、SOCN、及/或掺雜氟的矽酸鹽玻璃(FSG)。
在形成隔離絕緣層320於鰭狀結構310上後,進行平坦化製程以移除部份的隔離絕緣層320。平坦化製程可包含化學機械研磨(CMP)及/或回蝕刻製程。接著進一步移除隔離絕緣層320使其凹陷,以露出鰭狀結構310的上表面。
虛置閘極結構係形成於露出的鰭狀結構上。虛置閘極結構包含虛置閘極層與虛置閘極介電層。虛置閘極層之組成為多晶矽。側壁間隔物350包含一或多層的絕緣材料,其亦形成於虛置閘極層的側壁上。在形成虛置閘極結構後,虛置閘極結構未覆蓋的鰭狀結構310將凹陷至低於隔離絕緣層320的上表面。接著以磊晶成長法形成源極/汲極區360於凹陷的鰭狀結構上。源極/汲極區360可包含應力材料,以施加應力至通道區315。
接著形成ILD(層間介電)層370於虛置閘極結構與源極/汲極區360上。在平坦化步驟後,虛置閘極結構被移除以形成閘極空間。接著將金屬閘極結構330形成於閘極空間中,且金屬閘極結構330包含金屬閘極與閘極介電層(如高k介電層)。此外,絕緣蓋層340形成於金屬閘極結構330上。CESL(未圖示於第1D圖中)形成於側壁間隔物350上。在第1D圖中,截斷部份的金屬閘極結構330、絕緣蓋層340、側壁間隔物350、與ILD層370以顯示下方的結構。
第1D圖中的金屬閘極結構330、絕緣蓋層340、側壁間隔物350、源極/汲極區360、與ILD層370,實質上分別對應第1A與1B中的金屬閘極結構10、絕緣蓋層20、側壁間隔物30、源極/汲極區50、與第一ILD層40。
第2至10圖係本揭露一實施例中,半導體裝置於多個製程階段中,沿著第1A圖中剖線X1-X1的剖視圖。可以理解的是,在第2至10圖的製程之前、之中、或之後可進行額外步驟,且可置換或省略某些下述步驟於其他實施例。下述步驟/製程的順序可交換。
如第2圖所示,以乾蝕刻及/或溼蝕刻使絕緣蓋層20與CESL 35凹陷。由於絕緣蓋層20與CESL 35之組成為相同材料,且不同於側壁間隔物30與第一ILD層40之材料組成,因此可實質上選擇性地蝕刻絕緣蓋層20與CESL 35。在某些實施例中,在凹陷的絕緣蓋層20上之凹陷空間25,其自第一ILD層40之上表面向下的深度D1介於約10nm至約30nm之間。在其他實施例中,深度D1介於約15nm至約25nm之間。位於凹陷的CESL
35上之凹陷空間26,其深度與前述之深度D1實質上相同。然而凹陷空間26之深度可小於或大於深度D1,且兩者之差距大於約1nm。
如第3圖所示,採用乾蝕刻及/或濕蝕刻使側壁間隔物30凹陷,以形成凹陷空間37。由於側壁間隔物30的材料組成不同於絕緣蓋層20、CESL 35、與第一ILD層40的材料組成,因此可實質上選擇性地蝕刻側壁間隔物30。如第3圖所示,π形的凹陷在沿著X方向的剖面中具有頂部62與兩個腳部61與63。在某些實施例中,凹陷空間37自第一ILD層40之上表面向下的深度D2,比深度D1多至少5nm,且介於約20nm至約50nm之間。在其他實施例中,深度D2介於約10nm至約30nm之間。凹陷空間37的底部具有自閘極結構10(如層狀物18)之上表面向上的高度H1,其介於約5nm至約30nm之間。
如第3圖所示,深度D2大於深度D1,且兩者差距大於約3nm。值得注意的是,可在使側壁間隔物30凹陷之後,再使絕緣蓋層20與CESL 35凹陷。
保護層係實質上形成於凹陷空間25、26、與37中。如第4圖所示,一或多層的保護層70如絕緣材料係形成於第3圖之結構上。接著進行平坦化步驟如回蝕刻及/或化學機械研磨(CMP)製程,以形成第5圖所示之結構。絕緣材料之形成方法可為CVD、物理氣相沉積(PVD)如濺鍍、原子層沉積(ALD)、或其他合適的成膜方法。在平坦化步驟後,某些實施例之保護層70自絕緣蓋層20之上表面向上之高度H2介於約5nm至約20nm之間。在其他實施例中,高度H2介於約7nm至約15nm之間。
保護層70之材料組成與氧化矽為主的材料相較具有高抗蝕刻性。在某些實施例中,保護層70可採用氮化鋁、氮氧化鋁、氧化鋁、氧化鈦、與氧化鋯中至少一者。
如第5圖所示,π形的保護層70在沿著X方向的剖面具有頂部72與兩個腳部73與75。在某些實施例中,腳部73與75之高度H3介於約5nm至約10nm之間。
在形成保護層70後,以適當的微影與蝕刻步驟移除源極/汲極區50上的第一ILD層40,以形成接點孔85露出至少一源極/汲極區50,如第6圖所示。
在某些實施例中,完全移除第一ILD層40後,再形成第二ILD層於閘極結構上。接著以微影與蝕刻步驟形成接點孔85以露出至少一源極/汲極區50,如第6圖所示。
如第6圖所示,在蝕刻形成接點孔85時,亦蝕刻部份保護層70。然而保護層70在接點孔蝕刻製程中的抗蝕刻性高於CESL的抗蝕刻性,因此可最小化CESL 35的蝕刻量。此外,由於保護層70的關係,形成接點孔的蝕刻製程不會蝕刻絕緣蓋層20與側壁間隔物30。如此一來,絕緣蓋層20的較上端維持實質上垂直的角落。由於絕緣蓋層20被保護而不被蝕刻,可避免金屬閘極10與源極/汲極接點95(見第8與9圖)之間的短路。
在形成接點孔85後,形成導電材料90於第6圖之結構上。如第7圖所示,一或多層的導電材料90如鎢、鈦、鈷、鉭、銅、鋁、鎳、上述之矽化物、或其他合適材料係形成於第6圖之結構上。接著進行平坦化步驟如CMP製程,以得第8圖所示之結構。兩相鄰閘極結構之間的空間填有導電材料,以形成
接觸源極/汲極區50的源極/汲極接點95。
在此實施例中,未移除且保留保護層70,如第9圖所示。在此例中,保護層70可作為CMP製程的研磨停止層。源極/汲極接點95接觸源極/汲極區50。在某些實施例中,CMP製程或後續用於S/D絕緣蓋層之CMP製程將進一步移除保護層70。
在形成源極/汲極接點95後,移除較上部份的源極/汲極接點95使其凹陷,並形成S/D絕緣蓋層100如第9圖所示。形成絕緣材料的毯覆層如SiC或SiOC後,進行CMP步驟以形成S/D絕緣蓋層100。在第9圖中,某些實施例之π形的保護層70其頂部的厚度T1介於約1nm至約5nm之間。此外,π形的保護層70其腳部的厚度T2大於頂部的厚度T1。在某些實施例中,厚度T2與厚度T1的比例(T2/T1)介於約1至約10之間。在其他實施例中,T2/T1介於約2至約6之間。
接著形成ESL(蝕刻停止層)105與第三ILD層108於第9圖所示之結構上。接著進行圖案化步驟以形成通孔。將一或多層的導電材料填入通孔,以形成通孔插塞110與115及其上的第一金屬線路120與第二金屬線路125,如第10圖所示。第一金屬線路120、第二金屬線路125、及通孔插塞110與115之形成方法可為雙鑲嵌製程。在某些實施例中,可省略ESL 105。
可以理解的是,可對第10圖之裝置進行後續CMOS製程,以形成多種結構如內連線金屬層、介電層、保護層、或類似物。
此處所述之多種實施例或實例與現有技術相較,
具有多種優勢如下。舉例來說,本揭露實施例中的保護層70形成於金屬閘極、側壁間隔物、與絕緣蓋層上,可避免蝕刻形成接點孔時同時蝕刻絕緣蓋層,進而避免金屬閘極與源極/汲極接點之間的短路。
應理解的是,上述內容不必提及所有的優點,所有實施例或實例不需包含特定優點,且其他實施例或實例可具有不同優點。
在本揭露一實施例之半導體裝置的形成方法中,形成第一閘極結構於基板上。第一閘極結構包括第一閘極、第一絕緣蓋層位於第一閘極上、多個第一側壁間隔物位於第一閘極與第一絕緣蓋層的相反兩側面上、以及多個第二側壁間隔物位於第一側壁間隔物上。第一閘極結構沿著第一方向延伸。形成第一源極/汲極區。形成第一絕緣層於第一源極/汲極區上。在形成第一絕緣層後,使第一絕緣蓋層與第二側壁間隔物凹陷,並使第一側壁間隔物凹陷,以形成第一凹陷空間。形成第一保護層於第一凹陷空間中。第一凹陷空間沿著第二方向的剖面為π形,其具有一頂部位於第一絕緣蓋層與第二側壁間隔物上,以及兩個腳部位於第一側壁間隔物上,其中第二方向垂直於第一方向。第一保護層沿著第二方向的剖面為π形,其具有頂部與兩個腳部。
在本揭露一實施例之半導體裝置的形成方法中,形成第一閘極結構與第二閘極結構於基板上。第一閘極結構包括第一閘極、第一絕緣蓋層位於第一閘極上、多個第一側壁間隔物位於第一閘極與第一絕緣蓋層之相反兩側面上、以及多個
第一蝕刻停止層位於第一側壁間隔物上。第二閘極結構包括第二閘極、第二絕緣蓋層位於第二閘極上、多個第二側壁間隔物位於第二閘極與第二絕緣蓋層之相反兩側面上、以及多個第二蝕刻停止層位於第二側壁間隔物上。第一閘極結構與第二閘極結構沿著第一方向延伸。形成第一源極/汲極區於第一閘極結構與第二閘極結構之間的區域中。形成第一絕緣層於第一源極/汲極區上以及第一閘極結構與第二閘極結構之間。在形成第一絕緣層後,使第一絕緣蓋層、第二絕緣蓋層、第一蝕刻停止層、與第二蝕刻停止層凹陷,並使第一側壁間隔物與第二側壁間隔物凹陷,以形成第一凹陷空間於第一閘極上,與第二凹陷空間於第二閘極上。形成第一保護層於第一凹陷空間中,以及第二保護層於第二凹陷空間中。第一凹陷空間與第二凹陷空間沿著一第二方向的剖面各自為π形,其具有頂部與兩個腳部,且第二方向垂直於第一方向。第一保護層與第二保護層沿著第二方向的剖面各自為π形,其具有頂部與兩個腳部。
本揭露又一實施例中的半導體裝置,包括第一閘極結構位於基板上且沿著第一方向延伸。第一閘極結構包括第一閘極、第一絕緣蓋層位於第一閘極上、多個第一側壁間隔物位於第一閘極與第一絕緣蓋層之相反兩側面上、以及多個第二側壁間隔物位於第一側壁間隔物上。半導體裝置亦包含第一保護層形成於第一絕緣蓋層、第一側壁間隔物、與第二側壁間隔物上。第一保護層沿著第二方向的剖面為π形,其具有頂部與兩個腳部,且第二方向垂直於第一方向。
上述實施例或實例之特徵有利於本技術領域中具
有通常知識者理解本揭露實施例。本技術領域中具有通常知識者應理解可採用本揭露實施例作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本揭露實施例之精神與範疇,並可在未脫離本揭露實施例之精神與範疇的前提下進行改變、替換、或更動。
Claims (9)
- 一種半導體裝置的形成方法,包括:形成一第一閘極結構於一基板上,該第一閘極結構包括一第一閘極、一第一絕緣蓋層位於該第一閘極上、多個第一側壁間隔物位於該第一閘極的相反兩側面上與該第一絕緣蓋層的相反兩側面上、以及多個第二側壁間隔物位於該些第一側壁間隔物上,且該第一閘極結構沿著一第一方向延伸;形成一第一源極/汲極區;形成一第一絕緣層於該第一源極/汲極區上;在形成該第一絕緣層後,使該第一絕緣蓋層與該些第二側壁間隔物凹陷,並使該些第一側壁間隔物凹陷,以形成一第一凹陷空間;以及形成一第一保護層於該第一凹陷空間中;其中該第一凹陷空間沿著一第二方向的剖面為π形,其具有一頂部位於該第一絕緣蓋層與該些第二側壁間隔物上,以及兩個腳部位於該些第一側壁間隔物上,其中該第二方向垂直於該第一方向;以及該第一保護層沿著該第二方向的剖面為π形,其具有一頂部與兩個腳部。
- 如申請專利範圍第1項所述之半導體裝置的形成方法,其中該第一絕緣蓋層與該第二側壁間隔物之材料組成相同,且與該第一側壁間隔物之材料組成不同。
- 如申請專利範圍第1項所述之半導體裝置的形成方法,在形成該第一保護層之步驟後,更包括:移除該源極/汲極區上的部份該第一絕緣層,以形成一接點孔;將一導電材料填入該接點孔;使填入的該導電材料凹陷;以及形成一第二絕緣層於凹陷的該導電材料上;其中形成該接點孔之步驟不蝕刻該第一絕緣蓋層。
- 一種半導體裝置的形成方法,包括:形成一第一閘極結構與一第二閘極結構於一基板上,該第一閘極結構包括一第一閘極、一第一絕緣蓋層位於該第一閘極上、多個第一側壁間隔物位於該第一閘極與該第一絕緣蓋層之相反兩側面上、以及多個第一蝕刻停止層位於該些第一側壁間隔物上,該第二閘極結構包括一第二閘極、一第二絕緣蓋層位於該第二閘極上、多個第二側壁間隔物位於該第二閘極與該第二絕緣蓋層之相反兩側面上、以及多個第二蝕刻停止層位於該些第二側壁間隔物上,且該第一閘極結構與該第二閘極結構沿著一第一方向延伸;形成一第一源極/汲極區於該第一閘極結構與該第二閘極結構之間的區域中;形成一第一絕緣層於該第一源極/汲極區上以及該第一閘極結構與該第二閘極結構之間;在形成該第一絕緣層後,使該第一絕緣蓋層、該第二絕緣蓋層、該第一蝕刻停止層、與該第二蝕刻停止層凹陷,並使該些第一側壁間隔物與該些第二側壁間隔物凹陷,以形成一第一凹陷空間於該第一閘極上,與一第二凹陷空間於該第二閘極上;以及形成一第一保護層於該第一凹陷空間中,以及一第二保護層於該第二凹陷空間中;其中該第一凹陷空間與該第二凹陷空間沿著一第二方向的剖面各自為π形,其具有一頂部與兩個腳部,且該第二方向垂直於該第一方向;以及該第一保護層與該第二保護層沿著該第二方向的剖面各自為π形,其具有一頂部與兩個腳部。
- 如申請專利範圍第4項所述之半導體裝置的形成方法,其中該第一絕緣蓋層、該第二絕緣蓋層、該第一蝕刻停止層、與該第二蝕刻停止層之材料組成相同,而與該第一側壁間隔物與該第二側壁間隔物之材料組成不同。
- 如申請專利範圍第4項所述之半導體裝置的形成方法,在形成該第一保護層之步驟後更包括:移除該源極/汲極區上的該第一絕緣層,以形成一接點孔;將一導電材料填入接點孔;使填入的該導電材料凹陷;以及形成一第二絕緣層於凹陷的該導電材料上;其中形成該導電孔之步驟不蝕刻該第一絕緣蓋層與該第二絕緣蓋層。
- 一種半導體裝置,包括:一第一閘極結構,包括一第一閘極、一第一絕緣蓋層位於該第一閘極上、多個第一側壁間隔物位於該第一閘極的相反兩側面上與該第一絕緣蓋層的相反兩側面上、以及多個第二側壁間隔物位於該些第一側壁間隔物上,且該第一閘極結構沿著一第一方向延伸;以及一第一保護層,形成於該第一絕緣蓋層、該些第一側壁間隔物、與該些第二側壁間隔物上;其中該第一保護層沿著一第二方向的剖面為π形,其具有一頂部與兩個腳部,且該第二方向垂直於該第一方向,其中該些腳部的底部接觸該些第一側壁間隔物的上表面。
- 如申請專利範圍第7項所述之半導體裝置,其中該第一絕緣蓋層與該些第二側壁間隔物之組成包括SiN,且該些第一側壁間隔物之組成包含SiOC與SiOCN中至少一者。
- 如申請專利範圍第8項所述之半導體裝置,其中該第一保護層之組成包括氮化鋁、氮氧化鋁、氧化鋁、氧化鈦、與氧化鋯中至少一者。
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TW201724519A (zh) | 2017-07-01 |
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KR101960573B1 (ko) | 2019-03-20 |
CN107017297B (zh) | 2020-05-01 |
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