CN103594495A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103594495A
CN103594495A CN201210293241.0A CN201210293241A CN103594495A CN 103594495 A CN103594495 A CN 103594495A CN 201210293241 A CN201210293241 A CN 201210293241A CN 103594495 A CN103594495 A CN 103594495A
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substrate
source
drain area
semiconductor device
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马小龙
殷华湘
付作振
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Institute of Microelectronics of CAS
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Priority to US13/812,499 priority patent/US8889519B2/en
Priority to PCT/CN2012/001376 priority patent/WO2014026305A1/zh
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Abstract

本发明公开了一种半导体器件，包括衬底、衬底上的栅极堆叠结构、栅极堆叠结构两侧衬底中的源漏区、衬底中源漏区之间的沟道区，其特征在于：源漏区中至少一个包括GeSn合金。依照本发明的半导体器件及其制造方法，通过注入前驱物然后激光快速退火，形成了高Sn含量的GeSn应力源漏区，有效提高了沟道区器件载流子迁移率并进一步提高了器件驱动能力。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体集成电路制造领域，更具体地，涉及一种具有GeSn应力源漏区的MOSFET及其制造方法。
背景技术
随着集成电路工艺持续发展，特别是器件尺寸不断等比例缩减，器件的各个关键参数例如阈值电压等也随之减小，功耗减小、集成度提高这些优点促进了器件整体性能提高。然而与此同时，器件的驱动能力却受制于传统的硅材料工艺的限制，载流子迁移率较低，面临了器件驱动能力相比而言不足的问题。因此，高迁移率沟道器件在未来具有重要应用背景。
现有的高迁移率沟道器件通常是采用Si1-xGex或Si1-xCx来作为应力源漏区向Si的沟道区施加应力，或者直接采用这些材料作为衬底和沟道区。在Si1-xGex中引入压应变能够进一步提高空穴的迁移率，相应地在在Si1-xCx中引入张应变能够进一步提高电子的迁移率。然而，这两种材料晶格常数与Si差别仍不够大，能够提供的应变有限，难以应用在需要更高驱动能力的器件中。
一种可选的替代材料是GeSn合金，该薄膜具有很高的载流子迁移率，并且可以通过调节Sn的含量调节合金的能带结构，因此广泛应用于先进的CMOS器件和光电子器件中。
然而传统的GeSn合金需要用分子束外延或者CVD，目前仍不成熟或者与CMOS不兼容。此外，由于Sn在Ge中的平衡固溶度非常的低，因此用常规的方法很难得到Sn的含量大于1％的Ge1-xSnx。
此外，其他高迁移率材料，诸如GaAs、InSb等也存在类似问题，难以与Si基的CMOS工艺兼容。
发明内容
有鉴于此，本发明的目的在于提供一种具有GeSn应力源漏区的MOSFET及其制造方法，克服上述传统工艺的缺陷，有效提高器件沟道区载流子迁移率。
实现本发明的上述目的，是通过提供一种半导体器件，包括衬底、衬底上的栅极堆叠结构、栅极堆叠结构两侧衬底中的源漏区、衬底中源漏区之间的沟道区，其特征在于：源漏区中至少一个包括GeSn合金。
其中，沟道区包括Si和/或SiGe。
其中，GeSn合金中Sn含量大于0并且小于30％。
其中，源漏区上还包括材质相同的提升源漏区。
其中，源漏区上还包括金属化源漏接触层。
本发明还提供了一种半导体器件制造方法，包括：在衬底上形成栅极堆叠结构；在栅极堆叠结构至少一侧的衬底中注入前驱物；激光快速退火，使得前驱物反应形成GeSn合金，构成源漏区。
其中，GeSn合金中Sn含量大于0并且小于30％。
其中，注入前驱物的步骤进一步包括：执行非晶化离子注入，在衬底中形成非晶化区；在非晶化区中注入Sn。
其中，非晶化离子注入的离子包括Ge、B、Ga、In及其组合。
其中，Sn的注入剂量为5×1015～1×1017cm-2。
其中，在注入前驱物之后、在激光快速退火之前，在前驱物上形成保护层。
其中，在激光快速退火工艺中，激光处理的脉冲个数为1～100，能量密度为100mJ/cm2～1J/cm2，激光波长为157nm～10.6μm，脉冲时间宽度为1ns～10μs。
依照本发明的半导体器件及其制造方法，通过注入前驱物然后激光快速退火，形成了高Sn含量的GeSn应力源漏区，有效提高了沟道区器件载流子迁移率并进一步提高了器件驱动能力。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图3为根据本发明实施例的半导体器件制造方法各步骤的剖面示意图；
以及图4为根据本发明实施例的半导体器件的剖视图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”、“厚”、“薄”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
根据本发明实施例，参照图1至图3，形成了具有GeSn应力源漏区的常规MOSFET器件结构。
首先参照图1，在衬底1上形成栅极堆叠结构2和栅极侧墙3。
提供衬底1，其可以是体Si、SOI、体Ge、GeOI、SiGe、GeSb，也可以是III-V族或者II-VI族化合物半导体衬底，例如GaAs、GaN、InP、InSb等等。此外，也可以是玻璃、塑料、树脂等透明基板。为了与现有的CMOS工艺兼容以应用于大规模数字集成电路制造，衬底1优选地为体Si(单晶硅晶片)、SOI晶片。
在衬底1中先刻蚀形成浅沟槽，然后采用快速热氧化(RTO)、LPCVD、PECVD、HDPCVD等常规方法，在浅沟槽中沉积填充氧化物(例如氧化硅)从而形成浅沟槽隔离(STI)1A。STI 1A包围的衬底区域即构成器件的有源区。
优选地，在STI 1A包围的有源区内形成埋层(未示出)，埋层用于增强源漏区向沟道区施加的应力或者增强沟道区自身的应力，从而进一步提高载流子迁移率。埋层材质是晶格常数介于衬底Si与稍后的源漏区GeSn之间的材料，例如是SiGe。形成埋层的方法可以是可选地在衬底1上沉积缓冲层、在衬底/缓冲层上外延生长SiGe埋层、以及可选地在埋层上再外延生长Si或者Ge顶层。此外，形成埋层的方法还可以是将Ge离子注入到Si衬底中一定深度，随后退火使得注入的掺杂离子与衬底反应形成SiGe埋层。埋层与衬底1表面的距离也即埋层深度，依照沟道区应力分布需要而通过控制外延或者注入工艺参数而设定，埋层深度例如是10～30nm。
通过LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常规方法，在衬底1上依次沉积栅极绝缘层2A、栅极导电层2B，并随后刻蚀形成栅极堆叠结构2A/2B。在前栅工艺中，栅极堆叠结构将一直保留，栅极绝缘层2A是高k材料，包括但不限于氮化物(例如SiN、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))；栅极导电层2B是金属和/或金属氮化物，其中金属包括Al、Ti、Cu、Mo、W、Ta，金属氮化物包括TiN、TaN。在后栅工艺中，此时的栅极堆叠结构是假栅极堆叠结构，在后续工艺中将去除，栅极绝缘层2A包括氧化硅、氮氧化硅，栅极导电层2B是多晶硅、非晶硅。层2A厚度例如是1～5nm，层2B厚度例如是10～100nm。
在衬底1以及栅极堆叠结构2A/2B上通过PECVD、HDPCVD等常规方法沉积氮化硅、氮氧化硅、类金刚石无定形碳(DLC)等介质材料并刻蚀形成栅极侧墙3。
接着，参照图2，执行掺杂注入，以栅极侧墙3为掩模，在栅极侧墙3至少一侧的衬底1中注入前驱物，形成前驱物的掺杂区1B。
首先执行非晶化离子注入(PAI)。注入能量例如是10～200KeV，注入剂量例如是1×1015～1×1017cm-2。当衬底1为Si时，注入离子是Ge。注入的Ge离子破坏了待形成源漏区的衬底1表面一定区域(例如距离表面10～20nm)内的晶格，使其非晶化而构成非晶化区(未示出)，以利于稍后进一步离子注入、以及退火时反应形成合金。
优选地，非晶化离子注入之前和/或之后，进一步在非晶化区中注入B、Ga、In等杂质离子，以调整源漏区导电类型和浓度。
此外，当衬底1为SiGe或者是含有SiGe埋层的Si时(也即衬底本身含有Ge)，非晶化注入离子是B、Ga、In等杂质离子，在非晶化的同时也调整源漏区导电类型和浓度，因此不再额外地执行上述调节源漏导电类型和浓度的杂质注入。
非晶化离子注入之后，在非晶化区中注入Sn。注入能量例如是20～200KeV，注入剂量例如是5×1015～1×1017cm-2并优选1×1016cm-2。至此，非晶化区中至少包含了Ge和Sn两种掺杂离子以用作前驱物，从而构成了前驱物的掺杂区1B。
此外，也可以在注入Sn之后再注入B、Ga、In等杂质离子。
优选地，在前驱物掺杂区1B上形成保护层(未示出)。例如采用PECVD、LPCVD等方法并且降低沉积温度从而形成低温保护层，也即低温沉积保护层，例如低温氧化硅(LTO)，沉积温度例如低于400℃以避免此时Ge与Sn提前反应。或者通过旋涂、丝网印刷、喷涂等方法，采用PSG、BPSG等玻璃材料，甚至可以是光刻胶等树脂材料来形成保护层，用于避免稍后的激光处理过度而损坏材料。自然，如果能良好调整激光处理参数，保护层也可以省略。
然后，参照图3，执行激光快速退火，使得前驱物的掺杂区1B中Ge与Sn反应形成GeSn，从而构成GeSn的源漏区4。采用激光脉冲照射前驱物掺杂区1B，使得至少包含Ge与Sn这两种前驱物的掺杂区1B表面快速升温融化并且相互反应，并且在冷却的过程中以相同于衬底1和/或SiGe埋层的晶向结晶，最终形成Ge1-xSnx合金，其晶格常数大于沟道材料的晶格常数，沿载流子输运方向引入压应变，提高载流子的迁移率。此外，GeSn合金也可以减小器件的源漏接触电阻。激光处理的脉冲个数为m1(例如是1～100的整数)，能量密度为f1(例如100mJ/cm2～1J/cm2)，激光波长为157nm～10.6μm，脉冲时间宽度为t1(例如1ns～10μs)。调节上述激光脉冲参数，可以控制合金层的厚度以及Ge1-xSnx合金中Sn的含量(原子数目比)。优选地，0<x<0.3。
值得注意的是，虽然图1至图3所示为在栅极堆叠结构2两侧均形成了Ge1-xSnx合金的源漏区，但是实际上也可以仅在一侧形成，而另一侧则为普通的Si或者SiGe源漏区。
此后，参照图4，可以继续采用现有的前栅或者后栅工艺，完成MOSFET制造。例如在GeSn源漏区上形成金属硅化物或者金属锗化物的源漏金属化接触层5，以进一步减小源漏接触电阻。在整个器件上沉积低k材料的层间介质层(ILD)6。刻蚀ILD6形成源漏接触孔，直至暴露源漏金属化接触层5，在接触孔中沉积W、Cu、Al、Mo等金属以及TiN、TaN等金属氮化物而形成源漏接触塞7。值得注意的是，虽然图4所示结构中栅极堆叠结构为前栅工艺中平行层叠的栅极绝缘层2A与栅极导电层2B，但是也可以适用于后栅工艺，也即栅极绝缘层2A在栅极沟槽中包围栅极导电层2B的底面以及侧面(图4中未示出)。
由此，依照本发明实施例的半导体器件包括衬底、衬底上的栅极堆叠结构、栅极堆叠结构两侧衬底中的源漏区、衬底中源漏区之间的沟道区，其特征在于源漏区中至少一个包括Ge1-xSnx合金。此外，沟道区包括Si或者SiGe。
依照本发明的半导体器件及其制造方法，通过注入前驱物然后激光快速退火，形成了高Sn含量的GeSn应力源漏区，有效提高了沟道区器件载流子迁移率并进一步提高了器件驱动能力。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (12)

1.一种半导体器件，包括衬底、衬底上的栅极堆叠结构、栅极堆叠结构两侧衬底中的源漏区、衬底中源漏区之间的沟道区，其特征在于：源漏区中至少一个包括GeSn合金。
2.如权利要求1的半导体器件，其中，沟道区包括Si和/或SiGe。
3.如权利要求1的半导体器件，其中，GeSn合金中Sn含量大于0并且小于30％。
4.如权利要求1的半导体器件，其中，源漏区上还包括材质相同的提升源漏区。
5.如权利要求1的半导体器件，其中，源漏区上还包括金属化源漏接触层。
6.一种半导体器件制造方法，包括：
在衬底上形成栅极堆叠结构；
在栅极堆叠结构至少一侧的衬底中注入前驱物；
激光快速退火，使得前驱物反应形成GeSn合金，构成源漏区。
7.如权利要求6的半导体器件制造方法，其中，GeSn合金中Sn含量大于0并且小于30％。
8.如权利要求6的半导体器件制造方法，其中，注入前驱物的步骤进一步包括：
执行非晶化离子注入，在衬底中形成非晶化区；
在非晶化区中注入Sn。
9.如权利要求8的半导体器件制造方法，其中，非晶化离子注入的离子包括Ge、B、Ga、In及其组合。
10.如权利要求8的半导体器件制造方法，其中，Sn的注入剂量为5×1015～1×1017cm-2。
11.如权利要求6的半导体器件制造方法，其中，在注入前驱物之后、在激光快速退火之前，在前驱物上形成保护层。
12.如权利要求6的半导体器件制造方法，其中，在激光快速退火工艺中，激光处理的脉冲个数为1～100，能量密度为100mJ/cm2～1J/cm2，激光波长为157nm～10.6μm，脉冲时间宽度为1ns～10μs。
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